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authorYork Sun <yorksun@freescale.com>2014-02-10 13:59:42 -0800
committerTom Rini <trini@ti.com>2014-02-21 11:06:13 -0500
commit4e5b1bd0dff216b00d7ce9a5201dfe173805a06c (patch)
treed8f8e7ffda3f504d4d98b6f494f0c73eed1196fc /README
parent9c89614d3f1ea510d7fcb4a2b438fb3e0d58392c (diff)
driver/ddr: Change Freescale ARM DDR driver to support both big and little endian
Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
-rw-r--r--README6
1 files changed, 6 insertions, 0 deletions
diff --git a/README b/README
index 6668631bccc..413d6828292 100644
--- a/README
+++ b/README
@@ -486,6 +486,12 @@ The following options need to be configured:
PBI commands can be used to configure SoC before it starts the execution.
Please refer doc/README.pblimage for more details
+ CONFIG_SYS_FSL_DDR_BE
+ Defines the DDR controller register space as Big Endian
+
+ CONFIG_SYS_FSL_DDR_LE
+ Defines the DDR controller register space as Little Endian
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO