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authorPrabhakar Kushwaha <prabhakar@freescale.com>2014-01-13 11:28:04 +0530
committerYork Sun <yorksun@freescale.com>2014-01-21 14:02:41 -0800
commit690e425844511fe37d3315e86414d0a9e3accd1c (patch)
tree6fac7a0412bce228cbb9be8ea0929935e62c09e8 /README
parent3fdc827ca8a770848e8104c42cd6d8321d8c86ff (diff)
powerpc:Rename CONFIG_PBLRCW_CONFIG & CONFIG_SYS_FSL_PBL_PBI
Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG. Also add their details in README. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
-rw-r--r--README9
1 files changed, 9 insertions, 0 deletions
diff --git a/README b/README
index aea82be5b3e..176de61a331 100644
--- a/README
+++ b/README
@@ -472,6 +472,15 @@ The following options need to be configured:
Board config to use DDR3. It can be enabled for SoCs with
Freescale DDR3 controllers.
+ CONFIG_SYS_FSL_PBL_PBI
+ It enables addition of RCW (Power on reset configuration) in built image.
+ Please refer doc/README.pblimage for more details
+
+ CONFIG_SYS_FSL_PBL_RCW
+ It adds PBI(pre-boot instructions) commands in u-boot build image.
+ PBI commands can be used to configure SoC before it starts the execution.
+ Please refer doc/README.pblimage for more details
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO