diff options
| author | York Sun <yorksun@freescale.com> | 2014-03-27 17:54:47 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:48 -0700 |
| commit | 34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85 (patch) | |
| tree | f155ebdbac95a5ef637e7796ad22935029a56ce6 /README | |
| parent | 8d451a7129ee6820cc126c77f0f0a175a2cb2e8d (diff) | |
driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 13 |
1 files changed, 12 insertions, 1 deletions
@@ -458,6 +458,9 @@ The following options need to be configured: CONFIG_SYS_FSL_DDRC_GEN3 Freescale DDR3 controller. + CONFIG_SYS_FSL_DDRC_GEN4 + Freescale DDR4 controller. + CONFIG_SYS_FSL_DDRC_ARM_GEN3 Freescale DDR3 controller for ARM-based SoCs. @@ -473,7 +476,15 @@ The following options need to be configured: CONFIG_SYS_FSL_DDR3 Board config to use DDR3. It can be enabled for SoCs with - Freescale DDR3 controllers. + Freescale DDR3 or DDR3L controllers. + + CONFIG_SYS_FSL_DDR3L + Board config to use DDR3L. It can be enabled for SoCs with + DDR3L controllers. + + CONFIG_SYS_FSL_DDR4 + Board config to use DDR4. It can be enabled for SoCs with + DDR4 controllers. CONFIG_SYS_FSL_IFC_BE Defines the IFC controller register space as Big Endian |