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authorMichal Simek <michal.simek@xilinx.com>2022-02-23 16:17:40 +0100
committerMichal Simek <michal.simek@xilinx.com>2022-03-07 16:33:47 +0100
commitff7944829497ce94feb62268d0652487ea873ac2 (patch)
tree5141ac315b109201b78f3b6b9fbf5778e94fd274
parenta3efa53c01100fc1aa015c37a258a50142cca708 (diff)
arm64: zynqmp: Switch to ethernet-phy-id in kv260
Use ethernet-phy-id compatible string to properly describe phy reset on kv260 boards. Previous description wasn't correct because reset was done for mdio bus to operate and it was in this case used for different purpose which was eth phy reset. With ethernet-phy-id phy reset happens only for the phy via phy framework. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/73b64f1a2b873b4e26bd2b365364bdf313794ae2.1645629459.git.michal.simek@xilinx.com
-rw-r--r--arch/arm/dts/zynqmp-sck-kv-g-revA.dts6
-rw-r--r--arch/arm/dts/zynqmp-sck-kv-g-revB.dts6
2 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index f58ad69be3..9445dace73 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -168,16 +168,18 @@
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
- reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
reg = <1>;
+ compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
+ reset-assert-us = <100>;
+ reset-deassert-us = <280>;
+ reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
};
};
};
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 7236e03a5a..6ea950a13f 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -155,16 +155,18 @@
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
- reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
reg = <1>;
+ compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
+ reset-assert-us = <100>;
+ reset-deassert-us = <280>;
+ reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
};
};
};