diff options
| author | Emanuele Ghidoli <emanuele.ghidoli@toradex.com> | 2023-12-01 14:36:20 +0100 |
|---|---|---|
| committer | Emanuele Ghidoli <emanuele.ghidoli@toradex.com> | 2023-12-01 14:36:20 +0100 |
| commit | ff20984bc78933c081ab8f22a84dde8cdb38e8b9 (patch) | |
| tree | c626e16fdb2e6d51a7dbc27bad5a556a8549ea4a | |
| parent | 536d0d5eef241a80a352704d82f2284faac2b046 (diff) | |
| parent | 71b8c840ca61a4e11b2cdf63b0e6580ecb427912 (diff) | |
Merge tag '09.01.00.006' into toradex_ti-09.01.00.006
RC Release 09.01.00.006
162 files changed, 15691 insertions, 1204 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 32ea916be5..9197bd215f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1280,22 +1280,26 @@ dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-sk.dtb \ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \ k3-am642-r5-evm.dtb \ k3-am642-sk.dtb \ - k3-am642-r5-sk.dtb + k3-am642-r5-sk.dtb \ + k3-am642-evm-nand.dtbo dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ k3-am625-r5-sk.dtb \ k3-am62-lp-sk.dtb \ k3-am62-r5-lp-sk.dtb \ + k3-am62sip-r5-sk.dtb \ k3-am625-beagleplay.dtb \ k3-am625-r5-beagleplay.dtb - dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-r5.dtb -dtb-$(CONFIG_SOC_K3_AM625) += k3-am62a7-sk.dtb \ +dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \ k3-am62a7-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-sk.dtb \ + k3-am62p5-r5-sk.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi b/arch/arm/dts/am335x-evm-u-boot.dtsi index 82a483ae3e..42eeca8c04 100644 --- a/arch/arm/dts/am335x-evm-u-boot.dtsi +++ b/arch/arm/dts/am335x-evm-u-boot.dtsi @@ -23,10 +23,6 @@ status = "disabled"; }; -&usb0 { - dr_mode = "peripheral"; -}; - &i2c0 { bootph-all; }; diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts b/arch/arm/dts/k3-am62-r5-lp-sk.dts index ea6316c12e..2c3196a4a8 100644 --- a/arch/arm/dts/k3-am62-r5-lp-sk.dts +++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * AM62x LP SK dts file for R5 SPL - * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-am62-lp-sk.dts" @@ -19,12 +19,21 @@ clock-frequency = <133333333>; bootph-pre-ram; }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-pre-ram; + }; }; +/* &ospi0 { reg = <0x00 0x0fc40000 0x00 0x100>, <0x00 0x60000000 0x00 0x08000000>; }; +*/ &gpmc0 { /delete-property/ power-domains; diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index ead5c1ce48..87f6bfccda 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * AM625 SK dts file for R5 SPL - * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-am625-sk.dts" @@ -9,162 +9,14 @@ #include "k3-am62-ddr.dtsi" #include "k3-am625-sk-u-boot.dtsi" +#include "k3-am62x-r5-sk-common.dtsi" #include "k3-am625-sk-binman.dtsi" / { - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a53_0; - serial0 = &wkup_uart0; - serial3 = &main_uart1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - tick-timer = &main_timer0; - }; - memory@80000000 { device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - - bootph-pre-ram; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - }; - - a53_0: a53@0 { - compatible = "ti,am654-rproc"; - reg = <0x00 0x00a90000 0x00 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 135 0>; - clocks = <&k3_clks 61 0>; - assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; - assigned-clock-parents = <&k3_clks 61 2>; - assigned-clock-rates = <200000000>, <1200000000>; - ti,sci = <&dmsc>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <36>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 22>, - <&secure_proxy_main 23>; - bootph-pre-ram; - }; -}; - -&dmsc { - mboxes= <&secure_proxy_main 0>, - <&secure_proxy_main 1>, - <&secure_proxy_main 0>; - mbox-names = "rx", "tx", "notify"; - ti,host-id = <35>; - ti,secure-host; -}; - -&cbass_mcu { - mcu_esm: esm@4100000 { - compatible = "ti,j721e-esm"; - reg = <0x0 0x4100000 0x0 0x1000>; - ti,esm-pins = <0>, <1>, <2>, <85>; - bootph-pre-ram; - }; -}; - -&cbass_main { - sa3_secproxy: secproxy@44880000 { bootph-pre-ram; - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "rt", "scfg", "target_data"; - reg = <0x00 0x44880000 0x00 0x20000>, - <0x00 0x44860000 0x00 0x20000>, - <0x00 0x43600000 0x00 0x10000>; }; - - sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; - mbox-names = "tx", "rx", "boot_notify"; - bootph-pre-ram; - }; - - main_esm: esm@420000 { - compatible = "ti,j721e-esm"; - reg = <0x0 0x420000 0x0 0x1000>; - ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; - bootph-pre-ram; - }; -}; - -&mcu_pmx0 { - bootph-pre-ram; - wkup_uart0_pins_default: wkup-uart0-pins-default { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */ - AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ - AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */ - AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ - >; - bootph-pre-ram; - }; -}; - -&main_pmx0 { - bootph-pre-ram; - - main_uart1_pins_default: main-uart1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ - AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ - AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ - AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ - >; - bootph-pre-ram; - }; -}; - -/* WKUP UART0 is used for DM firmware logs */ -&wkup_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; - status = "okay"; - bootph-pre-ram; -}; - -/* Main UART1 is used for TIFS firmware logs */ -&main_uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; - status = "okay"; - bootph-pre-ram; -}; - -&ospi0 { - reg = <0x00 0x0fc40000 0x00 0x100>, - <0x00 0x60000000 0x00 0x08000000>; -}; - -&main_pktdma { - ti,sci = <&dm_tifs>; - bootph-pre-ram; }; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index eb1f7a929f..2523e08984 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -157,6 +157,62 @@ filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; + + fsstub-hs { + filename = "fsstub.bin_hs"; + ti-secure-rom { + content = <&fsstub_hs_cert>; + core = "secure"; + load = <0x60000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "custMpk.pem"; + countersign; + fsstub; + }; + fsstub_hs_cert: fsstub-hs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + fsstub_hs_enc: fsstub-hs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + + fsstub-fs { + filename = "fsstub.bin_fs"; + fsstub_fs_cert: fsstub-fs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + fsstub_fs_enc: fsstub-fs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + }; + + fsstub-gp { + filename = "fsstub.bin_gp"; + ti-secure-rom { + content = <&fsstub_gp>; + core = "secure"; + load = <0x60000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "ti-degenerate-key.pem"; + fsstub; + }; + fsstub_gp: fsstub-gp.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin"; + type = "blob-ext"; + optional; + }; + }; + ti-spl { filename = "tispl.bin"; pad-byte = <0xff>; @@ -199,6 +255,45 @@ }; }; + fsstub-hs { + description = "FSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "fsstub-hs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "fsstub.bin_hs"; + }; + }; + + fsstub-fs { + description = "FSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "fsstub-fs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "fsstub.bin_fs"; + }; + }; + + fsstub-gp { + description = "FSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "fsstub-gp"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "fsstub.bin_gp"; + }; + }; + dm { description = "DM binary"; type = "firmware"; @@ -256,7 +351,8 @@ conf-0 { description = "k3-am62a7-sk"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "fsstub-hs", "fsstub-fs", + "fsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; @@ -361,6 +457,45 @@ }; }; + fsstub-hs { + description = "FSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "fsstub-hs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "fsstub.bin_hs"; + }; + }; + + fsstub-fs { + description = "FSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "fsstub-fs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "fsstub.bin_fs"; + }; + }; + + fsstub-gp { + description = "FSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "fsstub-gp"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "fsstub.bin_gp"; + }; + }; + dm { description = "DM binary"; type = "firmware"; @@ -404,7 +539,8 @@ conf-0 { description = "k3-am62a7-sk"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "fsstub-hs", "fsstub-fs", + "fsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi new file mode 100644 index 0000000000..b5fdba46a0 --- /dev/null +++ b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi @@ -0,0 +1,2798 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.09.10 + * Wed Aug 23 2023 17:48:42 GMT-0500 (Central Daylight Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 1600MHz + * Density (per channel): 16Gb + * Number of Ranks: 2 + */ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_1 800000000 +#define DDRSS_PLL_FREQUENCY_2 800000000 + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x0004E200 +#define DDRSS_CTL_12_DATA 0x0030D400 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000C80 +#define DDRSS_CTL_15_DATA 0x0004E200 +#define DDRSS_CTL_16_DATA 0x0030D400 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000C80 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00004040 +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x00000000 +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000040C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x00001040 +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x00001040 +#define DDRSS_CTL_45_DATA 0x00000000 +#define DDRSS_CTL_46_DATA 0x05000804 +#define DDRSS_CTL_47_DATA 0x00000700 +#define DDRSS_CTL_48_DATA 0x09090004 +#define DDRSS_CTL_49_DATA 0x00000303 +#define DDRSS_CTL_50_DATA 0x00620011 +#define DDRSS_CTL_51_DATA 0x09110045 +#define DDRSS_CTL_52_DATA 0x0000421D +#define DDRSS_CTL_53_DATA 0x00620011 +#define DDRSS_CTL_54_DATA 0x09110045 +#define DDRSS_CTL_55_DATA 0x0900421D +#define DDRSS_CTL_56_DATA 0x000A0A09 +#define DDRSS_CTL_57_DATA 0x040006DB +#define DDRSS_CTL_58_DATA 0x090D2005 +#define DDRSS_CTL_59_DATA 0x00001710 +#define DDRSS_CTL_60_DATA 0x0C00DB60 +#define DDRSS_CTL_61_DATA 0x090D200D +#define DDRSS_CTL_62_DATA 0x00001710 +#define DDRSS_CTL_63_DATA 0x0C00DB60 +#define DDRSS_CTL_64_DATA 0x0304200D +#define DDRSS_CTL_65_DATA 0x04050002 +#define DDRSS_CTL_66_DATA 0x1F1E1F1E +#define DDRSS_CTL_67_DATA 0x01010008 +#define DDRSS_CTL_68_DATA 0x043C3C07 +#define DDRSS_CTL_69_DATA 0x03222203 +#define DDRSS_CTL_70_DATA 0x00002222 +#define DDRSS_CTL_71_DATA 0x00000101 +#define DDRSS_CTL_72_DATA 0x00000000 +#define DDRSS_CTL_73_DATA 0x01000000 +#define DDRSS_CTL_74_DATA 0x00130803 +#define DDRSS_CTL_75_DATA 0x000000BB +#define DDRSS_CTL_76_DATA 0x00000260 +#define DDRSS_CTL_77_DATA 0x00001858 +#define DDRSS_CTL_78_DATA 0x00000260 +#define DDRSS_CTL_79_DATA 0x00001858 +#define DDRSS_CTL_80_DATA 0x00000005 +#define DDRSS_CTL_81_DATA 0x0000000A +#define DDRSS_CTL_82_DATA 0x00000010 +#define DDRSS_CTL_83_DATA 0x00000130 +#define DDRSS_CTL_84_DATA 0x00000304 +#define DDRSS_CTL_85_DATA 0x00000130 +#define DDRSS_CTL_86_DATA 0x00000304 +#define DDRSS_CTL_87_DATA 0x03004000 +#define DDRSS_CTL_88_DATA 0x00001201 +#define DDRSS_CTL_89_DATA 0x000C0005 +#define DDRSS_CTL_90_DATA 0x2108000C +#define DDRSS_CTL_91_DATA 0x0A050521 +#define DDRSS_CTL_92_DATA 0x170C0803 +#define DDRSS_CTL_93_DATA 0x170C0803 +#define DDRSS_CTL_94_DATA 0x03010103 +#define DDRSS_CTL_95_DATA 0x00010301 +#define DDRSS_CTL_96_DATA 0x00140014 +#define DDRSS_CTL_97_DATA 0x026C026C +#define DDRSS_CTL_98_DATA 0x026C026C +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x03030000 +#define DDRSS_CTL_101_DATA 0x05050501 +#define DDRSS_CTL_102_DATA 0x03031804 +#define DDRSS_CTL_103_DATA 0x0C080C08 +#define DDRSS_CTL_104_DATA 0x08030318 +#define DDRSS_CTL_105_DATA 0x030C080C +#define DDRSS_CTL_106_DATA 0x00000303 +#define DDRSS_CTL_107_DATA 0x00000301 +#define DDRSS_CTL_108_DATA 0x00000001 +#define DDRSS_CTL_109_DATA 0x00000000 +#define DDRSS_CTL_110_DATA 0x40020100 +#define DDRSS_CTL_111_DATA 0x00038010 +#define DDRSS_CTL_112_DATA 0x00050004 +#define DDRSS_CTL_113_DATA 0x00000004 +#define DDRSS_CTL_114_DATA 0x00040003 +#define DDRSS_CTL_115_DATA 0x00040005 +#define DDRSS_CTL_116_DATA 0x00030000 +#define DDRSS_CTL_117_DATA 0x00050004 +#define DDRSS_CTL_118_DATA 0x00000004 +#define DDRSS_CTL_119_DATA 0x00002EC0 +#define DDRSS_CTL_120_DATA 0x00002EC0 +#define DDRSS_CTL_121_DATA 0x00002EC0 +#define DDRSS_CTL_122_DATA 0x00002EC0 +#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000051D +#define DDRSS_CTL_126_DATA 0x00061600 +#define DDRSS_CTL_127_DATA 0x00061600 +#define DDRSS_CTL_128_DATA 0x00061600 +#define DDRSS_CTL_129_DATA 0x00061600 +#define DDRSS_CTL_130_DATA 0x00061600 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000AA68 +#define DDRSS_CTL_133_DATA 0x00061600 +#define DDRSS_CTL_134_DATA 0x00061600 +#define DDRSS_CTL_135_DATA 0x00061600 +#define DDRSS_CTL_136_DATA 0x00061600 +#define DDRSS_CTL_137_DATA 0x00061600 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000AA68 +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000000 +#define DDRSS_CTL_157_DATA 0x00000000 +#define DDRSS_CTL_158_DATA 0x03050000 +#define DDRSS_CTL_159_DATA 0x03080308 +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x08010000 +#define DDRSS_CTL_162_DATA 0x000E0808 +#define DDRSS_CTL_163_DATA 0x01000000 +#define DDRSS_CTL_164_DATA 0x0E080808 +#define DDRSS_CTL_165_DATA 0x00000000 +#define DDRSS_CTL_166_DATA 0x08080801 +#define DDRSS_CTL_167_DATA 0x0000080E +#define DDRSS_CTL_168_DATA 0x00040003 +#define DDRSS_CTL_169_DATA 0x00000007 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x01000000 +#define DDRSS_CTL_177_DATA 0x00000000 +#define DDRSS_CTL_178_DATA 0x00001700 +#define DDRSS_CTL_179_DATA 0x0000100E +#define DDRSS_CTL_180_DATA 0x00000002 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00000001 +#define DDRSS_CTL_183_DATA 0x00000002 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00008000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00008000 +#define DDRSS_CTL_188_DATA 0x00000C00 +#define DDRSS_CTL_189_DATA 0x00008000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x0005000A +#define DDRSS_CTL_196_DATA 0x0404000D +#define DDRSS_CTL_197_DATA 0x0000000D +#define DDRSS_CTL_198_DATA 0x00A00140 +#define DDRSS_CTL_199_DATA 0x0C0C0190 +#define DDRSS_CTL_200_DATA 0x00000190 +#define DDRSS_CTL_201_DATA 0x00A00140 +#define DDRSS_CTL_202_DATA 0x0C0C0190 +#define DDRSS_CTL_203_DATA 0x00000190 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000004 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000064 +#define DDRSS_CTL_212_DATA 0x00000036 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000064 +#define DDRSS_CTL_215_DATA 0x00000036 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000004 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000064 +#define DDRSS_CTL_221_DATA 0x00000036 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000064 +#define DDRSS_CTL_224_DATA 0x00000036 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000029 +#define DDRSS_CTL_228_DATA 0x000000A9 +#define DDRSS_CTL_229_DATA 0x000000A9 +#define DDRSS_CTL_230_DATA 0x00000029 +#define DDRSS_CTL_231_DATA 0x000000A9 +#define DDRSS_CTL_232_DATA 0x000000A9 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x35003535 +#define DDRSS_CTL_258_DATA 0x00002735 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000027 +#define DDRSS_CTL_262_DATA 0x00000027 +#define DDRSS_CTL_263_DATA 0x00000027 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x0000002B +#define DDRSS_CTL_267_DATA 0x0000002B +#define DDRSS_CTL_268_DATA 0x0000002B +#define DDRSS_CTL_269_DATA 0x0000002B +#define DDRSS_CTL_270_DATA 0x0000002B +#define DDRSS_CTL_271_DATA 0x0000002B +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_274_DATA 0x00000015 +#define DDRSS_CTL_275_DATA 0x00000015 +#define DDRSS_CTL_276_DATA 0x00000000 +#define DDRSS_CTL_277_DATA 0x00000015 +#define DDRSS_CTL_278_DATA 0x00000015 +#define DDRSS_CTL_279_DATA 0x00000020 +#define DDRSS_CTL_280_DATA 0x00010000 +#define DDRSS_CTL_281_DATA 0x00000100 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000101 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x00000000 +#define DDRSS_CTL_291_DATA 0x00000000 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x0C181511 +#define DDRSS_CTL_297_DATA 0x00000304 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00020000 +#define DDRSS_CTL_312_DATA 0x00400100 +#define DDRSS_CTL_313_DATA 0x00080032 +#define DDRSS_CTL_314_DATA 0x01000200 +#define DDRSS_CTL_315_DATA 0x06400040 +#define DDRSS_CTL_316_DATA 0x00020030 +#define DDRSS_CTL_317_DATA 0x00400100 +#define DDRSS_CTL_318_DATA 0x00300640 +#define DDRSS_CTL_319_DATA 0x00030000 +#define DDRSS_CTL_320_DATA 0x00500050 +#define DDRSS_CTL_321_DATA 0x00000100 +#define DDRSS_CTL_322_DATA 0x01010000 +#define DDRSS_CTL_323_DATA 0x00000101 +#define DDRSS_CTL_324_DATA 0x1FFF0000 +#define DDRSS_CTL_325_DATA 0x000FFF00 +#define DDRSS_CTL_326_DATA 0x3FFF2000 +#define DDRSS_CTL_327_DATA 0x000FFF00 +#define DDRSS_CTL_328_DATA 0x0B000001 +#define DDRSS_CTL_329_DATA 0x0001FFFF +#define DDRSS_CTL_330_DATA 0x01010101 +#define DDRSS_CTL_331_DATA 0x01010101 +#define DDRSS_CTL_332_DATA 0x00000118 +#define DDRSS_CTL_333_DATA 0x00000C03 +#define DDRSS_CTL_334_DATA 0x00040100 +#define DDRSS_CTL_335_DATA 0x00040100 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x01030303 +#define DDRSS_CTL_339_DATA 0x00000001 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00000000 +#define DDRSS_CTL_378_DATA 0x00000000 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x01000101 +#define DDRSS_CTL_384_DATA 0x01010001 +#define DDRSS_CTL_385_DATA 0x00010101 +#define DDRSS_CTL_386_DATA 0x010A0A03 +#define DDRSS_CTL_387_DATA 0x05020201 +#define DDRSS_CTL_388_DATA 0x0C081C1C +#define DDRSS_CTL_389_DATA 0x0008030C +#define DDRSS_CTL_390_DATA 0x0B12030E +#define DDRSS_CTL_391_DATA 0x0B120315 +#define DDRSS_CTL_392_DATA 0x12120815 +#define DDRSS_CTL_393_DATA 0x01000000 +#define DDRSS_CTL_394_DATA 0x06030601 +#define DDRSS_CTL_395_DATA 0x04000103 +#define DDRSS_CTL_396_DATA 0x1B000004 +#define DDRSS_CTL_397_DATA 0x00000176 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x00000693 +#define DDRSS_CTL_403_DATA 0x00000E9C +#define DDRSS_CTL_404_DATA 0x03050202 +#define DDRSS_CTL_405_DATA 0x32200201 +#define DDRSS_CTL_406_DATA 0x000030B0 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x00000200 +#define DDRSS_CTL_411_DATA 0x0000DB18 +#define DDRSS_CTL_412_DATA 0x0001E6E0 +#define DDRSS_CTL_413_DATA 0x131F0402 +#define DDRSS_CTL_414_DATA 0x32200C0D +#define DDRSS_CTL_415_DATA 0x000030B0 +#define DDRSS_CTL_416_DATA 0x00000200 +#define DDRSS_CTL_417_DATA 0x00000200 +#define DDRSS_CTL_418_DATA 0x00000200 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x0000DB18 +#define DDRSS_CTL_421_DATA 0x0001E6E0 +#define DDRSS_CTL_422_DATA 0x131F0402 +#define DDRSS_CTL_423_DATA 0x00200C0D +#define DDRSS_CTL_424_DATA 0x00000000 +#define DDRSS_CTL_425_DATA 0x02000A00 +#define DDRSS_CTL_426_DATA 0x00050003 +#define DDRSS_CTL_427_DATA 0x00010101 +#define DDRSS_CTL_428_DATA 0x00010101 +#define DDRSS_CTL_429_DATA 0x00010001 +#define DDRSS_CTL_430_DATA 0x00000101 +#define DDRSS_CTL_431_DATA 0x02000201 +#define DDRSS_CTL_432_DATA 0x02010000 +#define DDRSS_CTL_433_DATA 0x06000200 +#define DDRSS_CTL_434_DATA 0x00002222 +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x000F0001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x01010000 +#define DDRSS_PI_27_DATA 0x0A000100 +#define DDRSS_PI_28_DATA 0x00000028 +#define DDRSS_PI_29_DATA 0x0F000000 +#define DDRSS_PI_30_DATA 0x00320000 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x00000000 +#define DDRSS_PI_36_DATA 0x00000000 +#define DDRSS_PI_37_DATA 0x00000001 +#define DDRSS_PI_38_DATA 0x000000AA +#define DDRSS_PI_39_DATA 0x00000055 +#define DDRSS_PI_40_DATA 0x000000B5 +#define DDRSS_PI_41_DATA 0x0000004A +#define DDRSS_PI_42_DATA 0x00000056 +#define DDRSS_PI_43_DATA 0x000000A9 +#define DDRSS_PI_44_DATA 0x000000A9 +#define DDRSS_PI_45_DATA 0x000000B5 +#define DDRSS_PI_46_DATA 0x00000000 +#define DDRSS_PI_47_DATA 0x00000000 +#define DDRSS_PI_48_DATA 0x000F0F00 +#define DDRSS_PI_49_DATA 0x00000019 +#define DDRSS_PI_50_DATA 0x000007D0 +#define DDRSS_PI_51_DATA 0x00000300 +#define DDRSS_PI_52_DATA 0x00000000 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x01000000 +#define DDRSS_PI_55_DATA 0x00010101 +#define DDRSS_PI_56_DATA 0x01000000 +#define DDRSS_PI_57_DATA 0x03000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x0000170F +#define DDRSS_PI_60_DATA 0x00000000 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x00000000 +#define DDRSS_PI_63_DATA 0x0A0A140A +#define DDRSS_PI_64_DATA 0x10020101 +#define DDRSS_PI_65_DATA 0x01000210 +#define DDRSS_PI_66_DATA 0x05000404 +#define DDRSS_PI_67_DATA 0x00010001 +#define DDRSS_PI_68_DATA 0x0001000E +#define DDRSS_PI_69_DATA 0x01010F00 +#define DDRSS_PI_70_DATA 0x00010000 +#define DDRSS_PI_71_DATA 0x00000034 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x0000FFFF +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x00000000 +#define DDRSS_PI_77_DATA 0x00000000 +#define DDRSS_PI_78_DATA 0x00000000 +#define DDRSS_PI_79_DATA 0x01000000 +#define DDRSS_PI_80_DATA 0x01010001 +#define DDRSS_PI_81_DATA 0x02000008 +#define DDRSS_PI_82_DATA 0x01000200 +#define DDRSS_PI_83_DATA 0x00000100 +#define DDRSS_PI_84_DATA 0x02000100 +#define DDRSS_PI_85_DATA 0x02000200 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000000 +#define DDRSS_PI_92_DATA 0x00000000 +#define DDRSS_PI_93_DATA 0x00000000 +#define DDRSS_PI_94_DATA 0x00000000 +#define DDRSS_PI_95_DATA 0x00000000 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00000000 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x01000400 +#define DDRSS_PI_100_DATA 0x0E0D0F10 +#define DDRSS_PI_101_DATA 0x080A1413 +#define DDRSS_PI_102_DATA 0x01000009 +#define DDRSS_PI_103_DATA 0x00000302 +#define DDRSS_PI_104_DATA 0x00000008 +#define DDRSS_PI_105_DATA 0x08000000 +#define DDRSS_PI_106_DATA 0x00000100 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x0000AA00 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00010000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000008 +#define DDRSS_PI_137_DATA 0x00000000 +#define DDRSS_PI_138_DATA 0x00000000 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x00000000 +#define DDRSS_PI_145_DATA 0x00010000 +#define DDRSS_PI_146_DATA 0x00000000 +#define DDRSS_PI_147_DATA 0x00000000 +#define DDRSS_PI_148_DATA 0x0000000A +#define DDRSS_PI_149_DATA 0x000186A0 +#define DDRSS_PI_150_DATA 0x00000100 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00000000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x01000000 +#define DDRSS_PI_157_DATA 0x00010003 +#define DDRSS_PI_158_DATA 0x02000101 +#define DDRSS_PI_159_DATA 0x01030001 +#define DDRSS_PI_160_DATA 0x00010400 +#define DDRSS_PI_161_DATA 0x06000105 +#define DDRSS_PI_162_DATA 0x01070001 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000000 +#define DDRSS_PI_165_DATA 0x00000000 +#define DDRSS_PI_166_DATA 0x00010001 +#define DDRSS_PI_167_DATA 0x00000000 +#define DDRSS_PI_168_DATA 0x00000000 +#define DDRSS_PI_169_DATA 0x00000000 +#define DDRSS_PI_170_DATA 0x00000000 +#define DDRSS_PI_171_DATA 0x00010000 +#define DDRSS_PI_172_DATA 0x00000004 +#define DDRSS_PI_173_DATA 0x00000000 +#define DDRSS_PI_174_DATA 0x00010000 +#define DDRSS_PI_175_DATA 0x00000000 +#define DDRSS_PI_176_DATA 0x00080000 +#define DDRSS_PI_177_DATA 0x00F000F0 +#define DDRSS_PI_178_DATA 0x00202001 +#define DDRSS_PI_179_DATA 0x00000034 +#define DDRSS_PI_180_DATA 0x0000005B +#define DDRSS_PI_181_DATA 0x0002005B +#define DDRSS_PI_182_DATA 0x02000200 +#define DDRSS_PI_183_DATA 0x00000004 +#define DDRSS_PI_184_DATA 0x0000100C +#define DDRSS_PI_185_DATA 0x00104000 +#define DDRSS_PI_186_DATA 0x00400000 +#define DDRSS_PI_187_DATA 0x00000013 +#define DDRSS_PI_188_DATA 0x000000BB +#define DDRSS_PI_189_DATA 0x00000260 +#define DDRSS_PI_190_DATA 0x00001858 +#define DDRSS_PI_191_DATA 0x00000260 +#define DDRSS_PI_192_DATA 0x04001858 +#define DDRSS_PI_193_DATA 0x01010404 +#define DDRSS_PI_194_DATA 0x00001501 +#define DDRSS_PI_195_DATA 0x00250025 +#define DDRSS_PI_196_DATA 0x01000100 +#define DDRSS_PI_197_DATA 0x00000100 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x050A0A03 +#define DDRSS_PI_200_DATA 0x01011C1C +#define DDRSS_PI_201_DATA 0x01010101 +#define DDRSS_PI_202_DATA 0x000C0C0A +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x04000000 +#define DDRSS_PI_206_DATA 0x0C021414 +#define DDRSS_PI_207_DATA 0x0404020C +#define DDRSS_PI_208_DATA 0x00090031 +#define DDRSS_PI_209_DATA 0x00190041 +#define DDRSS_PI_210_DATA 0x00190041 +#define DDRSS_PI_211_DATA 0x01010101 +#define DDRSS_PI_212_DATA 0x0003000D +#define DDRSS_PI_213_DATA 0x00030190 +#define DDRSS_PI_214_DATA 0x01000190 +#define DDRSS_PI_215_DATA 0x000E000E +#define DDRSS_PI_216_DATA 0x01910100 +#define DDRSS_PI_217_DATA 0x01000191 +#define DDRSS_PI_218_DATA 0x01910191 +#define DDRSS_PI_219_DATA 0x32103200 +#define DDRSS_PI_220_DATA 0x01013210 +#define DDRSS_PI_221_DATA 0x0A070601 +#define DDRSS_PI_222_DATA 0x180F090D +#define DDRSS_PI_223_DATA 0x180F0911 +#define DDRSS_PI_224_DATA 0x000C0011 +#define DDRSS_PI_225_DATA 0x00001000 +#define DDRSS_PI_226_DATA 0x00000C00 +#define DDRSS_PI_227_DATA 0x00001000 +#define DDRSS_PI_228_DATA 0x00000C00 +#define DDRSS_PI_229_DATA 0x02001000 +#define DDRSS_PI_230_DATA 0x001E000D +#define DDRSS_PI_231_DATA 0x001E0190 +#define DDRSS_PI_232_DATA 0x00000190 +#define DDRSS_PI_233_DATA 0x00001900 +#define DDRSS_PI_234_DATA 0x32000056 +#define DDRSS_PI_235_DATA 0x06000301 +#define DDRSS_PI_236_DATA 0x00250204 +#define DDRSS_PI_237_DATA 0x3212005C +#define DDRSS_PI_238_DATA 0x17000301 +#define DDRSS_PI_239_DATA 0x00250C14 +#define DDRSS_PI_240_DATA 0x3212005C +#define DDRSS_PI_241_DATA 0x17000301 +#define DDRSS_PI_242_DATA 0x00000C14 +#define DDRSS_PI_243_DATA 0x05030900 +#define DDRSS_PI_244_DATA 0x00040900 +#define DDRSS_PI_245_DATA 0x0000062B +#define DDRSS_PI_246_DATA 0x20010004 +#define DDRSS_PI_247_DATA 0x0A0A0A03 +#define DDRSS_PI_248_DATA 0x220D0000 +#define DDRSS_PI_249_DATA 0x1F09001E +#define DDRSS_PI_250_DATA 0x0000C570 +#define DDRSS_PI_251_DATA 0x20060045 +#define DDRSS_PI_252_DATA 0x17101718 +#define DDRSS_PI_253_DATA 0x220D0000 +#define DDRSS_PI_254_DATA 0x1F09001E +#define DDRSS_PI_255_DATA 0x0000C570 +#define DDRSS_PI_256_DATA 0x20060045 +#define DDRSS_PI_257_DATA 0x17101718 +#define DDRSS_PI_258_DATA 0x00000000 +#define DDRSS_PI_259_DATA 0x00000176 +#define DDRSS_PI_260_DATA 0x00000E9C +#define DDRSS_PI_261_DATA 0x000030B0 +#define DDRSS_PI_262_DATA 0x0001E6E0 +#define DDRSS_PI_263_DATA 0x000030B0 +#define DDRSS_PI_264_DATA 0x0001E6E0 +#define DDRSS_PI_265_DATA 0x026C0014 +#define DDRSS_PI_266_DATA 0x0303026C +#define DDRSS_PI_267_DATA 0x00000003 +#define DDRSS_PI_268_DATA 0x00000000 +#define DDRSS_PI_269_DATA 0x08030503 +#define DDRSS_PI_270_DATA 0x00000803 +#define DDRSS_PI_271_DATA 0x00002710 +#define DDRSS_PI_272_DATA 0x000186A0 +#define DDRSS_PI_273_DATA 0x00000005 +#define DDRSS_PI_274_DATA 0x00000064 +#define DDRSS_PI_275_DATA 0x00000014 +#define DDRSS_PI_276_DATA 0x0004E200 +#define DDRSS_PI_277_DATA 0x000186A0 +#define DDRSS_PI_278_DATA 0x00000005 +#define DDRSS_PI_279_DATA 0x00000C80 +#define DDRSS_PI_280_DATA 0x0000026C +#define DDRSS_PI_281_DATA 0x0004E200 +#define DDRSS_PI_282_DATA 0x000186A0 +#define DDRSS_PI_283_DATA 0x00000005 +#define DDRSS_PI_284_DATA 0x00000C80 +#define DDRSS_PI_285_DATA 0x0100026C +#define DDRSS_PI_286_DATA 0x00320040 +#define DDRSS_PI_287_DATA 0x00010008 +#define DDRSS_PI_288_DATA 0x06400040 +#define DDRSS_PI_289_DATA 0x00010030 +#define DDRSS_PI_290_DATA 0x06400040 +#define DDRSS_PI_291_DATA 0x00000330 +#define DDRSS_PI_292_DATA 0x00280050 +#define DDRSS_PI_293_DATA 0x03040404 +#define DDRSS_PI_294_DATA 0x00000303 +#define DDRSS_PI_295_DATA 0x01010000 +#define DDRSS_PI_296_DATA 0x04040202 +#define DDRSS_PI_297_DATA 0x67670808 +#define DDRSS_PI_298_DATA 0x67676767 +#define DDRSS_PI_299_DATA 0x67676767 +#define DDRSS_PI_300_DATA 0x67676767 +#define DDRSS_PI_301_DATA 0x00006767 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x55000000 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x3C00005A +#define DDRSS_PI_309_DATA 0x00005500 +#define DDRSS_PI_310_DATA 0x00005A00 +#define DDRSS_PI_311_DATA 0x0055003C +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x3C00005A +#define DDRSS_PI_314_DATA 0x00005500 +#define DDRSS_PI_315_DATA 0x00005A00 +#define DDRSS_PI_316_DATA 0x1716153C +#define DDRSS_PI_317_DATA 0x13121118 +#define DDRSS_PI_318_DATA 0x06050414 +#define DDRSS_PI_319_DATA 0x02010007 +#define DDRSS_PI_320_DATA 0x00000003 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000000 +#define DDRSS_PI_323_DATA 0x01000000 +#define DDRSS_PI_324_DATA 0x04020201 +#define DDRSS_PI_325_DATA 0x00080804 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000004 +#define DDRSS_PI_330_DATA 0x00000000 +#define DDRSS_PI_331_DATA 0x00000029 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00000000 +#define DDRSS_PI_335_DATA 0x20002B27 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x00000064 +#define DDRSS_PI_338_DATA 0x00000036 +#define DDRSS_PI_339_DATA 0x000000A9 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x35000000 +#define DDRSS_PI_343_DATA 0x20152B27 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PI_345_DATA 0x00000064 +#define DDRSS_PI_346_DATA 0x00000036 +#define DDRSS_PI_347_DATA 0x000000A9 +#define DDRSS_PI_348_DATA 0x00000000 +#define DDRSS_PI_349_DATA 0x00000000 +#define DDRSS_PI_350_DATA 0x35000000 +#define DDRSS_PI_351_DATA 0x20152B27 +#define DDRSS_PI_352_DATA 0x00000000 +#define DDRSS_PI_353_DATA 0x00000004 +#define DDRSS_PI_354_DATA 0x00000000 +#define DDRSS_PI_355_DATA 0x00000029 +#define DDRSS_PI_356_DATA 0x00000000 +#define DDRSS_PI_357_DATA 0x00000000 +#define DDRSS_PI_358_DATA 0x00000000 +#define DDRSS_PI_359_DATA 0x20002B27 +#define DDRSS_PI_360_DATA 0x00000000 +#define DDRSS_PI_361_DATA 0x00000064 +#define DDRSS_PI_362_DATA 0x00000036 +#define DDRSS_PI_363_DATA 0x000000A9 +#define DDRSS_PI_364_DATA 0x00000000 +#define DDRSS_PI_365_DATA 0x00000000 +#define DDRSS_PI_366_DATA 0x35000000 +#define DDRSS_PI_367_DATA 0x20152B27 +#define DDRSS_PI_368_DATA 0x00000000 +#define DDRSS_PI_369_DATA 0x00000064 +#define DDRSS_PI_370_DATA 0x00000036 +#define DDRSS_PI_371_DATA 0x000000A9 +#define DDRSS_PI_372_DATA 0x00000000 +#define DDRSS_PI_373_DATA 0x00000000 +#define DDRSS_PI_374_DATA 0x35000000 +#define DDRSS_PI_375_DATA 0x20152B27 +#define DDRSS_PI_376_DATA 0x00000000 +#define DDRSS_PI_377_DATA 0x00000004 +#define DDRSS_PI_378_DATA 0x00000000 +#define DDRSS_PI_379_DATA 0x00000029 +#define DDRSS_PI_380_DATA 0x00000000 +#define DDRSS_PI_381_DATA 0x00000000 +#define DDRSS_PI_382_DATA 0x00000000 +#define DDRSS_PI_383_DATA 0x20002B27 +#define DDRSS_PI_384_DATA 0x00000000 +#define DDRSS_PI_385_DATA 0x00000064 +#define DDRSS_PI_386_DATA 0x00000036 +#define DDRSS_PI_387_DATA 0x000000A9 +#define DDRSS_PI_388_DATA 0x00000000 +#define DDRSS_PI_389_DATA 0x00000000 +#define DDRSS_PI_390_DATA 0x35000000 +#define DDRSS_PI_391_DATA 0x20152B27 +#define DDRSS_PI_392_DATA 0x00000000 +#define DDRSS_PI_393_DATA 0x00000064 +#define DDRSS_PI_394_DATA 0x00000036 +#define DDRSS_PI_395_DATA 0x000000A9 +#define DDRSS_PI_396_DATA 0x00000000 +#define DDRSS_PI_397_DATA 0x00000000 +#define DDRSS_PI_398_DATA 0x35000000 +#define DDRSS_PI_399_DATA 0x20152B27 +#define DDRSS_PI_400_DATA 0x00000000 +#define DDRSS_PI_401_DATA 0x00000004 +#define DDRSS_PI_402_DATA 0x00000000 +#define DDRSS_PI_403_DATA 0x00000029 +#define DDRSS_PI_404_DATA 0x00000000 +#define DDRSS_PI_405_DATA 0x00000000 +#define DDRSS_PI_406_DATA 0x00000000 +#define DDRSS_PI_407_DATA 0x20002B27 +#define DDRSS_PI_408_DATA 0x00000000 +#define DDRSS_PI_409_DATA 0x00000064 +#define DDRSS_PI_410_DATA 0x00000036 +#define DDRSS_PI_411_DATA 0x000000A9 +#define DDRSS_PI_412_DATA 0x00000000 +#define DDRSS_PI_413_DATA 0x00000000 +#define DDRSS_PI_414_DATA 0x35000000 +#define DDRSS_PI_415_DATA 0x20152B27 +#define DDRSS_PI_416_DATA 0x00000000 +#define DDRSS_PI_417_DATA 0x00000064 +#define DDRSS_PI_418_DATA 0x00000036 +#define DDRSS_PI_419_DATA 0x000000A9 +#define DDRSS_PI_420_DATA 0x00000000 +#define DDRSS_PI_421_DATA 0x00000000 +#define DDRSS_PI_422_DATA 0x35000000 +#define DDRSS_PI_423_DATA 0x20152B27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01030000 +#define DDRSS_PHY_6_DATA 0x00010000 +#define DDRSS_PHY_7_DATA 0x01030004 +#define DDRSS_PHY_8_DATA 0x01000000 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x00000000 +#define DDRSS_PHY_12_DATA 0x01010000 +#define DDRSS_PHY_13_DATA 0x00010000 +#define DDRSS_PHY_14_DATA 0x00C00001 +#define DDRSS_PHY_15_DATA 0x00CC0008 +#define DDRSS_PHY_16_DATA 0x00660601 +#define DDRSS_PHY_17_DATA 0x00000003 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x00000001 +#define DDRSS_PHY_20_DATA 0x0000AAAA +#define DDRSS_PHY_21_DATA 0x00005555 +#define DDRSS_PHY_22_DATA 0x0000B5B5 +#define DDRSS_PHY_23_DATA 0x00004A4A +#define DDRSS_PHY_24_DATA 0x00005656 +#define DDRSS_PHY_25_DATA 0x0000A9A9 +#define DDRSS_PHY_26_DATA 0x0000B7B7 +#define DDRSS_PHY_27_DATA 0x00004848 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x00000000 +#define DDRSS_PHY_30_DATA 0x08000000 +#define DDRSS_PHY_31_DATA 0x0F000008 +#define DDRSS_PHY_32_DATA 0x00000F0F +#define DDRSS_PHY_33_DATA 0x00E4E400 +#define DDRSS_PHY_34_DATA 0x00071020 +#define DDRSS_PHY_35_DATA 0x000C0020 +#define DDRSS_PHY_36_DATA 0x00062000 +#define DDRSS_PHY_37_DATA 0x00000000 +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x55555555 +#define DDRSS_PHY_41_DATA 0xAAAAAAAA +#define DDRSS_PHY_42_DATA 0x00005555 +#define DDRSS_PHY_43_DATA 0x01000100 +#define DDRSS_PHY_44_DATA 0x00800180 +#define DDRSS_PHY_45_DATA 0x00000001 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000004 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x081F07FF +#define DDRSS_PHY_75_DATA 0x10200080 +#define DDRSS_PHY_76_DATA 0x00000008 +#define DDRSS_PHY_77_DATA 0x00000401 +#define DDRSS_PHY_78_DATA 0x00000000 +#define DDRSS_PHY_79_DATA 0x01CC0B01 +#define DDRSS_PHY_80_DATA 0x1003CC0C +#define DDRSS_PHY_81_DATA 0x20000140 +#define DDRSS_PHY_82_DATA 0x07FF0200 +#define DDRSS_PHY_83_DATA 0x0000DD01 +#define DDRSS_PHY_84_DATA 0x00100303 +#define DDRSS_PHY_85_DATA 0x00000000 +#define DDRSS_PHY_86_DATA 0x00000000 +#define DDRSS_PHY_87_DATA 0x00031000 +#define DDRSS_PHY_88_DATA 0x00100010 +#define DDRSS_PHY_89_DATA 0x00100010 +#define DDRSS_PHY_90_DATA 0x00100010 +#define DDRSS_PHY_91_DATA 0x00100010 +#define DDRSS_PHY_92_DATA 0x02000010 +#define DDRSS_PHY_93_DATA 0x00000004 +#define DDRSS_PHY_94_DATA 0x51516042 +#define DDRSS_PHY_95_DATA 0x31C06000 +#define DDRSS_PHY_96_DATA 0x07AB0340 +#define DDRSS_PHY_97_DATA 0x00C0C001 +#define DDRSS_PHY_98_DATA 0x0B000000 +#define DDRSS_PHY_99_DATA 0x000B0A0A +#define DDRSS_PHY_100_DATA 0x42100010 +#define DDRSS_PHY_101_DATA 0x010C073E +#define DDRSS_PHY_102_DATA 0x000F0C2D +#define DDRSS_PHY_103_DATA 0x01000140 +#define DDRSS_PHY_104_DATA 0x00F50120 +#define DDRSS_PHY_105_DATA 0x00000C00 +#define DDRSS_PHY_106_DATA 0x00000299 +#define DDRSS_PHY_107_DATA 0x00030200 +#define DDRSS_PHY_108_DATA 0x02800000 +#define DDRSS_PHY_109_DATA 0x80800000 +#define DDRSS_PHY_110_DATA 0x000B2010 +#define DDRSS_PHY_111_DATA 0x32570186 +#define DDRSS_PHY_112_DATA 0x00000004 +#define DDRSS_PHY_113_DATA 0x04190419 +#define DDRSS_PHY_114_DATA 0x04190419 +#define DDRSS_PHY_115_DATA 0x04190419 +#define DDRSS_PHY_116_DATA 0x04190419 +#define DDRSS_PHY_117_DATA 0x00000419 +#define DDRSS_PHY_118_DATA 0x0000A000 +#define DDRSS_PHY_119_DATA 0x00A000A0 +#define DDRSS_PHY_120_DATA 0x00A000A0 +#define DDRSS_PHY_121_DATA 0x00A000A0 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x01E600A0 +#define DDRSS_PHY_128_DATA 0x01000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00080200 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x20202020 +#define DDRSS_PHY_134_DATA 0x20202020 +#define DDRSS_PHY_135_DATA 0xF0F02020 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x00000000 +#define DDRSS_PHY_268_DATA 0x01010000 +#define DDRSS_PHY_269_DATA 0x00010000 +#define DDRSS_PHY_270_DATA 0x00C00001 +#define DDRSS_PHY_271_DATA 0x00CC0008 +#define DDRSS_PHY_272_DATA 0x00660601 +#define DDRSS_PHY_273_DATA 0x00000003 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x00000001 +#define DDRSS_PHY_276_DATA 0x0000AAAA +#define DDRSS_PHY_277_DATA 0x00005555 +#define DDRSS_PHY_278_DATA 0x0000B5B5 +#define DDRSS_PHY_279_DATA 0x00004A4A +#define DDRSS_PHY_280_DATA 0x00005656 +#define DDRSS_PHY_281_DATA 0x0000A9A9 +#define DDRSS_PHY_282_DATA 0x0000B7B7 +#define DDRSS_PHY_283_DATA 0x00004848 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x00000000 +#define DDRSS_PHY_286_DATA 0x08000000 +#define DDRSS_PHY_287_DATA 0x0F000008 +#define DDRSS_PHY_288_DATA 0x00000F0F +#define DDRSS_PHY_289_DATA 0x00E4E400 +#define DDRSS_PHY_290_DATA 0x00071020 +#define DDRSS_PHY_291_DATA 0x000C0020 +#define DDRSS_PHY_292_DATA 0x00062000 +#define DDRSS_PHY_293_DATA 0x00000000 +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x55555555 +#define DDRSS_PHY_297_DATA 0xAAAAAAAA +#define DDRSS_PHY_298_DATA 0x00005555 +#define DDRSS_PHY_299_DATA 0x01000100 +#define DDRSS_PHY_300_DATA 0x00800180 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000004 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x081F07FF +#define DDRSS_PHY_331_DATA 0x10200080 +#define DDRSS_PHY_332_DATA 0x00000008 +#define DDRSS_PHY_333_DATA 0x00000401 +#define DDRSS_PHY_334_DATA 0x00000000 +#define DDRSS_PHY_335_DATA 0x01CC0B01 +#define DDRSS_PHY_336_DATA 0x1003CC0C +#define DDRSS_PHY_337_DATA 0x20000140 +#define DDRSS_PHY_338_DATA 0x07FF0200 +#define DDRSS_PHY_339_DATA 0x0000DD01 +#define DDRSS_PHY_340_DATA 0x00100303 +#define DDRSS_PHY_341_DATA 0x00000000 +#define DDRSS_PHY_342_DATA 0x00000000 +#define DDRSS_PHY_343_DATA 0x00031000 +#define DDRSS_PHY_344_DATA 0x00100010 +#define DDRSS_PHY_345_DATA 0x00100010 +#define DDRSS_PHY_346_DATA 0x00100010 +#define DDRSS_PHY_347_DATA 0x00100010 +#define DDRSS_PHY_348_DATA 0x02000010 +#define DDRSS_PHY_349_DATA 0x00000004 +#define DDRSS_PHY_350_DATA 0x51516042 +#define DDRSS_PHY_351_DATA 0x31C06000 +#define DDRSS_PHY_352_DATA 0x07AB0340 +#define DDRSS_PHY_353_DATA 0x00C0C001 +#define DDRSS_PHY_354_DATA 0x0B000000 +#define DDRSS_PHY_355_DATA 0x000B0A0A +#define DDRSS_PHY_356_DATA 0x42100010 +#define DDRSS_PHY_357_DATA 0x010C073E +#define DDRSS_PHY_358_DATA 0x000F0C2D +#define DDRSS_PHY_359_DATA 0x01000140 +#define DDRSS_PHY_360_DATA 0x00F50120 +#define DDRSS_PHY_361_DATA 0x00000C00 +#define DDRSS_PHY_362_DATA 0x00000299 +#define DDRSS_PHY_363_DATA 0x00030200 +#define DDRSS_PHY_364_DATA 0x02800000 +#define DDRSS_PHY_365_DATA 0x80800000 +#define DDRSS_PHY_366_DATA 0x000B2010 +#define DDRSS_PHY_367_DATA 0x17520684 +#define DDRSS_PHY_368_DATA 0x00000003 +#define DDRSS_PHY_369_DATA 0x04190419 +#define DDRSS_PHY_370_DATA 0x04190419 +#define DDRSS_PHY_371_DATA 0x04190419 +#define DDRSS_PHY_372_DATA 0x04190419 +#define DDRSS_PHY_373_DATA 0x00000419 +#define DDRSS_PHY_374_DATA 0x0000A000 +#define DDRSS_PHY_375_DATA 0x00A000A0 +#define DDRSS_PHY_376_DATA 0x00A000A0 +#define DDRSS_PHY_377_DATA 0x00A000A0 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x01E600A0 +#define DDRSS_PHY_384_DATA 0x01000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00080200 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x20202020 +#define DDRSS_PHY_390_DATA 0x20202020 +#define DDRSS_PHY_391_DATA 0xF0F02020 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x04F00000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x01010000 +#define DDRSS_PHY_525_DATA 0x00010000 +#define DDRSS_PHY_526_DATA 0x00C00001 +#define DDRSS_PHY_527_DATA 0x00CC0008 +#define DDRSS_PHY_528_DATA 0x00660601 +#define DDRSS_PHY_529_DATA 0x00000003 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000001 +#define DDRSS_PHY_532_DATA 0x0000AAAA +#define DDRSS_PHY_533_DATA 0x00005555 +#define DDRSS_PHY_534_DATA 0x0000B5B5 +#define DDRSS_PHY_535_DATA 0x00004A4A +#define DDRSS_PHY_536_DATA 0x00005656 +#define DDRSS_PHY_537_DATA 0x0000A9A9 +#define DDRSS_PHY_538_DATA 0x0000B7B7 +#define DDRSS_PHY_539_DATA 0x00004848 +#define DDRSS_PHY_540_DATA 0x00000000 +#define DDRSS_PHY_541_DATA 0x00000000 +#define DDRSS_PHY_542_DATA 0x08000000 +#define DDRSS_PHY_543_DATA 0x0F000008 +#define DDRSS_PHY_544_DATA 0x00000F0F +#define DDRSS_PHY_545_DATA 0x00E4E400 +#define DDRSS_PHY_546_DATA 0x00071020 +#define DDRSS_PHY_547_DATA 0x000C0020 +#define DDRSS_PHY_548_DATA 0x00062000 +#define DDRSS_PHY_549_DATA 0x00000000 +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x55555555 +#define DDRSS_PHY_553_DATA 0xAAAAAAAA +#define DDRSS_PHY_554_DATA 0x00005555 +#define DDRSS_PHY_555_DATA 0x01000100 +#define DDRSS_PHY_556_DATA 0x00800180 +#define DDRSS_PHY_557_DATA 0x00000001 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000004 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x081F07FF +#define DDRSS_PHY_587_DATA 0x10200080 +#define DDRSS_PHY_588_DATA 0x00000008 +#define DDRSS_PHY_589_DATA 0x00000401 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x01CC0B01 +#define DDRSS_PHY_592_DATA 0x1003CC0C +#define DDRSS_PHY_593_DATA 0x20000140 +#define DDRSS_PHY_594_DATA 0x07FF0200 +#define DDRSS_PHY_595_DATA 0x0000DD01 +#define DDRSS_PHY_596_DATA 0x00100303 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00031000 +#define DDRSS_PHY_600_DATA 0x00100010 +#define DDRSS_PHY_601_DATA 0x00100010 +#define DDRSS_PHY_602_DATA 0x00100010 +#define DDRSS_PHY_603_DATA 0x00100010 +#define DDRSS_PHY_604_DATA 0x02000010 +#define DDRSS_PHY_605_DATA 0x00000004 +#define DDRSS_PHY_606_DATA 0x51516042 +#define DDRSS_PHY_607_DATA 0x31C06000 +#define DDRSS_PHY_608_DATA 0x07AB0340 +#define DDRSS_PHY_609_DATA 0x00C0C001 +#define DDRSS_PHY_610_DATA 0x0B000000 +#define DDRSS_PHY_611_DATA 0x000B0A0A +#define DDRSS_PHY_612_DATA 0x42100010 +#define DDRSS_PHY_613_DATA 0x010C073E +#define DDRSS_PHY_614_DATA 0x000F0C2D +#define DDRSS_PHY_615_DATA 0x01000140 +#define DDRSS_PHY_616_DATA 0x00F50120 +#define DDRSS_PHY_617_DATA 0x00000C00 +#define DDRSS_PHY_618_DATA 0x00000299 +#define DDRSS_PHY_619_DATA 0x00030200 +#define DDRSS_PHY_620_DATA 0x02800000 +#define DDRSS_PHY_621_DATA 0x80800000 +#define DDRSS_PHY_622_DATA 0x000B2010 +#define DDRSS_PHY_623_DATA 0x07684523 +#define DDRSS_PHY_624_DATA 0x00000001 +#define DDRSS_PHY_625_DATA 0x04190419 +#define DDRSS_PHY_626_DATA 0x04190419 +#define DDRSS_PHY_627_DATA 0x04190419 +#define DDRSS_PHY_628_DATA 0x04190419 +#define DDRSS_PHY_629_DATA 0x00000419 +#define DDRSS_PHY_630_DATA 0x0000A000 +#define DDRSS_PHY_631_DATA 0x00A000A0 +#define DDRSS_PHY_632_DATA 0x00A000A0 +#define DDRSS_PHY_633_DATA 0x00A000A0 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x01E600A0 +#define DDRSS_PHY_640_DATA 0x01000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00080200 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x20202020 +#define DDRSS_PHY_646_DATA 0x20202020 +#define DDRSS_PHY_647_DATA 0xF0F02020 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x04F00000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x01010000 +#define DDRSS_PHY_781_DATA 0x00010000 +#define DDRSS_PHY_782_DATA 0x00C00001 +#define DDRSS_PHY_783_DATA 0x00CC0008 +#define DDRSS_PHY_784_DATA 0x00660601 +#define DDRSS_PHY_785_DATA 0x00000003 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000001 +#define DDRSS_PHY_788_DATA 0x0000AAAA +#define DDRSS_PHY_789_DATA 0x00005555 +#define DDRSS_PHY_790_DATA 0x0000B5B5 +#define DDRSS_PHY_791_DATA 0x00004A4A +#define DDRSS_PHY_792_DATA 0x00005656 +#define DDRSS_PHY_793_DATA 0x0000A9A9 +#define DDRSS_PHY_794_DATA 0x0000B7B7 +#define DDRSS_PHY_795_DATA 0x00004848 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x08000000 +#define DDRSS_PHY_799_DATA 0x0F000008 +#define DDRSS_PHY_800_DATA 0x00000F0F +#define DDRSS_PHY_801_DATA 0x00E4E400 +#define DDRSS_PHY_802_DATA 0x00071020 +#define DDRSS_PHY_803_DATA 0x000C0020 +#define DDRSS_PHY_804_DATA 0x00062000 +#define DDRSS_PHY_805_DATA 0x00000000 +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x55555555 +#define DDRSS_PHY_809_DATA 0xAAAAAAAA +#define DDRSS_PHY_810_DATA 0x00005555 +#define DDRSS_PHY_811_DATA 0x01000100 +#define DDRSS_PHY_812_DATA 0x00800180 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000004 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x081F07FF +#define DDRSS_PHY_843_DATA 0x10200080 +#define DDRSS_PHY_844_DATA 0x00000008 +#define DDRSS_PHY_845_DATA 0x00000401 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x01CC0B01 +#define DDRSS_PHY_848_DATA 0x1003CC0C +#define DDRSS_PHY_849_DATA 0x20000140 +#define DDRSS_PHY_850_DATA 0x07FF0200 +#define DDRSS_PHY_851_DATA 0x0000DD01 +#define DDRSS_PHY_852_DATA 0x00100303 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00031000 +#define DDRSS_PHY_856_DATA 0x00100010 +#define DDRSS_PHY_857_DATA 0x00100010 +#define DDRSS_PHY_858_DATA 0x00100010 +#define DDRSS_PHY_859_DATA 0x00100010 +#define DDRSS_PHY_860_DATA 0x02000010 +#define DDRSS_PHY_861_DATA 0x00000004 +#define DDRSS_PHY_862_DATA 0x51516042 +#define DDRSS_PHY_863_DATA 0x31C06000 +#define DDRSS_PHY_864_DATA 0x07AB0340 +#define DDRSS_PHY_865_DATA 0x00C0C001 +#define DDRSS_PHY_866_DATA 0x0B000000 +#define DDRSS_PHY_867_DATA 0x000B0A0A +#define DDRSS_PHY_868_DATA 0x42100010 +#define DDRSS_PHY_869_DATA 0x010C073E +#define DDRSS_PHY_870_DATA 0x000F0C2D +#define DDRSS_PHY_871_DATA 0x01000140 +#define DDRSS_PHY_872_DATA 0x00F50120 +#define DDRSS_PHY_873_DATA 0x00000C00 +#define DDRSS_PHY_874_DATA 0x00000299 +#define DDRSS_PHY_875_DATA 0x00030200 +#define DDRSS_PHY_876_DATA 0x02800000 +#define DDRSS_PHY_877_DATA 0x80800000 +#define DDRSS_PHY_878_DATA 0x000B2010 +#define DDRSS_PHY_879_DATA 0x76158234 +#define DDRSS_PHY_880_DATA 0x00000000 +#define DDRSS_PHY_881_DATA 0x04190419 +#define DDRSS_PHY_882_DATA 0x04190419 +#define DDRSS_PHY_883_DATA 0x04190419 +#define DDRSS_PHY_884_DATA 0x04190419 +#define DDRSS_PHY_885_DATA 0x00000419 +#define DDRSS_PHY_886_DATA 0x0000A000 +#define DDRSS_PHY_887_DATA 0x00A000A0 +#define DDRSS_PHY_888_DATA 0x00A000A0 +#define DDRSS_PHY_889_DATA 0x00A000A0 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x01E600A0 +#define DDRSS_PHY_896_DATA 0x01000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00080200 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x20202020 +#define DDRSS_PHY_902_DATA 0x20202020 +#define DDRSS_PHY_903_DATA 0xF0F02020 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x0A418820 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x000304CC +#define DDRSS_PHY_1062_DATA 0x03000003 +#define DDRSS_PHY_1063_DATA 0x00030000 +#define DDRSS_PHY_1064_DATA 0x00000300 +#define DDRSS_PHY_1065_DATA 0x00000300 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x42080010 +#define DDRSS_PHY_1069_DATA 0x0000803E +#define DDRSS_PHY_1070_DATA 0x00000001 +#define DDRSS_PHY_1071_DATA 0x01000002 +#define DDRSS_PHY_1072_DATA 0x00008000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000000 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000100 +#define DDRSS_PHY_1286_DATA 0x00000200 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00400000 +#define DDRSS_PHY_1292_DATA 0x00000080 +#define DDRSS_PHY_1293_DATA 0x00DCBA98 +#define DDRSS_PHY_1294_DATA 0x03000000 +#define DDRSS_PHY_1295_DATA 0x00200000 +#define DDRSS_PHY_1296_DATA 0x00000000 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x00000000 +#define DDRSS_PHY_1300_DATA 0x00000000 +#define DDRSS_PHY_1301_DATA 0x0000002A +#define DDRSS_PHY_1302_DATA 0x00000015 +#define DDRSS_PHY_1303_DATA 0x00000015 +#define DDRSS_PHY_1304_DATA 0x0000002A +#define DDRSS_PHY_1305_DATA 0x00000033 +#define DDRSS_PHY_1306_DATA 0x0000000C +#define DDRSS_PHY_1307_DATA 0x0000000C +#define DDRSS_PHY_1308_DATA 0x00000033 +#define DDRSS_PHY_1309_DATA 0x0A418820 +#define DDRSS_PHY_1310_DATA 0x00000000 +#define DDRSS_PHY_1311_DATA 0x000F0000 +#define DDRSS_PHY_1312_DATA 0x20202003 +#define DDRSS_PHY_1313_DATA 0x00202020 +#define DDRSS_PHY_1314_DATA 0x20008008 +#define DDRSS_PHY_1315_DATA 0x00000810 +#define DDRSS_PHY_1316_DATA 0x00000F00 +#define DDRSS_PHY_1317_DATA 0x000304CC +#define DDRSS_PHY_1318_DATA 0x03000003 +#define DDRSS_PHY_1319_DATA 0x00030000 +#define DDRSS_PHY_1320_DATA 0x00000300 +#define DDRSS_PHY_1321_DATA 0x00000300 +#define DDRSS_PHY_1322_DATA 0x00000300 +#define DDRSS_PHY_1323_DATA 0x00000300 +#define DDRSS_PHY_1324_DATA 0x42080010 +#define DDRSS_PHY_1325_DATA 0x0000803E +#define DDRSS_PHY_1326_DATA 0x00000001 +#define DDRSS_PHY_1327_DATA 0x01000002 +#define DDRSS_PHY_1328_DATA 0x00008000 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000000 +#define DDRSS_PHY_1331_DATA 0x00000000 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x00000000 +#define DDRSS_PHY_1346_DATA 0x00000000 +#define DDRSS_PHY_1347_DATA 0x00000000 +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00000000 +#define DDRSS_PHY_1375_DATA 0x00000000 +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x00000000 +#define DDRSS_PHY_1383_DATA 0x00000000 +#define DDRSS_PHY_1384_DATA 0x00000000 +#define DDRSS_PHY_1385_DATA 0x00000000 +#define DDRSS_PHY_1386_DATA 0x00000000 +#define DDRSS_PHY_1387_DATA 0x00000000 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x00000000 +#define DDRSS_PHY_1394_DATA 0x00000000 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00000000 +#define DDRSS_PHY_1397_DATA 0x00000000 +#define DDRSS_PHY_1398_DATA 0x00000000 +#define DDRSS_PHY_1399_DATA 0x00000000 +#define DDRSS_PHY_1400_DATA 0x00000000 +#define DDRSS_PHY_1401_DATA 0x00000000 +#define DDRSS_PHY_1402_DATA 0x00000000 +#define DDRSS_PHY_1403_DATA 0x00000000 +#define DDRSS_PHY_1404_DATA 0x00000000 +#define DDRSS_PHY_1405_DATA 0x00000000 +#define DDRSS_PHY_1406_DATA 0x00000000 +#define DDRSS_PHY_1407_DATA 0x00000000 +#define DDRSS_PHY_1408_DATA 0x00000000 +#define DDRSS_PHY_1409_DATA 0x00000000 +#define DDRSS_PHY_1410_DATA 0x00000000 +#define DDRSS_PHY_1411_DATA 0x00000000 +#define DDRSS_PHY_1412_DATA 0x00000000 +#define DDRSS_PHY_1413_DATA 0x00000000 +#define DDRSS_PHY_1414_DATA 0x00000000 +#define DDRSS_PHY_1415_DATA 0x00000000 +#define DDRSS_PHY_1416_DATA 0x00000000 +#define DDRSS_PHY_1417_DATA 0x00000000 +#define DDRSS_PHY_1418_DATA 0x00000000 +#define DDRSS_PHY_1419_DATA 0x00000000 +#define DDRSS_PHY_1420_DATA 0x00000000 +#define DDRSS_PHY_1421_DATA 0x00000000 +#define DDRSS_PHY_1422_DATA 0x00000000 +#define DDRSS_PHY_1423_DATA 0x00000000 +#define DDRSS_PHY_1424_DATA 0x00000000 +#define DDRSS_PHY_1425_DATA 0x00000000 +#define DDRSS_PHY_1426_DATA 0x00000000 +#define DDRSS_PHY_1427_DATA 0x00000000 +#define DDRSS_PHY_1428_DATA 0x00000000 +#define DDRSS_PHY_1429_DATA 0x00000000 +#define DDRSS_PHY_1430_DATA 0x00000000 +#define DDRSS_PHY_1431_DATA 0x00000000 +#define DDRSS_PHY_1432_DATA 0x00000000 +#define DDRSS_PHY_1433_DATA 0x00000000 +#define DDRSS_PHY_1434_DATA 0x00000000 +#define DDRSS_PHY_1435_DATA 0x00000000 +#define DDRSS_PHY_1436_DATA 0x00000000 +#define DDRSS_PHY_1437_DATA 0x00000000 +#define DDRSS_PHY_1438_DATA 0x00000000 +#define DDRSS_PHY_1439_DATA 0x00000000 +#define DDRSS_PHY_1440_DATA 0x00000000 +#define DDRSS_PHY_1441_DATA 0x00000000 +#define DDRSS_PHY_1442_DATA 0x00000000 +#define DDRSS_PHY_1443_DATA 0x00000000 +#define DDRSS_PHY_1444_DATA 0x00000000 +#define DDRSS_PHY_1445_DATA 0x00000000 +#define DDRSS_PHY_1446_DATA 0x00000000 +#define DDRSS_PHY_1447_DATA 0x00000000 +#define DDRSS_PHY_1448_DATA 0x00000000 +#define DDRSS_PHY_1449_DATA 0x00000000 +#define DDRSS_PHY_1450_DATA 0x00000000 +#define DDRSS_PHY_1451_DATA 0x00000000 +#define DDRSS_PHY_1452_DATA 0x00000000 +#define DDRSS_PHY_1453_DATA 0x00000000 +#define DDRSS_PHY_1454_DATA 0x00000000 +#define DDRSS_PHY_1455_DATA 0x00000000 +#define DDRSS_PHY_1456_DATA 0x00000000 +#define DDRSS_PHY_1457_DATA 0x00000000 +#define DDRSS_PHY_1458_DATA 0x00000000 +#define DDRSS_PHY_1459_DATA 0x00000000 +#define DDRSS_PHY_1460_DATA 0x00000000 +#define DDRSS_PHY_1461_DATA 0x00000000 +#define DDRSS_PHY_1462_DATA 0x00000000 +#define DDRSS_PHY_1463_DATA 0x00000000 +#define DDRSS_PHY_1464_DATA 0x00000000 +#define DDRSS_PHY_1465_DATA 0x00000000 +#define DDRSS_PHY_1466_DATA 0x00000000 +#define DDRSS_PHY_1467_DATA 0x00000000 +#define DDRSS_PHY_1468_DATA 0x00000000 +#define DDRSS_PHY_1469_DATA 0x00000000 +#define DDRSS_PHY_1470_DATA 0x00000000 +#define DDRSS_PHY_1471_DATA 0x00000000 +#define DDRSS_PHY_1472_DATA 0x00000000 +#define DDRSS_PHY_1473_DATA 0x00000000 +#define DDRSS_PHY_1474_DATA 0x00000000 +#define DDRSS_PHY_1475_DATA 0x00000000 +#define DDRSS_PHY_1476_DATA 0x00000000 +#define DDRSS_PHY_1477_DATA 0x00000000 +#define DDRSS_PHY_1478_DATA 0x00000000 +#define DDRSS_PHY_1479_DATA 0x00000000 +#define DDRSS_PHY_1480_DATA 0x00000000 +#define DDRSS_PHY_1481_DATA 0x00000000 +#define DDRSS_PHY_1482_DATA 0x00000000 +#define DDRSS_PHY_1483_DATA 0x00000000 +#define DDRSS_PHY_1484_DATA 0x00000000 +#define DDRSS_PHY_1485_DATA 0x00000000 +#define DDRSS_PHY_1486_DATA 0x00000000 +#define DDRSS_PHY_1487_DATA 0x00000000 +#define DDRSS_PHY_1488_DATA 0x00000000 +#define DDRSS_PHY_1489_DATA 0x00000000 +#define DDRSS_PHY_1490_DATA 0x00000000 +#define DDRSS_PHY_1491_DATA 0x00000000 +#define DDRSS_PHY_1492_DATA 0x00000000 +#define DDRSS_PHY_1493_DATA 0x00000000 +#define DDRSS_PHY_1494_DATA 0x00000000 +#define DDRSS_PHY_1495_DATA 0x00000000 +#define DDRSS_PHY_1496_DATA 0x00000000 +#define DDRSS_PHY_1497_DATA 0x00000000 +#define DDRSS_PHY_1498_DATA 0x00000000 +#define DDRSS_PHY_1499_DATA 0x00000000 +#define DDRSS_PHY_1500_DATA 0x00000000 +#define DDRSS_PHY_1501_DATA 0x00000000 +#define DDRSS_PHY_1502_DATA 0x00000000 +#define DDRSS_PHY_1503_DATA 0x00000000 +#define DDRSS_PHY_1504_DATA 0x00000000 +#define DDRSS_PHY_1505_DATA 0x00000000 +#define DDRSS_PHY_1506_DATA 0x00000000 +#define DDRSS_PHY_1507_DATA 0x00000000 +#define DDRSS_PHY_1508_DATA 0x00000000 +#define DDRSS_PHY_1509_DATA 0x00000000 +#define DDRSS_PHY_1510_DATA 0x00000000 +#define DDRSS_PHY_1511_DATA 0x00000000 +#define DDRSS_PHY_1512_DATA 0x00000000 +#define DDRSS_PHY_1513_DATA 0x00000000 +#define DDRSS_PHY_1514_DATA 0x00000000 +#define DDRSS_PHY_1515_DATA 0x00000000 +#define DDRSS_PHY_1516_DATA 0x00000000 +#define DDRSS_PHY_1517_DATA 0x00000000 +#define DDRSS_PHY_1518_DATA 0x00000000 +#define DDRSS_PHY_1519_DATA 0x00000000 +#define DDRSS_PHY_1520_DATA 0x00000000 +#define DDRSS_PHY_1521_DATA 0x00000000 +#define DDRSS_PHY_1522_DATA 0x00000000 +#define DDRSS_PHY_1523_DATA 0x00000000 +#define DDRSS_PHY_1524_DATA 0x00000000 +#define DDRSS_PHY_1525_DATA 0x00000000 +#define DDRSS_PHY_1526_DATA 0x00000000 +#define DDRSS_PHY_1527_DATA 0x00000000 +#define DDRSS_PHY_1528_DATA 0x00000000 +#define DDRSS_PHY_1529_DATA 0x00000000 +#define DDRSS_PHY_1530_DATA 0x00000000 +#define DDRSS_PHY_1531_DATA 0x00000000 +#define DDRSS_PHY_1532_DATA 0x00000000 +#define DDRSS_PHY_1533_DATA 0x00000000 +#define DDRSS_PHY_1534_DATA 0x00000000 +#define DDRSS_PHY_1535_DATA 0x00000000 +#define DDRSS_PHY_1536_DATA 0x00000000 +#define DDRSS_PHY_1537_DATA 0x00000000 +#define DDRSS_PHY_1538_DATA 0x00000000 +#define DDRSS_PHY_1539_DATA 0x00000000 +#define DDRSS_PHY_1540_DATA 0x00000000 +#define DDRSS_PHY_1541_DATA 0x00000100 +#define DDRSS_PHY_1542_DATA 0x00000200 +#define DDRSS_PHY_1543_DATA 0x00000000 +#define DDRSS_PHY_1544_DATA 0x00000000 +#define DDRSS_PHY_1545_DATA 0x00000000 +#define DDRSS_PHY_1546_DATA 0x00000000 +#define DDRSS_PHY_1547_DATA 0x00400000 +#define DDRSS_PHY_1548_DATA 0x00000080 +#define DDRSS_PHY_1549_DATA 0x00DCBA98 +#define DDRSS_PHY_1550_DATA 0x03000000 +#define DDRSS_PHY_1551_DATA 0x00200000 +#define DDRSS_PHY_1552_DATA 0x00000000 +#define DDRSS_PHY_1553_DATA 0x00000000 +#define DDRSS_PHY_1554_DATA 0x00000000 +#define DDRSS_PHY_1555_DATA 0x00000000 +#define DDRSS_PHY_1556_DATA 0x00000000 +#define DDRSS_PHY_1557_DATA 0x0000002A +#define DDRSS_PHY_1558_DATA 0x00000015 +#define DDRSS_PHY_1559_DATA 0x00000015 +#define DDRSS_PHY_1560_DATA 0x0000002A +#define DDRSS_PHY_1561_DATA 0x00000033 +#define DDRSS_PHY_1562_DATA 0x0000000C +#define DDRSS_PHY_1563_DATA 0x0000000C +#define DDRSS_PHY_1564_DATA 0x00000033 +#define DDRSS_PHY_1565_DATA 0x0A418820 +#define DDRSS_PHY_1566_DATA 0x10000000 +#define DDRSS_PHY_1567_DATA 0x000F0000 +#define DDRSS_PHY_1568_DATA 0x20202003 +#define DDRSS_PHY_1569_DATA 0x00202020 +#define DDRSS_PHY_1570_DATA 0x20008008 +#define DDRSS_PHY_1571_DATA 0x00000810 +#define DDRSS_PHY_1572_DATA 0x00000F00 +#define DDRSS_PHY_1573_DATA 0x000304CC +#define DDRSS_PHY_1574_DATA 0x03000003 +#define DDRSS_PHY_1575_DATA 0x00030000 +#define DDRSS_PHY_1576_DATA 0x00000300 +#define DDRSS_PHY_1577_DATA 0x00000300 +#define DDRSS_PHY_1578_DATA 0x00000300 +#define DDRSS_PHY_1579_DATA 0x00000300 +#define DDRSS_PHY_1580_DATA 0x42080010 +#define DDRSS_PHY_1581_DATA 0x0000803E +#define DDRSS_PHY_1582_DATA 0x00000001 +#define DDRSS_PHY_1583_DATA 0x01000002 +#define DDRSS_PHY_1584_DATA 0x00008000 +#define DDRSS_PHY_1585_DATA 0x00000000 +#define DDRSS_PHY_1586_DATA 0x00000000 +#define DDRSS_PHY_1587_DATA 0x00000000 +#define DDRSS_PHY_1588_DATA 0x00000000 +#define DDRSS_PHY_1589_DATA 0x00000000 +#define DDRSS_PHY_1590_DATA 0x00000000 +#define DDRSS_PHY_1591_DATA 0x00000000 +#define DDRSS_PHY_1592_DATA 0x00000000 +#define DDRSS_PHY_1593_DATA 0x00000000 +#define DDRSS_PHY_1594_DATA 0x00000000 +#define DDRSS_PHY_1595_DATA 0x00000000 +#define DDRSS_PHY_1596_DATA 0x00000000 +#define DDRSS_PHY_1597_DATA 0x00000000 +#define DDRSS_PHY_1598_DATA 0x00000000 +#define DDRSS_PHY_1599_DATA 0x00000000 +#define DDRSS_PHY_1600_DATA 0x00000000 +#define DDRSS_PHY_1601_DATA 0x00000000 +#define DDRSS_PHY_1602_DATA 0x00000000 +#define DDRSS_PHY_1603_DATA 0x00000000 +#define DDRSS_PHY_1604_DATA 0x00000000 +#define DDRSS_PHY_1605_DATA 0x00000000 +#define DDRSS_PHY_1606_DATA 0x00000000 +#define DDRSS_PHY_1607_DATA 0x00000000 +#define DDRSS_PHY_1608_DATA 0x00000000 +#define DDRSS_PHY_1609_DATA 0x00000000 +#define DDRSS_PHY_1610_DATA 0x00000000 +#define DDRSS_PHY_1611_DATA 0x00000000 +#define DDRSS_PHY_1612_DATA 0x00000000 +#define DDRSS_PHY_1613_DATA 0x00000000 +#define DDRSS_PHY_1614_DATA 0x00000000 +#define DDRSS_PHY_1615_DATA 0x00000000 +#define DDRSS_PHY_1616_DATA 0x00000000 +#define DDRSS_PHY_1617_DATA 0x00000000 +#define DDRSS_PHY_1618_DATA 0x00000000 +#define DDRSS_PHY_1619_DATA 0x00000000 +#define DDRSS_PHY_1620_DATA 0x00000000 +#define DDRSS_PHY_1621_DATA 0x00000000 +#define DDRSS_PHY_1622_DATA 0x00000000 +#define DDRSS_PHY_1623_DATA 0x00000000 +#define DDRSS_PHY_1624_DATA 0x00000000 +#define DDRSS_PHY_1625_DATA 0x00000000 +#define DDRSS_PHY_1626_DATA 0x00000000 +#define DDRSS_PHY_1627_DATA 0x00000000 +#define DDRSS_PHY_1628_DATA 0x00000000 +#define DDRSS_PHY_1629_DATA 0x00000000 +#define DDRSS_PHY_1630_DATA 0x00000000 +#define DDRSS_PHY_1631_DATA 0x00000000 +#define DDRSS_PHY_1632_DATA 0x00000000 +#define DDRSS_PHY_1633_DATA 0x00000000 +#define DDRSS_PHY_1634_DATA 0x00000000 +#define DDRSS_PHY_1635_DATA 0x00000000 +#define DDRSS_PHY_1636_DATA 0x00000000 +#define DDRSS_PHY_1637_DATA 0x00000000 +#define DDRSS_PHY_1638_DATA 0x00000000 +#define DDRSS_PHY_1639_DATA 0x00000000 +#define DDRSS_PHY_1640_DATA 0x00000000 +#define DDRSS_PHY_1641_DATA 0x00000000 +#define DDRSS_PHY_1642_DATA 0x00000000 +#define DDRSS_PHY_1643_DATA 0x00000000 +#define DDRSS_PHY_1644_DATA 0x00000000 +#define DDRSS_PHY_1645_DATA 0x00000000 +#define DDRSS_PHY_1646_DATA 0x00000000 +#define DDRSS_PHY_1647_DATA 0x00000000 +#define DDRSS_PHY_1648_DATA 0x00000000 +#define DDRSS_PHY_1649_DATA 0x00000000 +#define DDRSS_PHY_1650_DATA 0x00000000 +#define DDRSS_PHY_1651_DATA 0x00000000 +#define DDRSS_PHY_1652_DATA 0x00000000 +#define DDRSS_PHY_1653_DATA 0x00000000 +#define DDRSS_PHY_1654_DATA 0x00000000 +#define DDRSS_PHY_1655_DATA 0x00000000 +#define DDRSS_PHY_1656_DATA 0x00000000 +#define DDRSS_PHY_1657_DATA 0x00000000 +#define DDRSS_PHY_1658_DATA 0x00000000 +#define DDRSS_PHY_1659_DATA 0x00000000 +#define DDRSS_PHY_1660_DATA 0x00000000 +#define DDRSS_PHY_1661_DATA 0x00000000 +#define DDRSS_PHY_1662_DATA 0x00000000 +#define DDRSS_PHY_1663_DATA 0x00000000 +#define DDRSS_PHY_1664_DATA 0x00000000 +#define DDRSS_PHY_1665_DATA 0x00000000 +#define DDRSS_PHY_1666_DATA 0x00000000 +#define DDRSS_PHY_1667_DATA 0x00000000 +#define DDRSS_PHY_1668_DATA 0x00000000 +#define DDRSS_PHY_1669_DATA 0x00000000 +#define DDRSS_PHY_1670_DATA 0x00000000 +#define DDRSS_PHY_1671_DATA 0x00000000 +#define DDRSS_PHY_1672_DATA 0x00000000 +#define DDRSS_PHY_1673_DATA 0x00000000 +#define DDRSS_PHY_1674_DATA 0x00000000 +#define DDRSS_PHY_1675_DATA 0x00000000 +#define DDRSS_PHY_1676_DATA 0x00000000 +#define DDRSS_PHY_1677_DATA 0x00000000 +#define DDRSS_PHY_1678_DATA 0x00000000 +#define DDRSS_PHY_1679_DATA 0x00000000 +#define DDRSS_PHY_1680_DATA 0x00000000 +#define DDRSS_PHY_1681_DATA 0x00000000 +#define DDRSS_PHY_1682_DATA 0x00000000 +#define DDRSS_PHY_1683_DATA 0x00000000 +#define DDRSS_PHY_1684_DATA 0x00000000 +#define DDRSS_PHY_1685_DATA 0x00000000 +#define DDRSS_PHY_1686_DATA 0x00000000 +#define DDRSS_PHY_1687_DATA 0x00000000 +#define DDRSS_PHY_1688_DATA 0x00000000 +#define DDRSS_PHY_1689_DATA 0x00000000 +#define DDRSS_PHY_1690_DATA 0x00000000 +#define DDRSS_PHY_1691_DATA 0x00000000 +#define DDRSS_PHY_1692_DATA 0x00000000 +#define DDRSS_PHY_1693_DATA 0x00000000 +#define DDRSS_PHY_1694_DATA 0x00000000 +#define DDRSS_PHY_1695_DATA 0x00000000 +#define DDRSS_PHY_1696_DATA 0x00000000 +#define DDRSS_PHY_1697_DATA 0x00000000 +#define DDRSS_PHY_1698_DATA 0x00000000 +#define DDRSS_PHY_1699_DATA 0x00000000 +#define DDRSS_PHY_1700_DATA 0x00000000 +#define DDRSS_PHY_1701_DATA 0x00000000 +#define DDRSS_PHY_1702_DATA 0x00000000 +#define DDRSS_PHY_1703_DATA 0x00000000 +#define DDRSS_PHY_1704_DATA 0x00000000 +#define DDRSS_PHY_1705_DATA 0x00000000 +#define DDRSS_PHY_1706_DATA 0x00000000 +#define DDRSS_PHY_1707_DATA 0x00000000 +#define DDRSS_PHY_1708_DATA 0x00000000 +#define DDRSS_PHY_1709_DATA 0x00000000 +#define DDRSS_PHY_1710_DATA 0x00000000 +#define DDRSS_PHY_1711_DATA 0x00000000 +#define DDRSS_PHY_1712_DATA 0x00000000 +#define DDRSS_PHY_1713_DATA 0x00000000 +#define DDRSS_PHY_1714_DATA 0x00000000 +#define DDRSS_PHY_1715_DATA 0x00000000 +#define DDRSS_PHY_1716_DATA 0x00000000 +#define DDRSS_PHY_1717_DATA 0x00000000 +#define DDRSS_PHY_1718_DATA 0x00000000 +#define DDRSS_PHY_1719_DATA 0x00000000 +#define DDRSS_PHY_1720_DATA 0x00000000 +#define DDRSS_PHY_1721_DATA 0x00000000 +#define DDRSS_PHY_1722_DATA 0x00000000 +#define DDRSS_PHY_1723_DATA 0x00000000 +#define DDRSS_PHY_1724_DATA 0x00000000 +#define DDRSS_PHY_1725_DATA 0x00000000 +#define DDRSS_PHY_1726_DATA 0x00000000 +#define DDRSS_PHY_1727_DATA 0x00000000 +#define DDRSS_PHY_1728_DATA 0x00000000 +#define DDRSS_PHY_1729_DATA 0x00000000 +#define DDRSS_PHY_1730_DATA 0x00000000 +#define DDRSS_PHY_1731_DATA 0x00000000 +#define DDRSS_PHY_1732_DATA 0x00000000 +#define DDRSS_PHY_1733_DATA 0x00000000 +#define DDRSS_PHY_1734_DATA 0x00000000 +#define DDRSS_PHY_1735_DATA 0x00000000 +#define DDRSS_PHY_1736_DATA 0x00000000 +#define DDRSS_PHY_1737_DATA 0x00000000 +#define DDRSS_PHY_1738_DATA 0x00000000 +#define DDRSS_PHY_1739_DATA 0x00000000 +#define DDRSS_PHY_1740_DATA 0x00000000 +#define DDRSS_PHY_1741_DATA 0x00000000 +#define DDRSS_PHY_1742_DATA 0x00000000 +#define DDRSS_PHY_1743_DATA 0x00000000 +#define DDRSS_PHY_1744_DATA 0x00000000 +#define DDRSS_PHY_1745_DATA 0x00000000 +#define DDRSS_PHY_1746_DATA 0x00000000 +#define DDRSS_PHY_1747_DATA 0x00000000 +#define DDRSS_PHY_1748_DATA 0x00000000 +#define DDRSS_PHY_1749_DATA 0x00000000 +#define DDRSS_PHY_1750_DATA 0x00000000 +#define DDRSS_PHY_1751_DATA 0x00000000 +#define DDRSS_PHY_1752_DATA 0x00000000 +#define DDRSS_PHY_1753_DATA 0x00000000 +#define DDRSS_PHY_1754_DATA 0x00000000 +#define DDRSS_PHY_1755_DATA 0x00000000 +#define DDRSS_PHY_1756_DATA 0x00000000 +#define DDRSS_PHY_1757_DATA 0x00000000 +#define DDRSS_PHY_1758_DATA 0x00000000 +#define DDRSS_PHY_1759_DATA 0x00000000 +#define DDRSS_PHY_1760_DATA 0x00000000 +#define DDRSS_PHY_1761_DATA 0x00000000 +#define DDRSS_PHY_1762_DATA 0x00000000 +#define DDRSS_PHY_1763_DATA 0x00000000 +#define DDRSS_PHY_1764_DATA 0x00000000 +#define DDRSS_PHY_1765_DATA 0x00000000 +#define DDRSS_PHY_1766_DATA 0x00000000 +#define DDRSS_PHY_1767_DATA 0x00000000 +#define DDRSS_PHY_1768_DATA 0x00000000 +#define DDRSS_PHY_1769_DATA 0x00000000 +#define DDRSS_PHY_1770_DATA 0x00000000 +#define DDRSS_PHY_1771_DATA 0x00000000 +#define DDRSS_PHY_1772_DATA 0x00000000 +#define DDRSS_PHY_1773_DATA 0x00000000 +#define DDRSS_PHY_1774_DATA 0x00000000 +#define DDRSS_PHY_1775_DATA 0x00000000 +#define DDRSS_PHY_1776_DATA 0x00000000 +#define DDRSS_PHY_1777_DATA 0x00000000 +#define DDRSS_PHY_1778_DATA 0x00000000 +#define DDRSS_PHY_1779_DATA 0x00000000 +#define DDRSS_PHY_1780_DATA 0x00000000 +#define DDRSS_PHY_1781_DATA 0x00000000 +#define DDRSS_PHY_1782_DATA 0x00000000 +#define DDRSS_PHY_1783_DATA 0x00000000 +#define DDRSS_PHY_1784_DATA 0x00000000 +#define DDRSS_PHY_1785_DATA 0x00000000 +#define DDRSS_PHY_1786_DATA 0x00000000 +#define DDRSS_PHY_1787_DATA 0x00000000 +#define DDRSS_PHY_1788_DATA 0x00000000 +#define DDRSS_PHY_1789_DATA 0x00000000 +#define DDRSS_PHY_1790_DATA 0x00000000 +#define DDRSS_PHY_1791_DATA 0x00000000 +#define DDRSS_PHY_1792_DATA 0x00000000 +#define DDRSS_PHY_1793_DATA 0x00010100 +#define DDRSS_PHY_1794_DATA 0x00000000 +#define DDRSS_PHY_1795_DATA 0x00000000 +#define DDRSS_PHY_1796_DATA 0x00000000 +#define DDRSS_PHY_1797_DATA 0x00000000 +#define DDRSS_PHY_1798_DATA 0x00050000 +#define DDRSS_PHY_1799_DATA 0x04000000 +#define DDRSS_PHY_1800_DATA 0x00000055 +#define DDRSS_PHY_1801_DATA 0x00000000 +#define DDRSS_PHY_1802_DATA 0x00000000 +#define DDRSS_PHY_1803_DATA 0x00000000 +#define DDRSS_PHY_1804_DATA 0x00000000 +#define DDRSS_PHY_1805_DATA 0x00002001 +#define DDRSS_PHY_1806_DATA 0x00004003 +#define DDRSS_PHY_1807_DATA 0x50020028 +#define DDRSS_PHY_1808_DATA 0x01010000 +#define DDRSS_PHY_1809_DATA 0x80080001 +#define DDRSS_PHY_1810_DATA 0x10200000 +#define DDRSS_PHY_1811_DATA 0x00000008 +#define DDRSS_PHY_1812_DATA 0x00000000 +#define DDRSS_PHY_1813_DATA 0x06000000 +#define DDRSS_PHY_1814_DATA 0x010F0F0E +#define DDRSS_PHY_1815_DATA 0x00040101 +#define DDRSS_PHY_1816_DATA 0x0000010F +#define DDRSS_PHY_1817_DATA 0x00000000 +#define DDRSS_PHY_1818_DATA 0x00000064 +#define DDRSS_PHY_1819_DATA 0x00000000 +#define DDRSS_PHY_1820_DATA 0x00000000 +#define DDRSS_PHY_1821_DATA 0x0F0F0F01 +#define DDRSS_PHY_1822_DATA 0x0F0F0F02 +#define DDRSS_PHY_1823_DATA 0x0F0F0F0F +#define DDRSS_PHY_1824_DATA 0x0F0F0804 +#define DDRSS_PHY_1825_DATA 0x00800120 +#define DDRSS_PHY_1826_DATA 0x00041B42 +#define DDRSS_PHY_1827_DATA 0x00004201 +#define DDRSS_PHY_1828_DATA 0x00000000 +#define DDRSS_PHY_1829_DATA 0x00000000 +#define DDRSS_PHY_1830_DATA 0x00000000 +#define DDRSS_PHY_1831_DATA 0x00000000 +#define DDRSS_PHY_1832_DATA 0x00000000 +#define DDRSS_PHY_1833_DATA 0x00000000 +#define DDRSS_PHY_1834_DATA 0x03010100 +#define DDRSS_PHY_1835_DATA 0x00540007 +#define DDRSS_PHY_1836_DATA 0x000040A2 +#define DDRSS_PHY_1837_DATA 0x00024410 +#define DDRSS_PHY_1838_DATA 0x00004410 +#define DDRSS_PHY_1839_DATA 0x00004410 +#define DDRSS_PHY_1840_DATA 0x00004410 +#define DDRSS_PHY_1841_DATA 0x00004410 +#define DDRSS_PHY_1842_DATA 0x00004410 +#define DDRSS_PHY_1843_DATA 0x00004410 +#define DDRSS_PHY_1844_DATA 0x00004410 +#define DDRSS_PHY_1845_DATA 0x00004410 +#define DDRSS_PHY_1846_DATA 0x00004410 +#define DDRSS_PHY_1847_DATA 0x00000000 +#define DDRSS_PHY_1848_DATA 0x00000076 +#define DDRSS_PHY_1849_DATA 0x00000400 +#define DDRSS_PHY_1850_DATA 0x00000008 +#define DDRSS_PHY_1851_DATA 0x00000000 +#define DDRSS_PHY_1852_DATA 0x00000000 +#define DDRSS_PHY_1853_DATA 0x00000000 +#define DDRSS_PHY_1854_DATA 0x00000000 +#define DDRSS_PHY_1855_DATA 0x00000000 +#define DDRSS_PHY_1856_DATA 0x03000000 +#define DDRSS_PHY_1857_DATA 0x00000000 +#define DDRSS_PHY_1858_DATA 0x00000000 +#define DDRSS_PHY_1859_DATA 0x00000000 +#define DDRSS_PHY_1860_DATA 0x04102006 +#define DDRSS_PHY_1861_DATA 0x00041020 +#define DDRSS_PHY_1862_DATA 0x01C98C98 +#define DDRSS_PHY_1863_DATA 0x3F400000 +#define DDRSS_PHY_1864_DATA 0x3F3F1F3F +#define DDRSS_PHY_1865_DATA 0x0000001F +#define DDRSS_PHY_1866_DATA 0x00000000 +#define DDRSS_PHY_1867_DATA 0x00000000 +#define DDRSS_PHY_1868_DATA 0x00000000 +#define DDRSS_PHY_1869_DATA 0x00000001 +#define DDRSS_PHY_1870_DATA 0x00000000 +#define DDRSS_PHY_1871_DATA 0x00000000 +#define DDRSS_PHY_1872_DATA 0x00000000 +#define DDRSS_PHY_1873_DATA 0x00000000 +#define DDRSS_PHY_1874_DATA 0x76543210 +#define DDRSS_PHY_1875_DATA 0x06010198 +#define DDRSS_PHY_1876_DATA 0x00000000 +#define DDRSS_PHY_1877_DATA 0x00000000 +#define DDRSS_PHY_1878_DATA 0x00000000 +#define DDRSS_PHY_1879_DATA 0x00040700 +#define DDRSS_PHY_1880_DATA 0x00000000 +#define DDRSS_PHY_1881_DATA 0x00000000 +#define DDRSS_PHY_1882_DATA 0x00000000 +#define DDRSS_PHY_1883_DATA 0x00000000 +#define DDRSS_PHY_1884_DATA 0x00000000 +#define DDRSS_PHY_1885_DATA 0x00000002 +#define DDRSS_PHY_1886_DATA 0x00000000 +#define DDRSS_PHY_1887_DATA 0x00000000 +#define DDRSS_PHY_1888_DATA 0x0001F7C3 +#define DDRSS_PHY_1889_DATA 0x03000003 +#define DDRSS_PHY_1890_DATA 0x00000000 +#define DDRSS_PHY_1891_DATA 0x00001142 +#define DDRSS_PHY_1892_DATA 0x01020000 +#define DDRSS_PHY_1893_DATA 0x00000080 +#define DDRSS_PHY_1894_DATA 0x03900390 +#define DDRSS_PHY_1895_DATA 0x03900390 +#define DDRSS_PHY_1896_DATA 0x03900390 +#define DDRSS_PHY_1897_DATA 0x03900390 +#define DDRSS_PHY_1898_DATA 0x03000300 +#define DDRSS_PHY_1899_DATA 0x03000300 +#define DDRSS_PHY_1900_DATA 0x00000300 +#define DDRSS_PHY_1901_DATA 0x00000300 +#define DDRSS_PHY_1902_DATA 0x00000300 +#define DDRSS_PHY_1903_DATA 0x00000300 +#define DDRSS_PHY_1904_DATA 0x00000004 +#define DDRSS_PHY_1905_DATA 0x3183BF77 +#define DDRSS_PHY_1906_DATA 0x00000000 +#define DDRSS_PHY_1907_DATA 0x0C000DFF +#define DDRSS_PHY_1908_DATA 0x30000DFF +#define DDRSS_PHY_1909_DATA 0x3F0DFF11 +#define DDRSS_PHY_1910_DATA 0x00EF0000 +#define DDRSS_PHY_1911_DATA 0x780DFFCC +#define DDRSS_PHY_1912_DATA 0x00000C11 +#define DDRSS_PHY_1913_DATA 0x00018011 +#define DDRSS_PHY_1914_DATA 0x0089FF00 +#define DDRSS_PHY_1915_DATA 0x000C3F11 +#define DDRSS_PHY_1916_DATA 0x01990000 +#define DDRSS_PHY_1917_DATA 0x000C3F11 +#define DDRSS_PHY_1918_DATA 0x01990000 +#define DDRSS_PHY_1919_DATA 0x3F0DFF11 +#define DDRSS_PHY_1920_DATA 0x00EF0000 +#define DDRSS_PHY_1921_DATA 0x00018011 +#define DDRSS_PHY_1922_DATA 0x0089FF00 +#define DDRSS_PHY_1923_DATA 0x20040005 diff --git a/arch/arm/dts/k3-am62p-main.dtsi b/arch/arm/dts/k3-am62p-main.dtsi new file mode 100644 index 0000000000..0994cff30d --- /dev/null +++ b/arch/arm/dts/k3-am62p-main.dtsi @@ -0,0 +1,1106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P main domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + oc_sram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x70000000 0x10000>; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_conf: bus@100000 { + compatible = "simple-bus"; + reg = <0x00 0x00100000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x20000>; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; + + epwm_tbclk: clock-controller@4130 { + compatible = "ti,am62-epwm-tbclk"; + reg = <0x4130 0x4>; + #clock-cells = <1>; + }; + + dss_oldi_io_ctrl: dss-oldi-io-ctrl@8600 { + compatible = "syscon"; + reg = <0x8600 0x200>; + }; + }; + + dmss: bus@48000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; + bootph-all; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d000000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + interrupt-names = "rx_012"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + bootph-all; + }; + + inta_main_dmss: interrupt-controller@48000000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x48000000 0x00 0x100000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <28>; + ti,interrupt-ranges = <5 69 35>; + ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; + }; + + main_bcdma: dma-controller@485c0100 { + compatible = "ti,am64-dmss-bcdma"; + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <3>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <26>; + ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ + ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ + ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ + bootph-all; + }; + + main_pktdma: dma-controller@485c0000 { + compatible = "ti,am64-dmss-pktdma"; + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <2>; + bootph-all; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <30>; + ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ + <0x24>, /* CPSW_TX_CHAN */ + <0x25>, /* SAUL_TX_0_CHAN */ + <0x26>; /* SAUL_TX_1_CHAN */ + ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ + <0x11>, /* RING_CPSW_TX_CHAN */ + <0x12>, /* RING_SAUL_TX_0_CHAN */ + <0x13>; /* RING_SAUL_TX_1_CHAN */ + ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ + <0x2b>, /* CPSW_RX_CHAN */ + <0x2d>, /* SAUL_RX_0_CHAN */ + <0x2f>, /* SAUL_RX_1_CHAN */ + <0x31>, /* SAUL_RX_2_CHAN */ + <0x33>; /* SAUL_RX_3_CHAN */ + ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ + <0x2c>, /* FLOW_CPSW_RX_CHAN */ + <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ + <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ + }; + }; + + dmss_csi: bus@4e000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>; + + ti,sci-dev-id = <198>; + + inta_main_dmss_csi: interrupt-controller@4e400000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x4e400000 0x00 0x8000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <200>; + ti,interrupt-ranges = <0 237 8>; + ti,unmapped-event-sources = <&main_bcdma_csi>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + }; + + main_bcdma_csi: dma-controller@4e230000 { + compatible = "ti,am62a-dmss-bcdma-csirx"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x8000>, + <0x00 0x4e100000 0x00 0x10000>; + reg-names = "gcfg", "rchanrt", "ringrt"; + msi-parent = <&inta_main_dmss_csi>; + #dma-cells = <3>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <199>; + ti,sci-rm-range-rchan = <0x21>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + }; + }; + + dmsc: system-controller@44043000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes = <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + reg-names = "debug_messages"; + reg = <0x00 0x44043000 0x00 0xfe0>; + bootph-all; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + bootph-all; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + bootph-all; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + bootph-all; + }; + }; + + crypto: crypto@40900000 { + compatible = "ti,am62-sa3ul"; + reg = <0x00 0x40900000 0x00 0x1200>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + + dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, + <&main_pktdma 0x7507 0>; + dma-names = "tx", "rx1", "rx2"; + }; + + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + bootph-all; + }; + + main_pmx0: pinctrl@f4000 { + compatible = "pinctrl-single"; + reg = <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + bootph-all; + }; + + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x420000 0x00 0x1000>; + ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; + bootph-pre-ram; + }; + + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + bootph-all; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 37 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 2>; + assigned-clock-parents = <&k3_clks 37 3>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 38 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 2>; + assigned-clock-parents = <&k3_clks 38 3>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 39 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 2>; + assigned-clock-parents = <&k3_clks 39 3>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 40 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 2>; + assigned-clock-parents = <&k3_clks 40 3>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 41 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 2>; + assigned-clock-parents = <&k3_clks 41 3>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 42 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 2>; + assigned-clock-parents = <&k3_clks 42 3>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 43 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 2>; + assigned-clock-parents = <&k3_clks 43 3>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 154 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 155 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_i2c0: i2c@20000000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20000000 0x00 0x100>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c1: i2c@20010000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20010000 0x00 0x100>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 103 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c2: i2c@20020000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20020000 0x00 0x100>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 104 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c3: i2c@20030000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20030000 0x00 0x100>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 2>; + clock-names = "fck"; + status = "disabled"; + }; + + vpu: video-codec@30210000 { + compatible = "cnm,cm521c-vpu"; + reg = <0x00 0x30210000 0x00 0x10000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 204 2>; + clock-names = "vcodec"; + power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; + }; + + main_spi0: spi@20100000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x20100000 0x00 0x400>; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 141 0>; + status = "disabled"; + }; + + main_spi1: spi@20110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20110000 0x00 0x400>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 142 0>; + status = "disabled"; + }; + + main_spi2: spi@20120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20120000 0x00 0x400>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 143 0>; + status = "disabled"; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <3>; + ti,interrupt-ranges = <0 32 16>; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <190>, <191>, <192>, + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <92>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 77 0>; + clock-names = "gpio"; + }; + + main_gpio1: gpio@601000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00601000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <180>, <181>, <182>, + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <52>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 78 0>; + clock-names = "gpio"; + }; + + sdhci0: mmc@fa10000 { + compatible = "ti,am64-sdhci-8bit"; + reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 1>, <&k3_clks 57 2>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 2>; + assigned-clock-parents = <&k3_clks 57 4>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + ti,clkbuf-sel = <0x7>; + ti,strobe-sel = <0x77>; + ti,trm-icp = <0x8>; + ti,otap-del-sel-legacy = <0x1>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0x8>; + ti,otap-del-sel-ddr50 = <0x5>; + ti,otap-del-sel-sdr104 = <0x8>; + ti,otap-del-sel-hs200 = <0x5>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-sdr12 = <0x8>; + ti,itap-del-sel-sdr25 = <0x8>; + status = "disabled"; + }; + + sdhci1: mmc@fa00000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; + clock-names = "clk_ahb", "clk_xin"; + ti,otap-del-sel-legacy = <0x8>; + bus-width = <4>; + status = "disabled"; + no-1-8-v; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; + ti,otap-del-sel-legacy = <0x8>; + status = "disabled"; + }; + + usbss0: dwc3-usb@f900000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f900000 0x00 0x800>; + clocks = <&k3_clks 161 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb0: usb@31000000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31000000 0x00 0x50000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + usbss1: dwc3-usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>; + clocks = <&k3_clks 162 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31100000 0x00 0x50000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + fss: bus@fc00000 { + compatible = "simple-bus"; + reg = <0x00 0x0fc00000 0x00 0x70000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ospi0: spi@fc40000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 75 7>; + assigned-clocks = <&k3_clks 75 7>; + assigned-clock-parents = <&k3_clks 75 8>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + cpsw3g: ethernet@8000000 { + compatible = "ti,am642-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0x08000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; + clocks = <&k3_clks 13 0>; + assigned-clocks = <&k3_clks 13 3>; + assigned-clock-parents = <&k3_clks 13 11>; + clock-names = "fck"; + power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_pktdma 0xc600 15>, + <&main_pktdma 0xc601 15>, + <&main_pktdma 0xc602 15>, + <&main_pktdma 0xc603 15>, + <&main_pktdma 0xc604 15>, + <&main_pktdma 0xc605 15>, + <&main_pktdma 0xc606 15>, + <&main_pktdma 0xc607 15>, + <&main_pktdma 0x4600 15>; + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", + "tx7", "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel 1>; + mac-address = [00 00 00 00 00 00]; + }; + + cpsw_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + phys = <&phy_gmii_sel 2>; + mac-address = [00 00 00 00 00 00]; + }; + }; + + cpsw3g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 13 0>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 13 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + hwspinlock: spinlock@2a000000 { + compatible = "ti,am64-hwspinlock"; + reg = <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + + mailbox0_cluster0: mailbox@29000000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29000000 0x00 0x200>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster1: mailbox@29010000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29010000 0x00 0x200>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster2: mailbox@29020000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29020000 0x00 0x200>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + mailbox0_cluster3: mailbox@29030000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29030000 0x00 0x200>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; + + ecap0: pwm@23100000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23100000 0x00 0x100>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 51 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23110000 0x00 0x100>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 52 0>; + clock-names = "fck"; + status = "disabled"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23120000 0x00 0x100>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 53 0>; + clock-names = "fck"; + status = "disabled"; + }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan1: can@20711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20711000 0x00 0x200>, + <0x00 0x20718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 99 6>, <&k3_clks 99 1>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_rti0: watchdog@e000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + + main_rti2: watchdog@e020000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e020000 0x00 0x100>; + clocks = <&k3_clks 127 0>; + power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 127 0>; + assigned-clock-parents = <&k3_clks 127 2>; + }; + + main_rti3: watchdog@e030000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e030000 0x00 0x100>; + clocks = <&k3_clks 128 0>; + power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 128 0>; + assigned-clock-parents = <&k3_clks 128 2>; + }; + + main_rti15: watchdog@e0f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e0f0000 0x00 0x100>; + clocks = <&k3_clks 130 0>; + power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 130 0>; + assigned-clock-parents = <&k3_clks 130 2>; + }; + + epwm0: pwm@23000000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23000000 0x00 0x100>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm1: pwm@23010000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23010000 0x00 0x100>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm2: pwm@23020000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23020000 0x00 0x100>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + mcasp0: audio-controller@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b00000 0x00 0x2000>, + <0x00 0x02b08000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 190 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 190 0>; + assigned-clock-parents = <&k3_clks 190 2>; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp1: audio-controller@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b10000 0x00 0x2000>, + <0x00 0x02b18000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 191 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 191 0>; + assigned-clock-parents = <&k3_clks 191 2>; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp2: audio-controller@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b20000 0x00 0x2000>, + <0x00 0x02b28000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 192 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 192 0>; + assigned-clock-parents = <&k3_clks 192 2>; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dss0: dss@30200000 { + compatible = "ti,am62p51-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>, /* DSS0 */ + <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>, /* OLDI0 */ + <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; /* OLDI1 */ + clocks = <&k3_clks 186 6>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + dss0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gpu: gpu@fd80000 { + compatible = "ti,am62p-pvr", "img,pvr-bxs64"; + reg = <0x00 0x0fd80000 0x00 0x80000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 237 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 237 3>; + assigned-clock-rates = <720000000>; + power-domain-names = "firmware", "dust"; + clocks = <&k3_clks 237 3>; + clock-names = "core"; + }; + + ti_csi2rx0: ticsi2rx@30102000 { + compatible = "ti,j721e-csi2rx"; + dmas = <&main_bcdma_csi 0 0x5000 0>, <&main_bcdma_csi 0 0x5001 0>, + <&main_bcdma_csi 0 0x5002 0>, <&main_bcdma_csi 0 0x5003 0>, + <&main_bcdma_csi 0 0x5004 0>, <&main_bcdma_csi 0 0x5005 0>; + dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5"; + reg = <0x00 0x30102000 0x00 0x1000>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@30101000 { + compatible = "cdns,csi2rx"; + reg = <0x00 0x30101000 0x00 0x1000>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, + <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@30110000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30110000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/k3-am62p-mcu.dtsi b/arch/arm/dts/k3-am62p-mcu.dtsi new file mode 100644 index 0000000000..c4b0b91d70 --- /dev/null +++ b/arch/arm/dts/k3-am62p-mcu.dtsi @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P MCU domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + bootph-all; + }; + + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x4100000 0x00 0x1000>; + ti,esm-pins = <0>, <1>, <2>, <85>; + status = "reserved"; + bootph-pre-ram; + }; + + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 2>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 2>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 2>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_uart0: serial@4a00000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x04a00000 0x00 0x100>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 149 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + mcu_i2c0: i2c@4900000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x04900000 0x00 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 106 2>; + clock-names = "fck"; + status = "disabled"; + }; + + mcu_spi0: spi@4b00000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x04b00000 0x00 0x400>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 147 0>; + status = "disabled"; + }; + + mcu_spi1: spi@4b10000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x04b10000 0x00 0x400>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 148 0>; + status = "disabled"; + }; + + mcu_gpio_intr: interrupt-controller@4210000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x04210000 0x00 0x200>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <5>; + ti,interrupt-ranges = <0 104 4>; + }; + + mcu_gpio0: gpio@4201000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x4201000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&mcu_gpio_intr>; + interrupts = <30>, <31>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <24>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 79 0>; + clock-names = "gpio"; + }; + + mcu_rti0: watchdog@4880000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x04880000 0x00 0x100>; + clocks = <&k3_clks 131 0>; + power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 131 0>; + assigned-clock-parents = <&k3_clks 131 2>; + /* Tightly coupled to M4F */ + status = "reserved"; + }; + + mcu_mcan0: can@4e08000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e08000 0x00 0x200>, + <0x00 0x4e00000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + status = "disabled"; + }; + + mcu_mcan1: can@4e18000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e18000 0x00 0x200>, + <0x00 0x4e10000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + status = "disabled"; + }; + + mcu_r5fss0: r5fss@79000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + mcu_r5fss0_core0: r5f@79000000 { + compatible = "ti,am62-r5f"; + reg = <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x03 0xff>; + resets = <&k3_reset 9 1>; + firmware-name = "am62p-mcu-r5f0_0-fw"; + ti,atcm-enable = <0>; + ti,btcm-enable = <1>; + ti,loczrama = <0>; + }; + }; +}; diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi new file mode 100644 index 0000000000..1c30ed8680 --- /dev/null +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -0,0 +1,517 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" + +#ifdef CONFIG_TARGET_AM62P5_R5_EVM + +&binman { + tiboot3-am62px-hs-evm.bin { + filename = "tiboot3-am62px-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>, + <&combined_dm_cfg>, <&sysfw_inner_cert>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl>; + content-sysfw = <&ti_fs_enc>; + content-sysfw-data = <&combined_tifs_cfg>; + content-sysfw-inner-cert = <&sysfw_inner_cert>; + content-dm-data = <&combined_dm_cfg>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c4a800>; + }; + u_boot_spl: u-boot-spl { + no-expanded; + }; + ti_fs_enc: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-am62px-hs-fs-evm.bin { + filename = "tiboot3-am62px-hs-fs-evm.bin"; + symlink = "tiboot3.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, + <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_fs_enc_fs>; + content-sysfw-data = <&combined_tifs_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + content-dm-data = <&combined_dm_cfg_fs>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c4a800>; + }; + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + ti_fs_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_fs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_fs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +#endif + +#ifdef CONFIG_TARGET_AM62P5_A53_EVM + +#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" +#define SPL_AM62PX_SK_DTB "spl/dts/k3-am62p5-sk.dtb" + +#define UBOOT_NODTB "u-boot-nodtb.bin" +#define AM62PX_SK_DTB "u-boot.dtb" + +&binman { + ti-dm { + filename = "ti-dm.bin"; + blob-ext { + filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + + fsstub-hs { + filename = "fsstub.bin_hs"; + ti-secure-rom { + content = <&fsstub_hs_cert>; + core = "secure"; + load = <0x60000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "custMpk.pem"; + countersign; + fsstub; + }; + fsstub_hs_cert: fsstub-hs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + fsstub_hs_enc: fsstub-hs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + + fsstub-fs { + filename = "fsstub.bin_fs"; + fsstub_fs_cert: fsstub-fs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + fsstub_fs_enc: fsstub-fs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + }; + + ti-spl { + filename = "tispl.bin"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = <CONFIG_K3_ATF_LOAD_ADDR>; + entry = <CONFIG_K3_ATF_LOAD_ADDR>; + ti-secure { + content = <&atf>; + keyfile = "custMpk.pem"; + }; + atf: atf-bl31 { + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + ti-secure { + content = <&tee>; + keyfile = "custMpk.pem"; + }; + tee: tee-os { + }; + }; + + fsstub-hs { + description = "FSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "fsstub-hs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "fsstub.bin_hs"; + }; + }; + + fsstub-fs { + description = "FSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "fsstub-fs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "fsstub.bin_fs"; + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + dm: blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_SPL_TEXT_BASE>; + entry = <CONFIG_SPL_TEXT_BASE>; + ti-secure { + content = <&u_boot_spl_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_spl_nodtb: blob-ext { + filename = SPL_NODTB; + }; + }; + + fdt-0 { + description = "k3-am62p5-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am62p5_sk_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am62p5_sk_dtb: blob-ext { + filename = SPL_AM62PX_SK_DTB; + }; + + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62px-sk"; + firmware = "atf"; + loadables = "tee", "fsstub-hs", "fsstub-fs", + "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + filename = "u-boot.img"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for AM62PX board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = <CONFIG_TEXT_BASE>; + ti-secure { + content = <&u_boot_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_nodtb: u-boot-nodtb { + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-am62px-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am62px_sk_dtb>; + keyfile = "custMpk.pem"; + }; + am62px_sk_dtb: blob-ext { + filename = AM62PX_SK_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62px-sk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + }; + }; + }; +}; + +&binman { + ti-spl_unsigned { + filename = "tispl.bin_unsigned"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = <CONFIG_K3_ATF_LOAD_ADDR>; + entry = <CONFIG_K3_ATF_LOAD_ADDR>; + atf-bl31 { + filename = "bl31.bin"; + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee-os { + filename = "tee-pager_v2.bin"; + }; + }; + + fsstub-hs { + description = "FSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "fsstub-hs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "fsstub.bin_hs"; + }; + }; + + fsstub-fs { + description = "FSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "fsstub-fs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "fsstub.bin_fs"; + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_SPL_TEXT_BASE>; + entry = <CONFIG_SPL_TEXT_BASE>; + blob { + filename = "spl/u-boot-spl-nodtb.bin"; + }; + }; + + fdt-0 { + description = "k3-am62px-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + spl_am62px_sk_dtb_unsigned: blob { + filename = SPL_AM62PX_SK_DTB; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62px-sk"; + firmware = "atf"; + loadables = "tee", "fsstub-hs", "fsstub-fs", + "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot_unsigned { + filename = "u-boot.img_unsigned"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for AM62PX board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = <CONFIG_TEXT_BASE>; + blob { + filename = UBOOT_NODTB; + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-am62px-sk"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + am62px_sk_dtb_unsigned: blob { + filename = AM62PX_SK_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62px-sk"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; +#endif diff --git a/arch/arm/dts/k3-am62p-thermal.dtsi b/arch/arm/dts/k3-am62p-thermal.dtsi new file mode 100644 index 0000000000..85ce545633 --- /dev/null +++ b/arch/arm/dts/k3-am62p-thermal.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/thermal/thermal.h> + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-am62p-wakeup.dtsi b/arch/arm/dts/k3-am62p-wakeup.dtsi new file mode 100644 index 0000000000..4c3a74cb97 --- /dev/null +++ b/arch/arm/dts/k3-am62p-wakeup.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P wakeup domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_wakeup { + wkup_conf: bus@43000000 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x43000000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x43000000 0x20000>; + bootph-all; + + chipid: chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + bootph-all; + }; + }; + + wkup_uart0: serial@2b300000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x2b300000 0x00 0x100>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + wkup_i2c0: i2c@2b200000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2b200000 0x00 0x100>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 107 4>; + clock-names = "fck"; + status = "disabled"; + }; + + wkup_rtc0: rtc@2b1f0000 { + compatible = "ti,am62-rtc"; + reg = <0x00 0x2b1f0000 0x00 0x100>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; + clock-names = "vbus", "osc32k"; + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; + wakeup-source; + }; + + wkup_rti0: watchdog@2b000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2b000000 0x00 0x100>; + clocks = <&k3_clks 132 0>; + power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 132 0>; + assigned-clock-parents = <&k3_clks 132 2>; + /* Used by DM firmware */ + status = "reserved"; + }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; + + wkup_r5fss0: r5fss@78000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + + wkup_r5fss0_core0: r5f@78000000 { + compatible = "ti,am62-r5f"; + reg = <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <121>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 121 1>; + firmware-name = "am62-wkup-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; +}; diff --git a/arch/arm/dts/k3-am62p.dtsi b/arch/arm/dts/k3-am62p.dtsi new file mode 100644 index 0000000000..d5046ec0b5 --- /dev/null +++ b/arch/arm/dts/k3-am62p.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62P SoC Family + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/ti,sci_pm_domain.h> + +#include "k3-pinctrl.h" + +/ { + model = "Texas Instruments K3 AM62P5 SoC"; + compatible = "ti,am62p5"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + bootph-all; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ + bootph-all; + }; + + cbass_wakeup: bus@b00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ + bootph-all; + }; + }; + + #include "k3-am62p-thermal.dtsi" +}; + +/* Now include peripherals for each bus segment */ +#include "k3-am62p-main.dtsi" +#include "k3-am62p-mcu.dtsi" +#include "k3-am62p-wakeup.dtsi" diff --git a/arch/arm/dts/k3-am62p5-r5-sk.dts b/arch/arm/dts/k3-am62p5-r5-sk.dts new file mode 100644 index 0000000000..658f2cf730 --- /dev/null +++ b/arch/arm/dts/k3-am62p5-r5-sk.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62P5 SK dts file for R5 SPL + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am62p5-sk.dts" +#include "k3-am62p5-sk-u-boot.dtsi" + +#include "k3-am62p-ddr-lp4-50-1600.dtsi" +#include "k3-am62a-ddr.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + serial0 = &wkup_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-all; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 20>, + <&secure_proxy_main 21>; + bootph-all; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&cbass_main { + sa3_secproxy: secproxy@44880000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>, + <0x00 0x43600000 0x00 0x10000>; + reg-names = "rt", "scfg", "target_data"; + bootph-all; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, + <&secure_proxy_main 0>, + <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-all; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + status = "okay"; +}; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + status = "okay"; +}; + +&main_pktdma { + ti,sci = <&dm_tifs>; +}; + +&main_bcdma { + ti,sci = <&dm_tifs>; +}; + +&ospi0 { + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x00 0x60000000 0x00 0x08000000>; +}; diff --git a/arch/arm/dts/k3-am62p5-sk-u-boot.dtsi b/arch/arm/dts/k3-am62p5-sk-u-boot.dtsi new file mode 100644 index 0000000000..ee91eb649b --- /dev/null +++ b/arch/arm/dts/k3-am62p5-sk-u-boot.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common AM62Px EVM dts file for SPLs + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am62p-sk-binman.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &main_timer0; + }; +}; + +&main_bcdma { + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>, + <0x00 0x48600000 0x00 0x8000>, + <0x00 0x484a4000 0x00 0x2000>, + <0x00 0x484c2000 0x00 0x2000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", + "ringrt", "cfg", "tchan", "rchan"; +}; + +&main_pktdma { + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>, + <0x00 0x485e0000 0x00 0x20000>, + <0x00 0x484a0000 0x00 0x4000>, + <0x00 0x484c0000 0x00 0x2000>, + <0x00 0x48430000 0x00 0x4000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", + "cfg", "tchan", "rchan", "rflow"; +}; + +&usbss0 { + bootph-pre-ram; +}; + +&usb0 { + /* Enable peripheral mode only during bootup + * to support DFU while allowing Linux to stay + * in OTG mode + */ + dr_mode = "peripheral"; + bootph-pre-ram; +}; + +&dmsc { + bootph-pre-ram; + k3_sysreset: sysreset-controller { + compatible = "ti,sci-sysreset"; + bootph-pre-ram; + }; +}; diff --git a/arch/arm/dts/k3-am62p5-sk.dts b/arch/arm/dts/k3-am62p5-sk.dts new file mode 100644 index 0000000000..cc9087fa3c --- /dev/null +++ b/arch/arm/dts/k3-am62p5-sk.dts @@ -0,0 +1,835 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5-SK + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://www.ti.com/lit/zip/sprr487 + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> +#include "k3-am62p5.dtsi" + +/ { + compatible = "ti,am62p5-sk", "ti,am62p5"; + model = "Texas Instruments AM62P5 SK"; + + aliases { + serial0 = &wkup_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + spi0 = &ospi0; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = &main_uart0; + }; + + memory@80000000 { + /* 8G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x24000000>; + linux,cma-default; + }; + + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b500000 0x00 0x00300000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x00100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0x00f00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x00100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_5v0: regulator-1 { + /* Output of TPS630702RNMR */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vdd_mmc1: regulator-2 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vddshv_sdio: regulator-3 { + compatible = "regulator-gpio"; + regulator-name = "vddshv_sdio"; + pinctrl-names = "default"; + pinctrl-0 = <&vddshv_sdio_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62-sk:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; + + opp-table { + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + tlv320_mclk: clk-0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12288000>; + }; + + codec_audio: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62x-SKEVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&tlv320_mclk>; + }; + }; + + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; +}; + +&main_gpio0 { + bootph-all; +}; + +&main_gpio1 { + bootph-all; +}; + +&main_pmx0 { + bootph-all; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */ + AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ + AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */ + >; + bootph-all; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */ + AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C22) UART0_RTSn.GPIO1_23 */ + >; + }; + + main_mcasp1_pins_default: main-mcasp1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ + AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */ + AM62PX_IOPAD(0x008c, PIN_OUTPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */ + AM62PX_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 */ + >; + }; + + main_mdio1_pins_default: main-mdio1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ + AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ + AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ + AM62PX_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H23) MMC1_DAT1 */ + AM62PX_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (H22) MMC1_DAT2 */ + AM62PX_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ + AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */ + >; + bootph-all; + }; + + main_mmc2_pins_default: main-mmc2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ + AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ + AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */ + AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ + AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */ + AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */ + AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */ + >; + bootph-all; + }; + + main_rgmii1_pins_default: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */ + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */ + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */ + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */ + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */ + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */ + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */ + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */ + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */ + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */ + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */ + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */ + >; + bootph-all; + }; + + main_rgmii2_pins_default: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */ + AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */ + AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */ + AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */ + AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */ + AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */ + AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */ + AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */ + AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */ + AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */ + AM62PX_IOPAD(0x0168, PIN_INPUT, 0) /* (D16) RGMII2_TXC */ + AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */ + >; + bootph-all; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + >; + bootph-all; + }; + + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3.UART1_CTSn */ + AM62PX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2.UART1_RTSn */ + AM62PX_IOPAD(0x01ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR.UART1_RXD */ + AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */ + >; + bootph-all; + }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ + >; + }; + + main_wlirq_pins_default: main-wlirq-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0128, PIN_INPUT, 7) /* (K25) MMC2_SDWP.GPIO0_72 */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */ + AM62PX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */ + AM62PX_IOPAD(0x000c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */ + AM62PX_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */ + AM62PX_IOPAD(0x0014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */ + AM62PX_IOPAD(0x0018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */ + AM62PX_IOPAD(0x001c, PIN_INPUT, 0) /* (N21) OSPI0_D4 */ + AM62PX_IOPAD(0x0020, PIN_INPUT, 0) /* (N22) OSPI0_D5 */ + AM62PX_IOPAD(0x0024, PIN_INPUT, 0) /* (P21) OSPI0_D6 */ + AM62PX_IOPAD(0x0028, PIN_INPUT, 0) /* (N20) OSPI0_D7 */ + AM62PX_IOPAD(0x0008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */ + >; + bootph-all; + }; + + usr_led_pins_default: usr-led-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0244, PIN_INPUT, 7) /* (D24) MMC1_SDWP.GPIO1_49 */ + >; + }; + + vddshv_sdio_pins_default: vddshvr-sdio-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x007c, PIN_INPUT, 7) /* (Y25) GPMC0_CLK.GPIO0_31 */ + >; + bootph-all; + }; + + wlan_en_pins_default: wlan-en-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0124, PIN_INPUT, 7) /* (J25) MMC2_SDCD.GPIO0_71 */ + >; + }; + + main_dpi_pins_default: main-dpi-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0100, PIN_OUTPUT, 0) /* (W20) VOUT0_VSYNC */ + AM62PX_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AC20) VOUT0_HSYNC */ + AM62PX_IOPAD(0x0104, PIN_OUTPUT, 0) /* (Y21) VOUT0_PCLK */ + AM62PX_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (W21) VOUT0_DE */ + AM62PX_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (AE24) VOUT0_DATA0 */ + AM62PX_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (W23) VOUT0_DATA1 */ + AM62PX_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA2 */ + AM62PX_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA3 */ + AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (AB23) VOUT0_DATA4 */ + AM62PX_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (AD23) VOUT0_DATA5 */ + AM62PX_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (AC23) VOUT0_DATA6 */ + AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AE23) VOUT0_DATA7 */ + AM62PX_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (AE22) VOUT0_DATA8 */ + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (AC22) VOUT0_DATA9 */ + AM62PX_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */ + AM62PX_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AE21) VOUT0_DATA11 */ + AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AD21) VOUT0_DATA12 */ + AM62PX_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AC21) VOUT0_DATA13 */ + AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA20) VOUT0_DATA14 */ + AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y20) VOUT0_DATA15 */ + AM62PX_IOPAD(0x005c, PIN_OUTPUT, 1) /* (AC25) GPMC0_AD8.VOUT0_DATA16 */ + AM62PX_IOPAD(0x0060, PIN_OUTPUT, 1) /* (AB25) GPMC0_AD9.VOUT0_DATA17 */ + AM62PX_IOPAD(0x0064, PIN_OUTPUT, 1) /* (AA25) GPMC0_AD10.VOUT0_DATA18 */ + AM62PX_IOPAD(0x0068, PIN_OUTPUT, 1) /* (W24) GPMC0_AD11.VOUT0_DATA19 */ + AM62PX_IOPAD(0x006c, PIN_OUTPUT, 1) /* (Y24) GPMC0_AD12.VOUT0_DATA20 */ + AM62PX_IOPAD(0x0070, PIN_OUTPUT, 1) /* (AD25) GPMC0_AD13.VOUT0_DATA21 */ + AM62PX_IOPAD(0x0074, PIN_OUTPUT, 1) /* (AB24) GPMC0_AD14.VOUT0_DATA22 */ + AM62PX_IOPAD(0x0078, PIN_OUTPUT, 1) /* (AC24) GPMC0_AD15.VOUT0_DATA23 */ + AM62PX_IOPAD(0x009c, PIN_OUTPUT, 1) /* (AD24) GPMC0_WAIT1.VOUT0_EXTPCLKIN */ + >; + }; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + typec_pd0: tps6598x@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; + }; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <100000>; + bootph-all; + + tlv320aic3106: audio-codec@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + ai3x-micbias-vg = <1>; /* 2.0V */ + }; + + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "OLDI_INT#", "x8_NAND_DETECT", + "UART1_FET_SEL", "MMC1_SD_EN", + "VPP_EN", "EXP_PS_3V3_EN", + "UART1_FET_BUF_EN", "EXP_HAT_DETECT", + "DSI_GPIO0", "DSI_GPIO1", + "OLDI_EDID", "BT_UART_WAKE_SOC_3V3", + "USB_TYPEA_OC_INDICATION", "CSI_GPIO0", + "CSI_GPIO1", "WLAN_ALERTn", + "HDMI_INTn", "TEST_GPIO2", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "DSI_EDID", + "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + bootph-all; + }; + + exp2: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BT_EN_SOC", "EXP_PS_5V0_EN", + "", "", + "", "", + "", "", + "WL_LT_EN", "", + "TP3", "TP6", + "TP4", "TP7", + "TP5", "TP8", + "SoC_I2C2_MCAN_SEL", "GPIO_HDMI_RSTn", + "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "GPIO_OLDI_RSTn", "GPIO_AUD_RSTn", + "GPIO_eMMC_RSTn", "SoC_WLAN_SDIO_RST"; + }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + + hdmi_tx_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * HDMI can be serviced with 3 potential VPs - + * (DSS0 VP1 / DSS1 VP0 / DSS1 VP1). + * For now, we will service it with DSS0 VP1. + */ + port@0 { + reg = <0>; + sii9022_in: endpoint { + remote-endpoint = <&dss0_dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&main_i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; +}; + +&sdhci0 { + status = "okay"; + ti,driver-strength-ohm = <50>; + disable-wp; + bootph-all; +}; + +&sdhci1 { + /* SD/MMC */ + status = "okay"; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vddshv_sdio>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + no-1-8-v; + bootph-all; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>, + <&main_rgmii2_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; +}; + +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usbss1 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + usb-role-switch; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; + +&mcasp1 { + status = "okay"; + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp1_pins_default>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&fss { + bootph-all; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + bootph-all; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + cdns,phy-mode; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x00 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + bootph-all; + }; + }; + }; +}; + +&mailbox0_cluster0 { + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; + bootph-all; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; + bootph-all; +}; + +&mcu_pmx0 { + bootph-all; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ + AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ + AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ + AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ + >; + bootph-all; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; + bootph-all; +}; + +&dss0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_dpi_pins_default>; +}; + +&dss0_ports { + /* DSS0-VP2: DPI/HDMI Output */ + port@1 { + reg = <1>; + dss0_dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; diff --git a/arch/arm/dts/k3-am62p5.dtsi b/arch/arm/dts/k3-am62p5.dtsi new file mode 100644 index 0000000000..a78b8d4217 --- /dev/null +++ b/arch/arm/dts/k3-am62p5.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5 SoC family (quad core) + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * TRM: https://www.ti.com/lit/pdf/spruj83 + */ + +/dts-v1/; + +#include "k3-am62p.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 135 0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 136 0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 137 0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&wkup_conf>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; +}; diff --git a/arch/arm/dts/k3-am62sip-r5-sk.dts b/arch/arm/dts/k3-am62sip-r5-sk.dts new file mode 100644 index 0000000000..c95d80852a --- /dev/null +++ b/arch/arm/dts/k3-am62sip-r5-sk.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62x SIP SKEVM dts file for R5 SPL + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am625-sk.dts" +#include "k3-am62x-sip-ddr-lp4-50-800.dtsi" +#include "k3-am62-ddr.dtsi" + +#include "k3-am625-sk-u-boot.dtsi" +#include "k3-am62x-r5-sk-common.dtsi" +#include "k3-am625-sk-binman.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + /* 512M RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x20000000>; + + bootph-pre-ram; + }; +}; diff --git a/arch/arm/dts/k3-am62x-r5-sk-common.dtsi b/arch/arm/dts/k3-am62x-r5-sk-common.dtsi index bd03777322..521b6b678c 100644 --- a/arch/arm/dts/k3-am62x-r5-sk-common.dtsi +++ b/arch/arm/dts/k3-am62x-r5-sk-common.dtsi @@ -17,13 +17,6 @@ tick-timer = &timer1; }; - memory@80000000 { - device_type = "memory"; - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - bootph-pre-ram; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -40,7 +33,8 @@ compatible = "ti,am654-rproc"; reg = <0x00 0x00a90000 0x00 0x10>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; clocks = <&k3_clks 61 0>; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; @@ -72,6 +66,68 @@ ti,secure-host; }; +&cbass_mcu { + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x4100000 0x0 0x1000>; + ti,esm-pins = <0>, <1>, <2>, <85>; + bootph-pre-ram; + }; +}; + +&cbass_main { + sa3_secproxy: secproxy@44880000 { + bootph-pre-ram; + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "rt", "scfg", "target_data"; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>, + <0x00 0x43600000 0x00 0x10000>; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-pre-ram; + }; + + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x420000 0x0 0x1000>; + ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; + bootph-pre-ram; + }; +}; + +&mcu_pmx0 { + bootph-pre-ram; + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */ + AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ + AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */ + AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ + >; + bootph-pre-ram; + }; +}; + +&main_pmx0 { + bootph-pre-ram; + + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ + >; + bootph-pre-ram; + }; +}; + &ospi0 { reg = <0x00 0x0fc40000 0x00 0x100>, <0x00 0x60000000 0x00 0x08000000>; diff --git a/arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi b/arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi new file mode 100644 index 0000000000..04c9a78fba --- /dev/null +++ b/arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi @@ -0,0 +1,2191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.03 + * Mon Nov 21 2022 09:04:01 GMT-0600 (Central Standard Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 800MHz + * Density (per channel): 4Gb + * Write DBI: Enable + * Number of Ranks: 1 +*/ + +#define DDRSS_PLL_FHS_CNT 3 +#define DDRSS_PLL_FREQUENCY_1 400000000 +#define DDRSS_PLL_FREQUENCY_2 400000000 + + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x00027100 +#define DDRSS_CTL_12_DATA 0x00186A00 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000640 +#define DDRSS_CTL_15_DATA 0x00027100 +#define DDRSS_CTL_16_DATA 0x00186A00 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000640 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00002020 +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x0000040C +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000081C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x0000081C +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x05000804 +#define DDRSS_CTL_45_DATA 0x00000700 +#define DDRSS_CTL_46_DATA 0x09090004 +#define DDRSS_CTL_47_DATA 0x00000303 +#define DDRSS_CTL_48_DATA 0x00320007 +#define DDRSS_CTL_49_DATA 0x09090023 +#define DDRSS_CTL_50_DATA 0x0000210F +#define DDRSS_CTL_51_DATA 0x00320007 +#define DDRSS_CTL_52_DATA 0x09090023 +#define DDRSS_CTL_53_DATA 0x0900210F +#define DDRSS_CTL_54_DATA 0x000A0A09 +#define DDRSS_CTL_55_DATA 0x040006DB +#define DDRSS_CTL_56_DATA 0x09092004 +#define DDRSS_CTL_57_DATA 0x00000C0A +#define DDRSS_CTL_58_DATA 0x06006DB0 +#define DDRSS_CTL_59_DATA 0x09092006 +#define DDRSS_CTL_60_DATA 0x00000C0A +#define DDRSS_CTL_61_DATA 0x06006DB0 +#define DDRSS_CTL_62_DATA 0x03042006 +#define DDRSS_CTL_63_DATA 0x04050002 +#define DDRSS_CTL_64_DATA 0x100F100F +#define DDRSS_CTL_65_DATA 0x01010008 +#define DDRSS_CTL_66_DATA 0x041F1F07 +#define DDRSS_CTL_67_DATA 0x03111103 +#define DDRSS_CTL_68_DATA 0x00001111 +#define DDRSS_CTL_69_DATA 0x00000101 +#define DDRSS_CTL_70_DATA 0x00000000 +#define DDRSS_CTL_71_DATA 0x01000000 +#define DDRSS_CTL_72_DATA 0x00090803 +#define DDRSS_CTL_73_DATA 0x000000BB +#define DDRSS_CTL_74_DATA 0x00000090 +#define DDRSS_CTL_75_DATA 0x00000C2B +#define DDRSS_CTL_76_DATA 0x00000090 +#define DDRSS_CTL_77_DATA 0x00000C2B +#define DDRSS_CTL_78_DATA 0x00000005 +#define DDRSS_CTL_79_DATA 0x00000005 +#define DDRSS_CTL_80_DATA 0x00000010 +#define DDRSS_CTL_81_DATA 0x00000048 +#define DDRSS_CTL_82_DATA 0x0000017E +#define DDRSS_CTL_83_DATA 0x00000048 +#define DDRSS_CTL_84_DATA 0x0000017E +#define DDRSS_CTL_85_DATA 0x03004000 +#define DDRSS_CTL_86_DATA 0x00001201 +#define DDRSS_CTL_87_DATA 0x00060005 +#define DDRSS_CTL_88_DATA 0x00000006 +#define DDRSS_CTL_89_DATA 0x00000000 +#define DDRSS_CTL_90_DATA 0x05121208 +#define DDRSS_CTL_91_DATA 0x05030A05 +#define DDRSS_CTL_92_DATA 0x05030C06 +#define DDRSS_CTL_93_DATA 0x01030C06 +#define DDRSS_CTL_94_DATA 0x02010201 +#define DDRSS_CTL_95_DATA 0x00000A01 +#define DDRSS_CTL_96_DATA 0x0096000A +#define DDRSS_CTL_97_DATA 0x00960096 +#define DDRSS_CTL_98_DATA 0x00000096 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x05010303 +#define DDRSS_CTL_101_DATA 0x0C040505 +#define DDRSS_CTL_102_DATA 0x06050203 +#define DDRSS_CTL_103_DATA 0x030C0605 +#define DDRSS_CTL_104_DATA 0x05060502 +#define DDRSS_CTL_105_DATA 0x03030306 +#define DDRSS_CTL_106_DATA 0x03010000 +#define DDRSS_CTL_107_DATA 0x00010000 +#define DDRSS_CTL_108_DATA 0x00000000 +#define DDRSS_CTL_109_DATA 0x01000000 +#define DDRSS_CTL_110_DATA 0x80104002 +#define DDRSS_CTL_111_DATA 0x00040003 +#define DDRSS_CTL_112_DATA 0x00040005 +#define DDRSS_CTL_113_DATA 0x00030000 +#define DDRSS_CTL_114_DATA 0x00050004 +#define DDRSS_CTL_115_DATA 0x00000004 +#define DDRSS_CTL_116_DATA 0x00040003 +#define DDRSS_CTL_117_DATA 0x00040005 +#define DDRSS_CTL_118_DATA 0x00000000 +#define DDRSS_CTL_119_DATA 0x00002EC0 +#define DDRSS_CTL_120_DATA 0x00002EC0 +#define DDRSS_CTL_121_DATA 0x00002EC0 +#define DDRSS_CTL_122_DATA 0x00002EC0 +#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000051D +#define DDRSS_CTL_126_DATA 0x00030AC0 +#define DDRSS_CTL_127_DATA 0x00030AC0 +#define DDRSS_CTL_128_DATA 0x00030AC0 +#define DDRSS_CTL_129_DATA 0x00030AC0 +#define DDRSS_CTL_130_DATA 0x00030AC0 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000552D +#define DDRSS_CTL_133_DATA 0x00030AC0 +#define DDRSS_CTL_134_DATA 0x00030AC0 +#define DDRSS_CTL_135_DATA 0x00030AC0 +#define DDRSS_CTL_136_DATA 0x00030AC0 +#define DDRSS_CTL_137_DATA 0x00030AC0 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000552D +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x03050000 +#define DDRSS_CTL_157_DATA 0x03050305 +#define DDRSS_CTL_158_DATA 0x00000000 +#define DDRSS_CTL_159_DATA 0x08010000 +#define DDRSS_CTL_160_DATA 0x000E0808 +#define DDRSS_CTL_161_DATA 0x01000000 +#define DDRSS_CTL_162_DATA 0x0E080808 +#define DDRSS_CTL_163_DATA 0x00000000 +#define DDRSS_CTL_164_DATA 0x08080801 +#define DDRSS_CTL_165_DATA 0x0000080E +#define DDRSS_CTL_166_DATA 0x00040003 +#define DDRSS_CTL_167_DATA 0x00000007 +#define DDRSS_CTL_168_DATA 0x00000000 +#define DDRSS_CTL_169_DATA 0x00000000 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x01000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x00001500 +#define DDRSS_CTL_177_DATA 0x0000100E +#define DDRSS_CTL_178_DATA 0x00000002 +#define DDRSS_CTL_179_DATA 0x00000000 +#define DDRSS_CTL_180_DATA 0x00000001 +#define DDRSS_CTL_181_DATA 0x00000002 +#define DDRSS_CTL_182_DATA 0x00000C00 +#define DDRSS_CTL_183_DATA 0x00001000 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00001000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00001000 +#define DDRSS_CTL_188_DATA 0x00000000 +#define DDRSS_CTL_189_DATA 0x00000000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x0005000A +#define DDRSS_CTL_193_DATA 0x0404000D +#define DDRSS_CTL_194_DATA 0x0000000D +#define DDRSS_CTL_195_DATA 0x005000A0 +#define DDRSS_CTL_196_DATA 0x060600C8 +#define DDRSS_CTL_197_DATA 0x000000C8 +#define DDRSS_CTL_198_DATA 0x005000A0 +#define DDRSS_CTL_199_DATA 0x060600C8 +#define DDRSS_CTL_200_DATA 0x000000C8 +#define DDRSS_CTL_201_DATA 0x00000000 +#define DDRSS_CTL_202_DATA 0x00000000 +#define DDRSS_CTL_203_DATA 0x00000000 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000004 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000024 +#define DDRSS_CTL_209_DATA 0x00000012 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000024 +#define DDRSS_CTL_212_DATA 0x00000012 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000004 +#define DDRSS_CTL_215_DATA 0x00000000 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000024 +#define DDRSS_CTL_218_DATA 0x00000012 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000024 +#define DDRSS_CTL_221_DATA 0x00000012 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000000 +#define DDRSS_CTL_224_DATA 0x00000031 +#define DDRSS_CTL_225_DATA 0x000000B1 +#define DDRSS_CTL_226_DATA 0x000000B1 +#define DDRSS_CTL_227_DATA 0x00000031 +#define DDRSS_CTL_228_DATA 0x000000B1 +#define DDRSS_CTL_229_DATA 0x000000B1 +#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_231_DATA 0x00000000 +#define DDRSS_CTL_232_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x65006565 +#define DDRSS_CTL_255_DATA 0x00002765 +#define DDRSS_CTL_256_DATA 0x00000027 +#define DDRSS_CTL_257_DATA 0x00000027 +#define DDRSS_CTL_258_DATA 0x00000027 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000000 +#define DDRSS_CTL_262_DATA 0x00000000 +#define DDRSS_CTL_263_DATA 0x0000000F +#define DDRSS_CTL_264_DATA 0x0000000F +#define DDRSS_CTL_265_DATA 0x0000000F +#define DDRSS_CTL_266_DATA 0x0000000F +#define DDRSS_CTL_267_DATA 0x0000000F +#define DDRSS_CTL_268_DATA 0x0000000F +#define DDRSS_CTL_269_DATA 0x00000000 +#define DDRSS_CTL_270_DATA 0x00001000 +#define DDRSS_CTL_271_DATA 0x00000015 +#define DDRSS_CTL_272_DATA 0x00000015 +#define DDRSS_CTL_273_DATA 0x00000010 +#define DDRSS_CTL_274_DATA 0x00000015 +#define DDRSS_CTL_275_DATA 0x00000015 +#define DDRSS_CTL_276_DATA 0x00000020 +#define DDRSS_CTL_277_DATA 0x00010000 +#define DDRSS_CTL_278_DATA 0x00000100 +#define DDRSS_CTL_279_DATA 0x00000000 +#define DDRSS_CTL_280_DATA 0x00000000 +#define DDRSS_CTL_281_DATA 0x00000101 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000000 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x0C181511 +#define DDRSS_CTL_291_DATA 0x00000304 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0x00000000 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00020000 +#define DDRSS_CTL_306_DATA 0x00400100 +#define DDRSS_CTL_307_DATA 0x00080032 +#define DDRSS_CTL_308_DATA 0x01000200 +#define DDRSS_CTL_309_DATA 0x03200040 +#define DDRSS_CTL_310_DATA 0x00020018 +#define DDRSS_CTL_311_DATA 0x00400100 +#define DDRSS_CTL_312_DATA 0x00180320 +#define DDRSS_CTL_313_DATA 0x00030000 +#define DDRSS_CTL_314_DATA 0x00280028 +#define DDRSS_CTL_315_DATA 0x00000100 +#define DDRSS_CTL_316_DATA 0x01010000 +#define DDRSS_CTL_317_DATA 0x00000202 +#define DDRSS_CTL_318_DATA 0x0FFF0000 +#define DDRSS_CTL_319_DATA 0x000FFF00 +#define DDRSS_CTL_320_DATA 0xFFFFFFFF +#define DDRSS_CTL_321_DATA 0x00FFFF00 +#define DDRSS_CTL_322_DATA 0x0B000000 +#define DDRSS_CTL_323_DATA 0x0001FFFF +#define DDRSS_CTL_324_DATA 0x01010101 +#define DDRSS_CTL_325_DATA 0x01010101 +#define DDRSS_CTL_326_DATA 0x00000118 +#define DDRSS_CTL_327_DATA 0x00000C01 +#define DDRSS_CTL_328_DATA 0x01000100 +#define DDRSS_CTL_329_DATA 0x00000000 +#define DDRSS_CTL_330_DATA 0x00000000 +#define DDRSS_CTL_331_DATA 0x01030303 +#define DDRSS_CTL_332_DATA 0x00000001 +#define DDRSS_CTL_333_DATA 0x00000000 +#define DDRSS_CTL_334_DATA 0x00000000 +#define DDRSS_CTL_335_DATA 0x00000000 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x00000000 +#define DDRSS_CTL_339_DATA 0x00000000 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x01000101 +#define DDRSS_CTL_372_DATA 0x01010001 +#define DDRSS_CTL_373_DATA 0x00010101 +#define DDRSS_CTL_374_DATA 0x01050503 +#define DDRSS_CTL_375_DATA 0x05020201 +#define DDRSS_CTL_376_DATA 0x08080C0C +#define DDRSS_CTL_377_DATA 0x00080308 +#define DDRSS_CTL_378_DATA 0x000B030E +#define DDRSS_CTL_379_DATA 0x000B0310 +#define DDRSS_CTL_380_DATA 0x0B0B0810 +#define DDRSS_CTL_381_DATA 0x01000000 +#define DDRSS_CTL_382_DATA 0x03020301 +#define DDRSS_CTL_383_DATA 0x04000102 +#define DDRSS_CTL_384_DATA 0x1B000004 +#define DDRSS_CTL_385_DATA 0x00000176 +#define DDRSS_CTL_386_DATA 0x00000200 +#define DDRSS_CTL_387_DATA 0x00000200 +#define DDRSS_CTL_388_DATA 0x00000200 +#define DDRSS_CTL_389_DATA 0x00000200 +#define DDRSS_CTL_390_DATA 0x00000693 +#define DDRSS_CTL_391_DATA 0x00000E9C +#define DDRSS_CTL_392_DATA 0x03050202 +#define DDRSS_CTL_393_DATA 0x00250201 +#define DDRSS_CTL_394_DATA 0x00001856 +#define DDRSS_CTL_395_DATA 0x00000200 +#define DDRSS_CTL_396_DATA 0x00000200 +#define DDRSS_CTL_397_DATA 0x00000200 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00006D83 +#define DDRSS_CTL_400_DATA 0x0000F35C +#define DDRSS_CTL_401_DATA 0x070D0402 +#define DDRSS_CTL_402_DATA 0x00250405 +#define DDRSS_CTL_403_DATA 0x00001856 +#define DDRSS_CTL_404_DATA 0x00000200 +#define DDRSS_CTL_405_DATA 0x00000200 +#define DDRSS_CTL_406_DATA 0x00000200 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00006D83 +#define DDRSS_CTL_409_DATA 0x0000F35C +#define DDRSS_CTL_410_DATA 0x070D0402 +#define DDRSS_CTL_411_DATA 0x00000405 +#define DDRSS_CTL_412_DATA 0x00000000 +#define DDRSS_CTL_413_DATA 0x0302000A +#define DDRSS_CTL_414_DATA 0x01000500 +#define DDRSS_CTL_415_DATA 0x01010001 +#define DDRSS_CTL_416_DATA 0x00010001 +#define DDRSS_CTL_417_DATA 0x01010001 +#define DDRSS_CTL_418_DATA 0x02010000 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x02000201 +#define DDRSS_CTL_421_DATA 0x10100600 +#define DDRSS_CTL_422_DATA 0x00202020 +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x00010001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00010000 +#define DDRSS_PI_24_DATA 0x280A0001 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x00010000 +#define DDRSS_PI_27_DATA 0x00003200 +#define DDRSS_PI_28_DATA 0x00000000 +#define DDRSS_PI_29_DATA 0x00000000 +#define DDRSS_PI_30_DATA 0x01010102 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x00000000 +#define DDRSS_PI_34_DATA 0x00000001 +#define DDRSS_PI_35_DATA 0x000000AA +#define DDRSS_PI_36_DATA 0x00000055 +#define DDRSS_PI_37_DATA 0x000000B5 +#define DDRSS_PI_38_DATA 0x0000004A +#define DDRSS_PI_39_DATA 0x00000056 +#define DDRSS_PI_40_DATA 0x000000A9 +#define DDRSS_PI_41_DATA 0x000000A9 +#define DDRSS_PI_42_DATA 0x000000B5 +#define DDRSS_PI_43_DATA 0x00000000 +#define DDRSS_PI_44_DATA 0x00000000 +#define DDRSS_PI_45_DATA 0x00010100 +#define DDRSS_PI_46_DATA 0x00000015 +#define DDRSS_PI_47_DATA 0x000007D0 +#define DDRSS_PI_48_DATA 0x00000300 +#define DDRSS_PI_49_DATA 0x00000000 +#define DDRSS_PI_50_DATA 0x00000000 +#define DDRSS_PI_51_DATA 0x01000000 +#define DDRSS_PI_52_DATA 0x00010101 +#define DDRSS_PI_53_DATA 0x01000000 +#define DDRSS_PI_54_DATA 0x03000000 +#define DDRSS_PI_55_DATA 0x00000000 +#define DDRSS_PI_56_DATA 0x00001701 +#define DDRSS_PI_57_DATA 0x00000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00000000 +#define DDRSS_PI_60_DATA 0x0A0A140A +#define DDRSS_PI_61_DATA 0x10020101 +#define DDRSS_PI_62_DATA 0x01000210 +#define DDRSS_PI_63_DATA 0x05000404 +#define DDRSS_PI_64_DATA 0x00010001 +#define DDRSS_PI_65_DATA 0x0001000E +#define DDRSS_PI_66_DATA 0x01010100 +#define DDRSS_PI_67_DATA 0x00010000 +#define DDRSS_PI_68_DATA 0x00000034 +#define DDRSS_PI_69_DATA 0x00000000 +#define DDRSS_PI_70_DATA 0x00000000 +#define DDRSS_PI_71_DATA 0x0000FFFF +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x00000000 +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x01000000 +#define DDRSS_PI_77_DATA 0x08020100 +#define DDRSS_PI_78_DATA 0x00020000 +#define DDRSS_PI_79_DATA 0x00010002 +#define DDRSS_PI_80_DATA 0x00000001 +#define DDRSS_PI_81_DATA 0x00020001 +#define DDRSS_PI_82_DATA 0x00020002 +#define DDRSS_PI_83_DATA 0x00000000 +#define DDRSS_PI_84_DATA 0x00000000 +#define DDRSS_PI_85_DATA 0x00000000 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000400 +#define DDRSS_PI_92_DATA 0x0A090B0C +#define DDRSS_PI_93_DATA 0x04060708 +#define DDRSS_PI_94_DATA 0x01000005 +#define DDRSS_PI_95_DATA 0x00000800 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00010008 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x0000AA00 +#define DDRSS_PI_100_DATA 0x00000000 +#define DDRSS_PI_101_DATA 0x00010000 +#define DDRSS_PI_102_DATA 0x00000000 +#define DDRSS_PI_103_DATA 0x00000000 +#define DDRSS_PI_104_DATA 0x00000000 +#define DDRSS_PI_105_DATA 0x00000000 +#define DDRSS_PI_106_DATA 0x00000000 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x00000000 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00000000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000008 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00010000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x0000000A +#define DDRSS_PI_137_DATA 0x000186A0 +#define DDRSS_PI_138_DATA 0x00000100 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x01000000 +#define DDRSS_PI_145_DATA 0x00010003 +#define DDRSS_PI_146_DATA 0x02000101 +#define DDRSS_PI_147_DATA 0x01030001 +#define DDRSS_PI_148_DATA 0x00010400 +#define DDRSS_PI_149_DATA 0x06000105 +#define DDRSS_PI_150_DATA 0x01070001 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00010001 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x00000000 +#define DDRSS_PI_157_DATA 0x00000000 +#define DDRSS_PI_158_DATA 0x00000000 +#define DDRSS_PI_159_DATA 0x00010000 +#define DDRSS_PI_160_DATA 0x00000004 +#define DDRSS_PI_161_DATA 0x00000000 +#define DDRSS_PI_162_DATA 0x00000000 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000800 +#define DDRSS_PI_165_DATA 0x00780078 +#define DDRSS_PI_166_DATA 0x00101001 +#define DDRSS_PI_167_DATA 0x00000034 +#define DDRSS_PI_168_DATA 0x00000042 +#define DDRSS_PI_169_DATA 0x00020042 +#define DDRSS_PI_170_DATA 0x02000200 +#define DDRSS_PI_171_DATA 0x00000004 +#define DDRSS_PI_172_DATA 0x0000080C +#define DDRSS_PI_173_DATA 0x00081C00 +#define DDRSS_PI_174_DATA 0x001C0000 +#define DDRSS_PI_175_DATA 0x00000009 +#define DDRSS_PI_176_DATA 0x000000BB +#define DDRSS_PI_177_DATA 0x00000090 +#define DDRSS_PI_178_DATA 0x00000C2B +#define DDRSS_PI_179_DATA 0x00000090 +#define DDRSS_PI_180_DATA 0x04000C2B +#define DDRSS_PI_181_DATA 0x01010404 +#define DDRSS_PI_182_DATA 0x00001501 +#define DDRSS_PI_183_DATA 0x001D001D +#define DDRSS_PI_184_DATA 0x01000100 +#define DDRSS_PI_185_DATA 0x00000100 +#define DDRSS_PI_186_DATA 0x00000000 +#define DDRSS_PI_187_DATA 0x05050503 +#define DDRSS_PI_188_DATA 0x01010C0C +#define DDRSS_PI_189_DATA 0x01010101 +#define DDRSS_PI_190_DATA 0x000C0C0A +#define DDRSS_PI_191_DATA 0x00000000 +#define DDRSS_PI_192_DATA 0x00000000 +#define DDRSS_PI_193_DATA 0x04000000 +#define DDRSS_PI_194_DATA 0x04020808 +#define DDRSS_PI_195_DATA 0x04040204 +#define DDRSS_PI_196_DATA 0x00090031 +#define DDRSS_PI_197_DATA 0x00110039 +#define DDRSS_PI_198_DATA 0x00110039 +#define DDRSS_PI_199_DATA 0x01010101 +#define DDRSS_PI_200_DATA 0x0002000D +#define DDRSS_PI_201_DATA 0x000200C8 +#define DDRSS_PI_202_DATA 0x010000C8 +#define DDRSS_PI_203_DATA 0x000E000E +#define DDRSS_PI_204_DATA 0x00C90100 +#define DDRSS_PI_205_DATA 0x010000C9 +#define DDRSS_PI_206_DATA 0x00C900C9 +#define DDRSS_PI_207_DATA 0x32103200 +#define DDRSS_PI_208_DATA 0x01013210 +#define DDRSS_PI_209_DATA 0x0A070601 +#define DDRSS_PI_210_DATA 0x0D09070D +#define DDRSS_PI_211_DATA 0x0D09070D +#define DDRSS_PI_212_DATA 0x000C000D +#define DDRSS_PI_213_DATA 0x00001000 +#define DDRSS_PI_214_DATA 0x00000C00 +#define DDRSS_PI_215_DATA 0x00001000 +#define DDRSS_PI_216_DATA 0x00000C00 +#define DDRSS_PI_217_DATA 0x02001000 +#define DDRSS_PI_218_DATA 0x0016000D +#define DDRSS_PI_219_DATA 0x001600C8 +#define DDRSS_PI_220_DATA 0x000000C8 +#define DDRSS_PI_221_DATA 0x00001900 +#define DDRSS_PI_222_DATA 0x32000056 +#define DDRSS_PI_223_DATA 0x06000101 +#define DDRSS_PI_224_DATA 0x001D0204 +#define DDRSS_PI_225_DATA 0x32120058 +#define DDRSS_PI_226_DATA 0x05000101 +#define DDRSS_PI_227_DATA 0x001D0408 +#define DDRSS_PI_228_DATA 0x32120058 +#define DDRSS_PI_229_DATA 0x05000101 +#define DDRSS_PI_230_DATA 0x00000408 +#define DDRSS_PI_231_DATA 0x05030900 +#define DDRSS_PI_232_DATA 0x00040900 +#define DDRSS_PI_233_DATA 0x0000062B +#define DDRSS_PI_234_DATA 0x20010004 +#define DDRSS_PI_235_DATA 0x0A0A0A03 +#define DDRSS_PI_236_DATA 0x11090000 +#define DDRSS_PI_237_DATA 0x1009000F +#define DDRSS_PI_238_DATA 0x000062B8 +#define DDRSS_PI_239_DATA 0x20030023 +#define DDRSS_PI_240_DATA 0x0C0A0C0C +#define DDRSS_PI_241_DATA 0x11090000 +#define DDRSS_PI_242_DATA 0x1009000F +#define DDRSS_PI_243_DATA 0x000062B8 +#define DDRSS_PI_244_DATA 0x20030023 +#define DDRSS_PI_245_DATA 0x0C0A0C0C +#define DDRSS_PI_246_DATA 0x00000000 +#define DDRSS_PI_247_DATA 0x00000176 +#define DDRSS_PI_248_DATA 0x00000E9C +#define DDRSS_PI_249_DATA 0x00001856 +#define DDRSS_PI_250_DATA 0x0000F35C +#define DDRSS_PI_251_DATA 0x00001856 +#define DDRSS_PI_252_DATA 0x0000F35C +#define DDRSS_PI_253_DATA 0x0096000A +#define DDRSS_PI_254_DATA 0x03030096 +#define DDRSS_PI_255_DATA 0x00000003 +#define DDRSS_PI_256_DATA 0x00000000 +#define DDRSS_PI_257_DATA 0x05030503 +#define DDRSS_PI_258_DATA 0x00000503 +#define DDRSS_PI_259_DATA 0x00002710 +#define DDRSS_PI_260_DATA 0x000186A0 +#define DDRSS_PI_261_DATA 0x00000005 +#define DDRSS_PI_262_DATA 0x00000064 +#define DDRSS_PI_263_DATA 0x0000000A +#define DDRSS_PI_264_DATA 0x00027100 +#define DDRSS_PI_265_DATA 0x000186A0 +#define DDRSS_PI_266_DATA 0x00000005 +#define DDRSS_PI_267_DATA 0x00000640 +#define DDRSS_PI_268_DATA 0x00000096 +#define DDRSS_PI_269_DATA 0x00027100 +#define DDRSS_PI_270_DATA 0x000186A0 +#define DDRSS_PI_271_DATA 0x00000005 +#define DDRSS_PI_272_DATA 0x00000640 +#define DDRSS_PI_273_DATA 0x01000096 +#define DDRSS_PI_274_DATA 0x00320040 +#define DDRSS_PI_275_DATA 0x00010008 +#define DDRSS_PI_276_DATA 0x03200040 +#define DDRSS_PI_277_DATA 0x00010018 +#define DDRSS_PI_278_DATA 0x03200040 +#define DDRSS_PI_279_DATA 0x00000318 +#define DDRSS_PI_280_DATA 0x00280028 +#define DDRSS_PI_281_DATA 0x03040404 +#define DDRSS_PI_282_DATA 0x00000303 +#define DDRSS_PI_283_DATA 0x02020101 +#define DDRSS_PI_284_DATA 0x67676767 +#define DDRSS_PI_285_DATA 0x00000000 +#define DDRSS_PI_286_DATA 0x55000000 +#define DDRSS_PI_287_DATA 0x00000000 +#define DDRSS_PI_288_DATA 0x3C00005A +#define DDRSS_PI_289_DATA 0x00005500 +#define DDRSS_PI_290_DATA 0x00005A00 +#define DDRSS_PI_291_DATA 0x0D100F3C +#define DDRSS_PI_292_DATA 0x0003020E +#define DDRSS_PI_293_DATA 0x00000001 +#define DDRSS_PI_294_DATA 0x01000000 +#define DDRSS_PI_295_DATA 0x00020201 +#define DDRSS_PI_296_DATA 0x00000000 +#define DDRSS_PI_297_DATA 0x00000000 +#define DDRSS_PI_298_DATA 0x00000004 +#define DDRSS_PI_299_DATA 0x00000000 +#define DDRSS_PI_300_DATA 0x00000031 +#define DDRSS_PI_301_DATA 0x00000000 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00100F27 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x00000024 +#define DDRSS_PI_307_DATA 0x00000012 +#define DDRSS_PI_308_DATA 0x000000B1 +#define DDRSS_PI_309_DATA 0x00000000 +#define DDRSS_PI_310_DATA 0x00000000 +#define DDRSS_PI_311_DATA 0x65000000 +#define DDRSS_PI_312_DATA 0x00150F27 +#define DDRSS_PI_313_DATA 0x00000000 +#define DDRSS_PI_314_DATA 0x00000024 +#define DDRSS_PI_315_DATA 0x00000012 +#define DDRSS_PI_316_DATA 0x000000B1 +#define DDRSS_PI_317_DATA 0x00000000 +#define DDRSS_PI_318_DATA 0x00000000 +#define DDRSS_PI_319_DATA 0x65000000 +#define DDRSS_PI_320_DATA 0x00150F27 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000004 +#define DDRSS_PI_323_DATA 0x00000000 +#define DDRSS_PI_324_DATA 0x00000031 +#define DDRSS_PI_325_DATA 0x00000000 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00100F27 +#define DDRSS_PI_329_DATA 0x00000000 +#define DDRSS_PI_330_DATA 0x00000024 +#define DDRSS_PI_331_DATA 0x00000012 +#define DDRSS_PI_332_DATA 0x000000B1 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00000000 +#define DDRSS_PI_335_DATA 0x65000000 +#define DDRSS_PI_336_DATA 0x00150F27 +#define DDRSS_PI_337_DATA 0x00000000 +#define DDRSS_PI_338_DATA 0x00000024 +#define DDRSS_PI_339_DATA 0x00000012 +#define DDRSS_PI_340_DATA 0x000000B1 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x00000000 +#define DDRSS_PI_343_DATA 0x65000000 +#define DDRSS_PI_344_DATA 0x00150F27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01000000 +#define DDRSS_PHY_6_DATA 0x03000400 +#define DDRSS_PHY_7_DATA 0x00000001 +#define DDRSS_PHY_8_DATA 0x00000001 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x01010000 +#define DDRSS_PHY_12_DATA 0x00010000 +#define DDRSS_PHY_13_DATA 0x00C00001 +#define DDRSS_PHY_14_DATA 0x00CC0008 +#define DDRSS_PHY_15_DATA 0x00660601 +#define DDRSS_PHY_16_DATA 0x00000003 +#define DDRSS_PHY_17_DATA 0x00000000 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x0000AAAA +#define DDRSS_PHY_20_DATA 0x00005555 +#define DDRSS_PHY_21_DATA 0x0000B5B5 +#define DDRSS_PHY_22_DATA 0x00004A4A +#define DDRSS_PHY_23_DATA 0x00005656 +#define DDRSS_PHY_24_DATA 0x0000A9A9 +#define DDRSS_PHY_25_DATA 0x0000B7B7 +#define DDRSS_PHY_26_DATA 0x00004848 +#define DDRSS_PHY_27_DATA 0x00000000 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x08000000 +#define DDRSS_PHY_30_DATA 0x0F000008 +#define DDRSS_PHY_31_DATA 0x00000F0F +#define DDRSS_PHY_32_DATA 0x00E4E400 +#define DDRSS_PHY_33_DATA 0x00071020 +#define DDRSS_PHY_34_DATA 0x000C0020 +#define DDRSS_PHY_35_DATA 0x00062000 +#define DDRSS_PHY_36_DATA 0x00000000 +#define DDRSS_PHY_37_DATA 0x55555555 +#define DDRSS_PHY_38_DATA 0xAAAAAAAA +#define DDRSS_PHY_39_DATA 0x55555555 +#define DDRSS_PHY_40_DATA 0xAAAAAAAA +#define DDRSS_PHY_41_DATA 0x00005555 +#define DDRSS_PHY_42_DATA 0x01000100 +#define DDRSS_PHY_43_DATA 0x00800180 +#define DDRSS_PHY_44_DATA 0x00000000 // [SWAP] PHY_CALVL_VREF_DRIVING_SLICE_0 //0x00000001 Normal +#define DDRSS_PHY_45_DATA 0x00000000 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000004 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000000 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x041F07FF +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x01CC0B01 +#define DDRSS_PHY_75_DATA 0x1003CC0B +#define DDRSS_PHY_76_DATA 0x20000140 +#define DDRSS_PHY_77_DATA 0x07FF0200 +#define DDRSS_PHY_78_DATA 0x0000DD01 +#define DDRSS_PHY_79_DATA 0x00100303 +#define DDRSS_PHY_80_DATA 0x00000000 +#define DDRSS_PHY_81_DATA 0x00000000 +#define DDRSS_PHY_82_DATA 0x00021000 +#define DDRSS_PHY_83_DATA 0x00100010 +#define DDRSS_PHY_84_DATA 0x00100010 +#define DDRSS_PHY_85_DATA 0x00100010 +#define DDRSS_PHY_86_DATA 0x00100010 +#define DDRSS_PHY_87_DATA 0x02020010 +#define DDRSS_PHY_88_DATA 0x51516041 +#define DDRSS_PHY_89_DATA 0x31C06000 +#define DDRSS_PHY_90_DATA 0x07AB0340 +#define DDRSS_PHY_91_DATA 0x0000C0C0 +#define DDRSS_PHY_92_DATA 0x04050000 +#define DDRSS_PHY_93_DATA 0x00000504 +#define DDRSS_PHY_94_DATA 0x42100010 +#define DDRSS_PHY_95_DATA 0x010C053E +#define DDRSS_PHY_96_DATA 0x000F0C1D +#define DDRSS_PHY_97_DATA 0x01000140 +#define DDRSS_PHY_98_DATA 0x007A0120 +#define DDRSS_PHY_99_DATA 0x00000C00 +#define DDRSS_PHY_100_DATA 0x000001CC +#define DDRSS_PHY_101_DATA 0x20100200 +#define DDRSS_PHY_102_DATA 0x00000005 +#define DDRSS_PHY_103_DATA 0x56743210 // [SWIZZLE] PHY_DQ_DM_SWIZZLE0_0 //0x76543210 Swizzle DV +#define DDRSS_PHY_104_DATA 0x00000008 +#define DDRSS_PHY_105_DATA 0x034C034C +#define DDRSS_PHY_106_DATA 0x034C034C +#define DDRSS_PHY_107_DATA 0x034C034C +#define DDRSS_PHY_108_DATA 0x034C034C +#define DDRSS_PHY_109_DATA 0x0000034C +#define DDRSS_PHY_110_DATA 0x00008000 +#define DDRSS_PHY_111_DATA 0x00800080 +#define DDRSS_PHY_112_DATA 0x00800080 +#define DDRSS_PHY_113_DATA 0x00800080 +#define DDRSS_PHY_114_DATA 0x00800080 +#define DDRSS_PHY_115_DATA 0x00800080 +#define DDRSS_PHY_116_DATA 0x00800080 +#define DDRSS_PHY_117_DATA 0x00800080 +#define DDRSS_PHY_118_DATA 0x00800080 +#define DDRSS_PHY_119_DATA 0x01800080 +#define DDRSS_PHY_120_DATA 0x01000000 +#define DDRSS_PHY_121_DATA 0x00000000 +#define DDRSS_PHY_122_DATA 0x00000000 +#define DDRSS_PHY_123_DATA 0x00080200 +#define DDRSS_PHY_124_DATA 0x00000000 +#define DDRSS_PHY_125_DATA 0x0000F0F0 +#define DDRSS_PHY_126_DATA 0x00000000 +#define DDRSS_PHY_127_DATA 0x00000000 +#define DDRSS_PHY_128_DATA 0x00000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00000000 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x00000000 +#define DDRSS_PHY_134_DATA 0x00000000 +#define DDRSS_PHY_135_DATA 0x00000000 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01000000 +#define DDRSS_PHY_262_DATA 0x03000400 +#define DDRSS_PHY_263_DATA 0x00000001 +#define DDRSS_PHY_264_DATA 0x00000001 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x01010000 +#define DDRSS_PHY_268_DATA 0x00010000 +#define DDRSS_PHY_269_DATA 0x00C00001 +#define DDRSS_PHY_270_DATA 0x00CC0008 +#define DDRSS_PHY_271_DATA 0x00660601 +#define DDRSS_PHY_272_DATA 0x00000003 +#define DDRSS_PHY_273_DATA 0x00000000 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x0000AAAA +#define DDRSS_PHY_276_DATA 0x00005555 +#define DDRSS_PHY_277_DATA 0x0000B5B5 +#define DDRSS_PHY_278_DATA 0x00004A4A +#define DDRSS_PHY_279_DATA 0x00005656 +#define DDRSS_PHY_280_DATA 0x0000A9A9 +#define DDRSS_PHY_281_DATA 0x0000B7B7 +#define DDRSS_PHY_282_DATA 0x00004848 +#define DDRSS_PHY_283_DATA 0x00000000 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x08000000 +#define DDRSS_PHY_286_DATA 0x0F000008 +#define DDRSS_PHY_287_DATA 0x00000F0F +#define DDRSS_PHY_288_DATA 0x00E4E400 +#define DDRSS_PHY_289_DATA 0x00071020 +#define DDRSS_PHY_290_DATA 0x000C0020 +#define DDRSS_PHY_291_DATA 0x00062000 +#define DDRSS_PHY_292_DATA 0x00000000 +#define DDRSS_PHY_293_DATA 0x55555555 +#define DDRSS_PHY_294_DATA 0xAAAAAAAA +#define DDRSS_PHY_295_DATA 0x55555555 +#define DDRSS_PHY_296_DATA 0xAAAAAAAA +#define DDRSS_PHY_297_DATA 0x00005555 +#define DDRSS_PHY_298_DATA 0x01000100 +#define DDRSS_PHY_299_DATA 0x00800180 +#define DDRSS_PHY_300_DATA 0x00000001 // [SWAP] PHY_CALVL_VREF_DRIVING_SLICE_1 //0x00000000 Normal +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000004 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000000 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x041F07FF +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x01CC0B01 +#define DDRSS_PHY_331_DATA 0x1003CC0B +#define DDRSS_PHY_332_DATA 0x20000140 +#define DDRSS_PHY_333_DATA 0x07FF0200 +#define DDRSS_PHY_334_DATA 0x0000DD01 +#define DDRSS_PHY_335_DATA 0x00100303 +#define DDRSS_PHY_336_DATA 0x00000000 +#define DDRSS_PHY_337_DATA 0x00000000 +#define DDRSS_PHY_338_DATA 0x00021000 +#define DDRSS_PHY_339_DATA 0x00100010 +#define DDRSS_PHY_340_DATA 0x00100010 +#define DDRSS_PHY_341_DATA 0x00100010 +#define DDRSS_PHY_342_DATA 0x00100010 +#define DDRSS_PHY_343_DATA 0x02020010 +#define DDRSS_PHY_344_DATA 0x51516041 +#define DDRSS_PHY_345_DATA 0x31C06000 +#define DDRSS_PHY_346_DATA 0x07AB0340 +#define DDRSS_PHY_347_DATA 0x0000C0C0 +#define DDRSS_PHY_348_DATA 0x04050000 +#define DDRSS_PHY_349_DATA 0x00000504 +#define DDRSS_PHY_350_DATA 0x42100010 +#define DDRSS_PHY_351_DATA 0x010C053E +#define DDRSS_PHY_352_DATA 0x000F0C1D +#define DDRSS_PHY_353_DATA 0x01000140 +#define DDRSS_PHY_354_DATA 0x007A0120 +#define DDRSS_PHY_355_DATA 0x00000C00 +#define DDRSS_PHY_356_DATA 0x000001CC +#define DDRSS_PHY_357_DATA 0x20100200 +#define DDRSS_PHY_358_DATA 0x00000005 +#define DDRSS_PHY_359_DATA 0x01324567 // [SWIZZLE] PHY_DQ_DM_SWIZZLE0_1 //0x76543210 //Normal +#define DDRSS_PHY_360_DATA 0x00000008 +#define DDRSS_PHY_361_DATA 0x034C034C +#define DDRSS_PHY_362_DATA 0x034C034C +#define DDRSS_PHY_363_DATA 0x034C034C +#define DDRSS_PHY_364_DATA 0x034C034C +#define DDRSS_PHY_365_DATA 0x0000034C +#define DDRSS_PHY_366_DATA 0x00008000 +#define DDRSS_PHY_367_DATA 0x00800080 +#define DDRSS_PHY_368_DATA 0x00800080 +#define DDRSS_PHY_369_DATA 0x00800080 +#define DDRSS_PHY_370_DATA 0x00800080 +#define DDRSS_PHY_371_DATA 0x00800080 +#define DDRSS_PHY_372_DATA 0x00800080 +#define DDRSS_PHY_373_DATA 0x00800080 +#define DDRSS_PHY_374_DATA 0x00800080 +#define DDRSS_PHY_375_DATA 0x01800080 +#define DDRSS_PHY_376_DATA 0x01000000 +#define DDRSS_PHY_377_DATA 0x00000000 +#define DDRSS_PHY_378_DATA 0x00000000 +#define DDRSS_PHY_379_DATA 0x00080200 +#define DDRSS_PHY_380_DATA 0x00000000 +#define DDRSS_PHY_381_DATA 0x0000F0F0 +#define DDRSS_PHY_382_DATA 0x00000000 +#define DDRSS_PHY_383_DATA 0x00000000 +#define DDRSS_PHY_384_DATA 0x00000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00000000 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x00000000 +#define DDRSS_PHY_390_DATA 0x00000000 +#define DDRSS_PHY_391_DATA 0x00000000 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x00000000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00000000 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x00000100 +#define DDRSS_PHY_518_DATA 0x00000200 +#define DDRSS_PHY_519_DATA 0x00000000 +#define DDRSS_PHY_520_DATA 0x00000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00400000 +#define DDRSS_PHY_524_DATA 0x00000080 +#define DDRSS_PHY_525_DATA 0x00DCBA98 +#define DDRSS_PHY_526_DATA 0x03000000 +#define DDRSS_PHY_527_DATA 0x00200000 +#define DDRSS_PHY_528_DATA 0x00000000 +#define DDRSS_PHY_529_DATA 0x00000000 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000000 +#define DDRSS_PHY_532_DATA 0x0000002A +#define DDRSS_PHY_533_DATA 0x00000015 +#define DDRSS_PHY_534_DATA 0x00000015 +#define DDRSS_PHY_535_DATA 0x0000002A +#define DDRSS_PHY_536_DATA 0x00000033 +#define DDRSS_PHY_537_DATA 0x0000000C +#define DDRSS_PHY_538_DATA 0x0000000C +#define DDRSS_PHY_539_DATA 0x00000033 +#define DDRSS_PHY_540_DATA 0x0A418820 +#define DDRSS_PHY_541_DATA 0x003F0000 +#define DDRSS_PHY_542_DATA 0x000F013F +#define DDRSS_PHY_543_DATA 0x0000000F +#define DDRSS_PHY_544_DATA 0x020002CC +#define DDRSS_PHY_545_DATA 0x00030000 +#define DDRSS_PHY_546_DATA 0x00000300 +#define DDRSS_PHY_547_DATA 0x00000300 +#define DDRSS_PHY_548_DATA 0x00000300 +#define DDRSS_PHY_549_DATA 0x00000300 +#define DDRSS_PHY_550_DATA 0x00000300 +#define DDRSS_PHY_551_DATA 0x42080010 +#define DDRSS_PHY_552_DATA 0x0000803E +#define DDRSS_PHY_553_DATA 0x00000003 +#define DDRSS_PHY_554_DATA 0x00000002 +#define DDRSS_PHY_555_DATA 0x00000000 +#define DDRSS_PHY_556_DATA 0x00000000 +#define DDRSS_PHY_557_DATA 0x00000000 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000000 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x00000000 +#define DDRSS_PHY_587_DATA 0x00000000 +#define DDRSS_PHY_588_DATA 0x00000000 +#define DDRSS_PHY_589_DATA 0x00000000 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x00000000 +#define DDRSS_PHY_592_DATA 0x00000000 +#define DDRSS_PHY_593_DATA 0x00000000 +#define DDRSS_PHY_594_DATA 0x00000000 +#define DDRSS_PHY_595_DATA 0x00000000 +#define DDRSS_PHY_596_DATA 0x00000000 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00000000 +#define DDRSS_PHY_600_DATA 0x00000000 +#define DDRSS_PHY_601_DATA 0x00000000 +#define DDRSS_PHY_602_DATA 0x00000000 +#define DDRSS_PHY_603_DATA 0x00000000 +#define DDRSS_PHY_604_DATA 0x00000000 +#define DDRSS_PHY_605_DATA 0x00000000 +#define DDRSS_PHY_606_DATA 0x00000000 +#define DDRSS_PHY_607_DATA 0x00000000 +#define DDRSS_PHY_608_DATA 0x00000000 +#define DDRSS_PHY_609_DATA 0x00000000 +#define DDRSS_PHY_610_DATA 0x00000000 +#define DDRSS_PHY_611_DATA 0x00000000 +#define DDRSS_PHY_612_DATA 0x00000000 +#define DDRSS_PHY_613_DATA 0x00000000 +#define DDRSS_PHY_614_DATA 0x00000000 +#define DDRSS_PHY_615_DATA 0x00000000 +#define DDRSS_PHY_616_DATA 0x00000000 +#define DDRSS_PHY_617_DATA 0x00000000 +#define DDRSS_PHY_618_DATA 0x00000000 +#define DDRSS_PHY_619_DATA 0x00000000 +#define DDRSS_PHY_620_DATA 0x00000000 +#define DDRSS_PHY_621_DATA 0x00000000 +#define DDRSS_PHY_622_DATA 0x00000000 +#define DDRSS_PHY_623_DATA 0x00000000 +#define DDRSS_PHY_624_DATA 0x00000000 +#define DDRSS_PHY_625_DATA 0x00000000 +#define DDRSS_PHY_626_DATA 0x00000000 +#define DDRSS_PHY_627_DATA 0x00000000 +#define DDRSS_PHY_628_DATA 0x00000000 +#define DDRSS_PHY_629_DATA 0x00000000 +#define DDRSS_PHY_630_DATA 0x00000000 +#define DDRSS_PHY_631_DATA 0x00000000 +#define DDRSS_PHY_632_DATA 0x00000000 +#define DDRSS_PHY_633_DATA 0x00000000 +#define DDRSS_PHY_634_DATA 0x00000000 +#define DDRSS_PHY_635_DATA 0x00000000 +#define DDRSS_PHY_636_DATA 0x00000000 +#define DDRSS_PHY_637_DATA 0x00000000 +#define DDRSS_PHY_638_DATA 0x00000000 +#define DDRSS_PHY_639_DATA 0x00000000 +#define DDRSS_PHY_640_DATA 0x00000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00000000 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x00000000 +#define DDRSS_PHY_646_DATA 0x00000000 +#define DDRSS_PHY_647_DATA 0x00000000 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x00000000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00000000 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x00000100 +#define DDRSS_PHY_774_DATA 0x00000200 +#define DDRSS_PHY_775_DATA 0x00000000 +#define DDRSS_PHY_776_DATA 0x00000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00400000 +#define DDRSS_PHY_780_DATA 0x00000080 +#define DDRSS_PHY_781_DATA 0x00DCBA98 +#define DDRSS_PHY_782_DATA 0x03000000 +#define DDRSS_PHY_783_DATA 0x00200000 +#define DDRSS_PHY_784_DATA 0x00000000 +#define DDRSS_PHY_785_DATA 0x00000000 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000000 +#define DDRSS_PHY_788_DATA 0x0000002A +#define DDRSS_PHY_789_DATA 0x00000015 +#define DDRSS_PHY_790_DATA 0x00000015 +#define DDRSS_PHY_791_DATA 0x0000002A +#define DDRSS_PHY_792_DATA 0x00000033 +#define DDRSS_PHY_793_DATA 0x0000000C +#define DDRSS_PHY_794_DATA 0x0000000C +#define DDRSS_PHY_795_DATA 0x00000033 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x000F0000 +#define DDRSS_PHY_799_DATA 0x0000000F +#define DDRSS_PHY_800_DATA 0x020002CC +#define DDRSS_PHY_801_DATA 0x00030000 +#define DDRSS_PHY_802_DATA 0x00000300 +#define DDRSS_PHY_803_DATA 0x00000300 +#define DDRSS_PHY_804_DATA 0x00000300 +#define DDRSS_PHY_805_DATA 0x00000300 +#define DDRSS_PHY_806_DATA 0x00000300 +#define DDRSS_PHY_807_DATA 0x42080010 +#define DDRSS_PHY_808_DATA 0x0000803E +#define DDRSS_PHY_809_DATA 0x00000003 +#define DDRSS_PHY_810_DATA 0x00000002 +#define DDRSS_PHY_811_DATA 0x00000000 +#define DDRSS_PHY_812_DATA 0x00000000 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000000 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x00000000 +#define DDRSS_PHY_843_DATA 0x00000000 +#define DDRSS_PHY_844_DATA 0x00000000 +#define DDRSS_PHY_845_DATA 0x00000000 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x00000000 +#define DDRSS_PHY_848_DATA 0x00000000 +#define DDRSS_PHY_849_DATA 0x00000000 +#define DDRSS_PHY_850_DATA 0x00000000 +#define DDRSS_PHY_851_DATA 0x00000000 +#define DDRSS_PHY_852_DATA 0x00000000 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00000000 +#define DDRSS_PHY_856_DATA 0x00000000 +#define DDRSS_PHY_857_DATA 0x00000000 +#define DDRSS_PHY_858_DATA 0x00000000 +#define DDRSS_PHY_859_DATA 0x00000000 +#define DDRSS_PHY_860_DATA 0x00000000 +#define DDRSS_PHY_861_DATA 0x00000000 +#define DDRSS_PHY_862_DATA 0x00000000 +#define DDRSS_PHY_863_DATA 0x00000000 +#define DDRSS_PHY_864_DATA 0x00000000 +#define DDRSS_PHY_865_DATA 0x00000000 +#define DDRSS_PHY_866_DATA 0x00000000 +#define DDRSS_PHY_867_DATA 0x00000000 +#define DDRSS_PHY_868_DATA 0x00000000 +#define DDRSS_PHY_869_DATA 0x00000000 +#define DDRSS_PHY_870_DATA 0x00000000 +#define DDRSS_PHY_871_DATA 0x00000000 +#define DDRSS_PHY_872_DATA 0x00000000 +#define DDRSS_PHY_873_DATA 0x00000000 +#define DDRSS_PHY_874_DATA 0x00000000 +#define DDRSS_PHY_875_DATA 0x00000000 +#define DDRSS_PHY_876_DATA 0x00000000 +#define DDRSS_PHY_877_DATA 0x00000000 +#define DDRSS_PHY_878_DATA 0x00000000 +#define DDRSS_PHY_879_DATA 0x00000000 +#define DDRSS_PHY_880_DATA 0x00000000 +#define DDRSS_PHY_881_DATA 0x00000000 +#define DDRSS_PHY_882_DATA 0x00000000 +#define DDRSS_PHY_883_DATA 0x00000000 +#define DDRSS_PHY_884_DATA 0x00000000 +#define DDRSS_PHY_885_DATA 0x00000000 +#define DDRSS_PHY_886_DATA 0x00000000 +#define DDRSS_PHY_887_DATA 0x00000000 +#define DDRSS_PHY_888_DATA 0x00000000 +#define DDRSS_PHY_889_DATA 0x00000000 +#define DDRSS_PHY_890_DATA 0x00000000 +#define DDRSS_PHY_891_DATA 0x00000000 +#define DDRSS_PHY_892_DATA 0x00000000 +#define DDRSS_PHY_893_DATA 0x00000000 +#define DDRSS_PHY_894_DATA 0x00000000 +#define DDRSS_PHY_895_DATA 0x00000000 +#define DDRSS_PHY_896_DATA 0x00000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00000000 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x00000000 +#define DDRSS_PHY_902_DATA 0x00000000 +#define DDRSS_PHY_903_DATA 0x00000000 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x0000002A +#define DDRSS_PHY_1045_DATA 0x00000015 +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x0000002A +#define DDRSS_PHY_1048_DATA 0x00000033 +#define DDRSS_PHY_1049_DATA 0x0000000C +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x00000033 +#define DDRSS_PHY_1052_DATA 0x2307B9AC +#define DDRSS_PHY_1053_DATA 0x10000000 +#define DDRSS_PHY_1054_DATA 0x000F0000 +#define DDRSS_PHY_1055_DATA 0x0000000F +#define DDRSS_PHY_1056_DATA 0x020002CC +#define DDRSS_PHY_1057_DATA 0x00030000 +#define DDRSS_PHY_1058_DATA 0x00000300 +#define DDRSS_PHY_1059_DATA 0x00000300 +#define DDRSS_PHY_1060_DATA 0x00000300 +#define DDRSS_PHY_1061_DATA 0x00000300 +#define DDRSS_PHY_1062_DATA 0x00000300 +#define DDRSS_PHY_1063_DATA 0x42080010 +#define DDRSS_PHY_1064_DATA 0x0000803E +#define DDRSS_PHY_1065_DATA 0x00000003 +#define DDRSS_PHY_1066_DATA 0x00000002 +#define DDRSS_PHY_1067_DATA 0x00000000 +#define DDRSS_PHY_1068_DATA 0x00000000 +#define DDRSS_PHY_1069_DATA 0x00000000 +#define DDRSS_PHY_1070_DATA 0x00000000 +#define DDRSS_PHY_1071_DATA 0x00000000 +#define DDRSS_PHY_1072_DATA 0x00000000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00010100 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000000 +#define DDRSS_PHY_1286_DATA 0x00050000 +#define DDRSS_PHY_1287_DATA 0x04000000 +#define DDRSS_PHY_1288_DATA 0x00000055 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00000000 +#define DDRSS_PHY_1292_DATA 0x00000000 +#define DDRSS_PHY_1293_DATA 0x00002001 +#define DDRSS_PHY_1294_DATA 0x00004001 +#define DDRSS_PHY_1295_DATA 0x00020028 +#define DDRSS_PHY_1296_DATA 0x01010100 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x0F0F0E06 +#define DDRSS_PHY_1300_DATA 0x00010101 +#define DDRSS_PHY_1301_DATA 0x010F0004 +#define DDRSS_PHY_1302_DATA 0x00000000 +#define DDRSS_PHY_1303_DATA 0x00000000 +#define DDRSS_PHY_1304_DATA 0x00000064 +#define DDRSS_PHY_1305_DATA 0x00000000 +#define DDRSS_PHY_1306_DATA 0x00000000 +#define DDRSS_PHY_1307_DATA 0x01020103 +#define DDRSS_PHY_1308_DATA 0x0F020102 +#define DDRSS_PHY_1309_DATA 0x03030303 +#define DDRSS_PHY_1310_DATA 0x03030303 +#define DDRSS_PHY_1311_DATA 0x00041B42 +#define DDRSS_PHY_1312_DATA 0x00005201 +#define DDRSS_PHY_1313_DATA 0x00000000 +#define DDRSS_PHY_1314_DATA 0x00000000 +#define DDRSS_PHY_1315_DATA 0x00000000 +#define DDRSS_PHY_1316_DATA 0x00000000 +#define DDRSS_PHY_1317_DATA 0x00000000 +#define DDRSS_PHY_1318_DATA 0x00000000 +#define DDRSS_PHY_1319_DATA 0x07030101 +#define DDRSS_PHY_1320_DATA 0x00005400 +#define DDRSS_PHY_1321_DATA 0x000040A2 +#define DDRSS_PHY_1322_DATA 0x00024410 +#define DDRSS_PHY_1323_DATA 0x00004410 +#define DDRSS_PHY_1324_DATA 0x00004410 +#define DDRSS_PHY_1325_DATA 0x00004410 +#define DDRSS_PHY_1326_DATA 0x00004410 +#define DDRSS_PHY_1327_DATA 0x00004410 +#define DDRSS_PHY_1328_DATA 0x00004410 +#define DDRSS_PHY_1329_DATA 0x00004410 +#define DDRSS_PHY_1330_DATA 0x00004410 +#define DDRSS_PHY_1331_DATA 0x00004410 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000076 +#define DDRSS_PHY_1334_DATA 0x00000400 +#define DDRSS_PHY_1335_DATA 0x00000008 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x03000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x04102006 +#define DDRSS_PHY_1346_DATA 0x00041020 +#define DDRSS_PHY_1347_DATA 0x01C98C98 +#define DDRSS_PHY_1348_DATA 0x3F400000 +#define DDRSS_PHY_1349_DATA 0x3F3F1F3F +#define DDRSS_PHY_1350_DATA 0x0000001F +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000001 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x76543201 // [SWAP] PHY_DATA_BYTE_ORDER_SEL //0x76543210 //Normal +#define DDRSS_PHY_1360_DATA 0x00040198 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00040700 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000002 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000AC3 +#define DDRSS_PHY_1372_DATA 0x00020002 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00001142 +#define DDRSS_PHY_1375_DATA 0x03020000 +#define DDRSS_PHY_1376_DATA 0x00000080 +#define DDRSS_PHY_1377_DATA 0x03900390 +#define DDRSS_PHY_1378_DATA 0x03900390 +#define DDRSS_PHY_1379_DATA 0x03900390 +#define DDRSS_PHY_1380_DATA 0x03900390 +#define DDRSS_PHY_1381_DATA 0x03000300 +#define DDRSS_PHY_1382_DATA 0x03000300 +#define DDRSS_PHY_1383_DATA 0x00000300 +#define DDRSS_PHY_1384_DATA 0x00000300 +#define DDRSS_PHY_1385_DATA 0x00000300 +#define DDRSS_PHY_1386_DATA 0x00000300 +#define DDRSS_PHY_1387_DATA 0x3183BF77 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x0C000DFF +#define DDRSS_PHY_1390_DATA 0x30000DFF +#define DDRSS_PHY_1391_DATA 0x3F0DFF11 +#define DDRSS_PHY_1392_DATA 0x01990000 +#define DDRSS_PHY_1393_DATA 0x780DFFCC +#define DDRSS_PHY_1394_DATA 0x00000C11 +#define DDRSS_PHY_1395_DATA 0x00018011 +#define DDRSS_PHY_1396_DATA 0x0089FF00 +#define DDRSS_PHY_1397_DATA 0x000C3F11 +#define DDRSS_PHY_1398_DATA 0x01990000 +#define DDRSS_PHY_1399_DATA 0x000C3F11 +#define DDRSS_PHY_1400_DATA 0x01990000 +#define DDRSS_PHY_1401_DATA 0x3F0DFF11 +#define DDRSS_PHY_1402_DATA 0x01990000 +#define DDRSS_PHY_1403_DATA 0x00018011 +#define DDRSS_PHY_1404_DATA 0x0089FF00 +#define DDRSS_PHY_1405_DATA 0x20040002 diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi index 5e8036f32d..f8d8b9e85d 100644 --- a/arch/arm/dts/k3-am64-main.dtsi +++ b/arch/arm/dts/k3-am64-main.dtsi @@ -473,6 +473,9 @@ mmc-ddr-1_8v; mmc-hs200-1_8v; ti,trm-icp = <0x2>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xA>; + ti,itap-del-sel-ddr52 = <0x3>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; @@ -487,6 +490,10 @@ clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; clock-names = "clk_ahb", "clk_xin"; ti,trm-icp = <0x2>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0xf>; ti,otap-del-sel-sdr12 = <0xf>; diff --git a/arch/arm/dts/k3-am642-evm-nand.dts b/arch/arm/dts/k3-am642-evm-nand.dts new file mode 100644 index 0000000000..72302533da --- /dev/null +++ b/arch/arm/dts/k3-am642-evm-nand.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for HSE NAND expansion card on AM642 EVM + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/k3.h> + +#include "k3-am642-evm-nand.dtsi" diff --git a/arch/arm/dts/k3-am642-evm-nand.dtsi b/arch/arm/dts/k3-am642-evm-nand.dtsi new file mode 100644 index 0000000000..5e0e79cc82 --- /dev/null +++ b/arch/arm/dts/k3-am642-evm-nand.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for HSE NAND expansion card on AM642 EVM + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; +}; + +&main_pmx0 { + gpmc0_pins_default: gpmc0-pins-default { + bootph-pre-ram; + pinctrl-single,pins = < + AM64X_IOPAD(0x0094, PIN_INPUT, 7) /* (T19) GPMC0_BE1n.GPIO0_36 */ + + AM64X_IOPAD(0x003c, PIN_INPUT, 0) /* (T20) GPMC0_AD0 */ + AM64X_IOPAD(0x0040, PIN_INPUT, 0) /* (U21) GPMC0_AD1 */ + AM64X_IOPAD(0x0064, PIN_INPUT, 0) /* (R16) GPMC0_AD10 */ + AM64X_IOPAD(0x0068, PIN_INPUT, 0) /* (W20) GPMC0_AD11 */ + AM64X_IOPAD(0x006c, PIN_INPUT, 0) /* (W21) GPMC0_AD12 */ + AM64X_IOPAD(0x0070, PIN_INPUT, 0) /* (V18) GPMC0_AD13 */ + AM64X_IOPAD(0x0074, PIN_INPUT, 0) /* (Y21) GPMC0_AD14 */ + AM64X_IOPAD(0x0078, PIN_INPUT, 0) /* (Y20) GPMC0_AD15 */ + AM64X_IOPAD(0x0044, PIN_INPUT, 0) /* (T18) GPMC0_AD2 */ + AM64X_IOPAD(0x0048, PIN_INPUT, 0) /* (U20) GPMC0_AD3 */ + AM64X_IOPAD(0x004c, PIN_INPUT, 0) /* (U18) GPMC0_AD4 */ + AM64X_IOPAD(0x0050, PIN_INPUT, 0) /* (U19) GPMC0_AD5 */ + AM64X_IOPAD(0x0054, PIN_INPUT, 0) /* (V20) GPMC0_AD6 */ + AM64X_IOPAD(0x0058, PIN_INPUT, 0) /* (V21) GPMC0_AD7 */ + AM64X_IOPAD(0x005c, PIN_INPUT, 0) /* (V19) GPMC0_AD8 */ + AM64X_IOPAD(0x0060, PIN_INPUT, 0) /* (T17) GPMC0_AD9 */ + AM64X_IOPAD(0x0098, PIN_INPUT_PULLUP, 0) /* (W19) GPMC0_WAIT0 */ + AM64X_IOPAD(0x009c, PIN_INPUT_PULLUP, 0) /* (Y18) GPMC0_WAIT1 */ + AM64X_IOPAD(0x00a8, PIN_OUTPUT_PULLUP, 0) /* (R19) GPMC0_CSn0 */ + AM64X_IOPAD(0x00ac, PIN_OUTPUT_PULLUP, 0) /* (R20) GPMC0_CSn1 */ + AM64X_IOPAD(0x00b0, PIN_OUTPUT_PULLUP, 0) /* (P19) GPMC0_CSn2 */ + AM64X_IOPAD(0x00b4, PIN_OUTPUT_PULLUP, 0) /* (R21) GPMC0_CSn3 */ + AM64X_IOPAD(0x007c, PIN_OUTPUT, 0) /* (R17) GPMC0_CLK */ + AM64X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (P16) GPMC0_ADVn_ALE */ + AM64X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (R18) GPMC0_OEn_REn */ + AM64X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (T21) GPMC0_WEn */ + AM64X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (P17) GPMC0_BE0n_CLE */ + AM64X_IOPAD(0x00a0, PIN_OUTPUT_PULLUP, 0) /* (N16) GPMC0_WPn */ + AM64X_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (N17) GPMC0_DIR */ + >; + }; +}; + +&main_gpio0 { + gpio0-36 { + bootph-pre-ram; + gpio-hog; + gpios = <36 0>; + input; + line-name = "GPMC0_MUX_DIR"; + }; +}; + +&elm0 { + status = "okay"; +}; + +&gpmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gpmc0_pins_default>; + ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + #address-cells = <2>; + #size-cells = <1>; + + nand0_0: nand@0,0 { + bootph-pre-ram; + compatible = "ti,am64-nand"; + reg = <0 0 64>; /* device IO registers */ + interrupt-parent = <&gpmc0>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-polled"; + ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */ + ti,elm-id = <&elm0>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <25>; + gpmc,adv-wr-off-ns = <25>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <3>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "NAND.tiboot3"; + reg = <0x00000000 0x00200000>; /* 2M */ + }; + partition@200000 { + label = "NAND.tispl"; + reg = <0x00200000 0x00200000>; /* 2M */ + }; + partition@400000 { + label = "NAND.tiboot3.backup"; /* 2M */ + reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */ + }; + partition@600000 { + label = "NAND.u-boot"; + reg = <0x00600000 0x00400000>; /* 4M */ + }; + partition@a00000 { + label = "NAND.u-boot-env"; + reg = <0x00a00000 0x00040000>; /* 256K */ + }; + partition@a40000 { + label = "NAND.u-boot-env.backup"; + reg = <0x00a40000 0x00040000>; /* 256K */ + }; + partition@a80000 { + label = "NAND.file-system"; + reg = <0x00a80000 0x3f580000>; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi index fae197dff5..e56bdea3d7 100644 --- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi @@ -36,30 +36,18 @@ &main_pmx0 { bootph-pre-ram; - main_i2c0_pins_default: main-i2c0-pins-default { - bootph-pre-ram; - pinctrl-single,pins = < - AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ - AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ - >; - }; +}; + +&main_i2c0_pins_default { + bootph-pre-ram; }; &main_i2c0 { - status = "okay"; bootph-pre-ram; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; +}; - tca9554: gpio@38 { - /* TCA9554 */ - bootph-pre-ram; - compatible = "nxp,pca9554"; - reg = <0x38>; - gpio-controller; - #gpio-cells = <2>; - }; +&tca9554 { + bootph-pre-ram; }; &main_uart0 { @@ -192,3 +180,15 @@ }; }; }; + +&gpmc0 { + bootph-pre-ram; +}; + +&elm0 { + bootph-pre-ram; +}; + +&main_gpio0 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts index 7f82730736..dcd8f7ba4c 100644 --- a/arch/arm/dts/k3-am642-evm.dts +++ b/arch/arm/dts/k3-am642-evm.dts @@ -233,6 +233,13 @@ >; }; + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ @@ -335,6 +342,21 @@ status = "reserved"; }; +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + tca9554: gpio@38 { + /* TCA9554 */ + compatible = "nxp,pca9554"; + reg = <0x38>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &main_i2c1 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index 6b32be1c4c..b10e6d9b17 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -226,6 +226,13 @@ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ >; }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ + >; + }; }; &dmsc { @@ -284,6 +291,13 @@ /* EEPROM might be read before SYSFW is available */ &main_i2c0 { /delete-property/ power-domains; + tca9554: gpio@38 { + /* TCA9554 */ + compatible = "nxp,pca9554"; + reg = <0x38>; + gpio-controller; + #gpio-cells = <2>; + }; }; &usbss0 { diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi index 24f562aafd..ec6dfae3f2 100644 --- a/arch/arm/dts/k3-am64x-binman.dtsi +++ b/arch/arm/dts/k3-am64x-binman.dtsi @@ -126,6 +126,8 @@ #define AM642_EVM_DTB "u-boot.dtb" #define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb" +#define AM642_EVM_NAND_DTBO "arch/arm/dts/k3-am642-evm-nand.dtbo" + &binman { ti-spl { filename = "tispl.bin"; @@ -229,6 +231,20 @@ }; }; + + fdt-2 { + description = "k3-am642-evm-nand overlay"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am64x_evm_nand_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am64x_evm_nand_dtb: blob-ext { + filename = AM642_EVM_NAND_DTBO; + }; + }; }; configurations { @@ -247,6 +263,13 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-1"; }; + + conf-2 { + description = "k3-am642-evm-nand"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0", "fdt-2"; + }; }; }; }; @@ -315,6 +338,23 @@ }; }; + fdt-2 { + description = "k3-am642-evm-nand overlay"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am64x_evm_nand_dtb>; + keyfile = "custMpk.pem"; + + }; + am64x_evm_nand_dtb: blob-ext { + filename = AM642_EVM_NAND_DTBO; + }; + hash { + algo = "crc32"; + }; + }; }; configurations { @@ -333,6 +373,13 @@ loadables = "uboot"; fdt = "fdt-1"; }; + + conf-2 { + description = "k3-am642-evm-nand"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0", "fdt-2"; + }; }; }; }; @@ -418,6 +465,16 @@ filename = SPL_AM642_SK_DTB; }; }; + + fdt-2 { + description = "k3-am642-evm-nand overlay"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM642_EVM_NAND_DTBO; + }; + }; }; configurations { @@ -436,6 +493,13 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-1"; }; + + conf-2 { + description = "k3-am642-evm-nand"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0", "fdt-2"; + }; }; }; }; @@ -490,6 +554,19 @@ algo = "crc32"; }; }; + + fdt-2 { + description = "k3-am642-evm-nand overlay"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM642_EVM_NAND_DTBO; + }; + hash { + algo = "crc32"; + }; + }; }; configurations { @@ -508,6 +585,13 @@ loadables = "uboot"; fdt = "fdt-1"; }; + + conf-2 { + description = "k3-am642-evm-nand"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0", "fdt-2"; + }; }; }; }; diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts index cfbcebfa37..7bc8b0d5b6 100644 --- a/arch/arm/dts/k3-am654-base-board.dts +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -282,6 +282,13 @@ pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; + gpio@38 { + compatible = "nxp,pca9554"; + reg = <0x38>; + gpio-controller; + #gpio-cells = <2>; + }; + pca9554: gpio@39 { compatible = "nxp,pca9554"; reg = <0x39>; diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi index 97a3573bdb..c246bbe81e 100644 --- a/arch/arm/dts/k3-binman.dtsi +++ b/arch/arm/dts/k3-binman.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include "k3-security.h" + / { binman: binman { multiple-images; diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index 2a1be4a9e0..d55b3ba403 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -55,6 +55,7 @@ <&combined_dm_cfg>, <&sysfw_inner_cert>; combined; dm-data; + core-opts = <2>; sysfw-inner-cert; keyfile = "custMpk.pem"; sw-rev = <1>; @@ -100,6 +101,7 @@ <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; combined; dm-data; + core-opts = <2>; sysfw-inner-cert; keyfile = "custMpk.pem"; sw-rev = <1>; @@ -146,6 +148,7 @@ <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; combined; dm-data; + core-opts = <2>; content-sbl = <&u_boot_spl_unsigned>; load = <0x41c00000>; content-sysfw = <&ti_fs_gp>; @@ -214,6 +217,74 @@ ti-secure { content = <&atf>; keyfile = "custMpk.pem"; + auth-in-place = <0xa02>; + + firewall-257-0 { + /* cpu_0_cpu_0_msmc Background Firewall */ + id = <257>; + region = <0>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_BG | FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; + end_address = <0xff 0xffffffff>; + }; + + firewall-257-1 { + /* cpu_0_cpu_0_msmc Foreground Firewall */ + id = <257>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x70000000>; + end_address = <0x0 0x7001ffff>; + }; + + /* firewall-4760-0 { + * nb_slv0__mem0 Background Firewall + * Already configured by the secure entity + * }; + */ + + firewall-4760-1 { + /* nb_slv0__mem0 Foreground Firewall */ + id = <4760>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x70000000>; + end_address = <0x0 0x7001ffff>; + }; + + /* firewall-4761-0 { + * nb_slv1__mem0 Background Firewall + * Already configured by the secure entity + * }; + */ + + firewall-4761-1 { + /* nb_slv1__mem0 Foreground Firewall */ + id = <4761>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x70000000>; + end_address = <0x0 0x7001ffff>; + }; + }; atf: atf-bl31 { }; @@ -230,6 +301,81 @@ ti-secure { content = <&tee>; keyfile = "custMpk.pem"; + auth-in-place = <0xa02>; + + /* cpu_0_cpu_0_msmc region 0 and 1 configured + * during ATF Firewalling + */ + + firewall-257-2 { + /* cpu_0_cpu_0_msmc Foreground Firewall */ + id = <257>; + region = <2>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + + firewall-4762-0 { + /* nb_slv2__mem0 Background Firewall - 0 */ + id = <4762>; + region = <0>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_BG | FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; + end_address = <0xff 0xffffffff>; + }; + + firewall-4762-1 { + /* nb_slv2__mem0 Foreground Firewall */ + id = <4762>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + + firewall-4763-0 { + /* nb_slv3__mem0 Background Firewall - 0 */ + id = <4763>; + region = <0>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_BG | FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; + end_address = <0xff 0xffffffff>; + }; + + firewall-4763-1 { + /* nb_slv3__mem0 Foreground Firewall */ + id = <4763>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + }; tee: tee-os { }; diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi index bff00a627e..54581734e1 100644 --- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi @@ -339,7 +339,7 @@ mcu_r5fss0: r5fss@41000000 { compatible = "ti,j7200-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x41000000 0x00 0x41000000 0x20000>, @@ -347,7 +347,7 @@ power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j7200-r5f"; + compatible = "ti,j7200-mcu-r5f"; reg = <0x41000000 0x00010000>, <0x41010000 0x00010000>; reg-names = "atcm", "btcm"; @@ -362,7 +362,7 @@ }; mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j7200-r5f"; + compatible = "ti,j7200-mcu-r5f"; reg = <0x41400000 0x00008000>, <0x41410000 0x00008000>; reg-names = "atcm", "btcm"; @@ -376,4 +376,11 @@ ti,loczrama = <1>; }; }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; }; diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index c2c137006a..5e39b10f3a 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -94,7 +94,8 @@ wkup_vtm0: vtm@42040000 { compatible = "ti,am654-vtm", "ti,j721e-avs"; - reg = <0x0 0x42040000 0x0 0x330>; + reg = <0x0 0x42040000 0x0 0x330>, + <0x00 0x42050000 0x00 0x350>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 1fffc8c441..8f58f4e17f 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -13,6 +13,7 @@ ti-secure-rom { content = <&u_boot_spl>; core = "public"; + core-opts = <2>; load = <CONFIG_SPL_TEXT_BASE>; keyfile = "custMpk.pem"; }; @@ -123,6 +124,7 @@ ti-secure-rom { content = <&u_boot_spl_fs>; core = "public"; + core-opts = <2>; load = <CONFIG_SPL_TEXT_BASE>; keyfile = "custMpk.pem"; }; @@ -211,6 +213,7 @@ ti-secure-rom { content = <&u_boot_spl_unsigned>; core = "public"; + core-opts = <2>; load = <CONFIG_SPL_TEXT_BASE>; sw-rev = <CONFIG_K3_X509_SWRV>; keyfile = "ti-degenerate-key.pem"; @@ -330,6 +333,102 @@ ti-secure { content = <&atf>; keyfile = "custMpk.pem"; + auth-in-place = <0xa02>; + + firewall-257-0 { + /* cpu_0_cpu_0_msmc Background Firewall */ + id = <257>; + region = <0>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_BG | FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; + end_address = <0xff 0xffffffff>; + }; + + firewall-257-1 { + /* cpu_0_cpu_0_msmc Foreground Firewall */ + id = <257>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x70000000>; + end_address = <0x0 0x7001ffff>; + }; + + firewall-284-0 { + /* dru_0_msmc Background Firewall */ + id = <284>; + region = <0>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_BG | FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; + end_address = <0xff 0xffffffff>; + }; + + firewall-284-1 { + /* dru_0_msmc Foreground Firewall */ + id = <284>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x70000000>; + end_address = <0x0 0x7001ffff>; + }; + + /* firewall-4760-0 { + * nb_slv0__mem0 Background Firewall + * Already configured by the secure entity + * }; + */ + + firewall-4760-1 { + /* nb_slv0__mem0 Foreground Firewall */ + id = <4760>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x70000000>; + end_address = <0x0 0x7001ffff>; + }; + + /* firewall-4761-0 { + * nb_slv1__mem0 Background Firewall + * Already configured by the secure entity + * }; + */ + + firewall-4761-1 { + /* nb_slv1__mem0 Foreground Firewall */ + id = <4761>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x70000000>; + end_address = <0x0 0x7001ffff>; + }; + }; atf: atf-bl31 { }; @@ -346,6 +445,97 @@ ti-secure { content = <&tee>; keyfile = "custMpk.pem"; + auth-in-place = <0xa02>; + + /* cpu_0_cpu_0_msmc region 0 and 1 configured + * during ATF Firewalling + */ + + firewall-257-2 { + /* cpu_0_cpu_0_msmc Foreground Firewall */ + id = <257>; + region = <2>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + + /* dru_0_msmc region 0 and 1 configured + * during ATF Firewalling + */ + + firewall-284-2 { + /* dru_0_msmc Foreground Firewall */ + id = <284>; + region = <2>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + + firewall-4762-0 { + /* nb_slv2__mem0 Background Firewall */ + id = <4762>; + region = <0>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_BG | FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; + end_address = <0xff 0xffffffff>; + }; + + firewall-4762-1 { + /* nb_slv2__mem0 Foreground Firewall */ + id = <4762>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + + firewall-4763-0 { + /* nb_slv3__mem0 Background Firewall */ + id = <4763>; + region = <0>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_BG | FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; + end_address = <0xff 0xffffffff>; + }; + + firewall-4763-1 { + /* nb_slv3__mem0 Foreground Firewall */ + id = <4763>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; }; tee: tee-os { }; diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index a40d510e39..1bfbf457dc 100644 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi @@ -372,7 +372,7 @@ mcu_r5fss0: r5fss@41000000 { compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x41000000 0x00 0x41000000 0x20000>, @@ -380,7 +380,7 @@ power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j721e-r5f"; + compatible = "ti,j721e-mcu-r5f"; reg = <0x41000000 0x00008000>, <0x41010000 0x00008000>; reg-names = "atcm", "btcm"; @@ -395,7 +395,7 @@ }; mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j721e-r5f"; + compatible = "ti,j721e-mcu-r5f"; reg = <0x41400000 0x00008000>, <0x41410000 0x00008000>; reg-names = "atcm", "btcm"; @@ -409,4 +409,11 @@ ti,loczrama = <1>; }; }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; }; diff --git a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts index 950df42d72..68aa7e7411 100644 --- a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts +++ b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts @@ -63,8 +63,10 @@ }; wkup_vtm0: wkup_vtm@42040000 { - compatible = "ti,am654-vtm", "ti,j721e-avs"; - reg = <0x0 0x42040000 0x0 0x330>; + compatible = "ti,am654-vtm", "ti,j721e-avs", "ti,j721e-vtm"; + reg = <0x0 0x42040000 0x0 0x330>, + <0x00 0x42050000 0x00 0x350>, + <0x00 0x43000300 0x00 0x10>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 7f70e347c9..45c3f3821e 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -73,8 +73,10 @@ }; wkup_vtm0: wkup_vtm@42040000 { - compatible = "ti,am654-vtm", "ti,j721e-avs"; - reg = <0x0 0x42040000 0x0 0x330>; + compatible = "ti,am654-vtm", "ti,j721e-avs", "ti,j721e-vtm"; + reg = <0x0 0x42040000 0x0 0x330>, + <0x00 0x42050000 0x00 0x350>, + <0x00 0x43000300 0x00 0x10>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; @@ -356,7 +358,7 @@ flash@0{ compatible = "jedec,spi-nor"; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <50000000>; cdns,tshsl-ns = <60>; diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts index 6986292e37..89344a4b24 100644 --- a/arch/arm/dts/k3-j721e-r5-sk.dts +++ b/arch/arm/dts/k3-j721e-r5-sk.dts @@ -205,8 +205,10 @@ }; wkup_vtm0: wkup_vtm@42040000 { - compatible = "ti,am654-vtm", "ti,j721e-avs"; - reg = <0x0 0x42040000 0x0 0x330>; + compatible = "ti,am654-vtm", "ti,j721e-avs", "ti,j721e-vtm"; + reg = <0x0 0x42040000 0x0 0x330>, + <0x00 0x42050000 0x00 0x350>, + <0x00 0x43000300 0x00 0x10>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 6a157ff0ee..72278f8322 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -15,6 +15,7 @@ <&combined_dm_cfg>, <&sysfw_inner_cert>; combined; dm-data; + core-opts = <2>; sysfw-inner-cert; keyfile = "custMpk.pem"; sw-rev = <1>; @@ -60,6 +61,7 @@ <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; combined; dm-data; + core-opts = <2>; sysfw-inner-cert; keyfile = "custMpk.pem"; sw-rev = <1>; @@ -106,6 +108,7 @@ <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; combined; dm-data; + core-opts = <2>; content-sbl = <&u_boot_spl_unsigned>; load = <0x41c00000>; content-sysfw = <&ti_fs_gp>; @@ -177,6 +180,102 @@ ti-secure { content = <&atf>; keyfile = "custMpk.pem"; + auth-in-place = <0xa02>; + + firewall-257-0 { + /* cpu_0_cpu_0_msmc Background Firewall */ + id = <257>; + region = <0>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_BG | FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; + end_address = <0xff 0xffffffff>; + }; + + firewall-257-1 { + /* cpu_0_cpu_0_msmc Foreground Firewall */ + id = <257>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x70000000>; + end_address = <0x0 0x7001ffff>; + }; + + firewall-284-0 { + /* dru_0_msmc Background Firewall */ + id = <284>; + region = <0>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_BG | FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; + end_address = <0xff 0xffffffff>; + }; + + firewall-284-1 { + /* dru_0_msmc Foreground Firewall */ + id = <284>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x70000000>; + end_address = <0x0 0x7001ffff>; + }; + + /* firewall-5140-0 { + * nb_slv0__mem0 Background Firewall + * Already configured by the secure entity + * }; + */ + + firewall-5140-1 { + /* nb_slv0__mem0 Foreground Firewall */ + id = <5140>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x70000000>; + end_address = <0x0 0x7001ffff>; + }; + + /* firewall-5140-0 { + * nb_slv1__mem0 Background Firewall + * Already configured by the secure entity + * }; + */ + + firewall-5141-1 { + /* nb_slv1__mem0 Foreground Firewall */ + id = <5141>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x70000000>; + end_address = <0x0 0x7001ffff>; + }; + }; atf: atf-bl31 { }; @@ -193,6 +292,118 @@ ti-secure { content = <&tee>; keyfile = "custMpk.pem"; + auth-in-place = <0xa02>; + + firewall-257-2 { + /* cpu_0_cpu_0_msmc Foreground Firewall */ + id = <257>; + region = <2>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + + firewall-284-2 { + /* dru_0_msmc Foreground Firewall */ + id = <284>; + region = <2>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + + firewall-5142-0 { + /* nb_slv2__mem0 Background Firewall - 0 */ + id = <5142>; + region = <0>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_BG | FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; + end_address = <0xff 0xffffffff>; + }; + + firewall-5142-1 { + /* nb_slv2__mem0 Foreground Firewall */ + id = <5142>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + + firewall-5143-0 { + /* nb_slv3__mem0 Background Firewall - 0 */ + id = <5143>; + region = <0>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_BG | FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; + end_address = <0xff 0xffffffff>; + }; + + firewall-5143-1 { + /* nb_slv3__mem0 Foreground Firewall */ + id = <5143>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + + firewall-5144-0 { + /* nb_slv4__mem0 Background Firewall - 0 */ + id = <5144>; + region = <0>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_BG | FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; + end_address = <0xff 0xffffffff>; + }; + + firewall-5144-1 { + /* nb_slv4__mem0 Foreground Firewall */ + id = <5144>; + region = <1>; + control = <(FWCTRL_EN | FWCTRL_LOCK | + FWCTRL_CACHE)>; + permissions = <((FWPRIVID_ARMV8 << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD)>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + }; tee: tee-os { }; diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi index fa1dc25037..da63385646 100644 --- a/arch/arm/dts/k3-j721s2-main.dtsi +++ b/arch/arm/dts/k3-j721s2-main.dtsi @@ -1184,4 +1184,11 @@ resets = <&k3_reset 11 1>; firmware-name = "j721s2-c71_1-fw"; }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x700000 0x00 0x1000>; + ti,esm-pins = <688>, <689>; + bootph-pre-ram; + }; }; diff --git a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi index 222da2a00a..b55f508728 100644 --- a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi @@ -304,7 +304,7 @@ mcu_r5fss0: r5fss@41000000 { compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x41000000 0x00 0x41000000 0x20000>, @@ -312,7 +312,7 @@ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j721s2-r5f"; + compatible = "ti,j721s2-mcu-r5f"; reg = <0x41000000 0x00010000>, <0x41010000 0x00010000>; reg-names = "atcm", "btcm"; @@ -327,7 +327,7 @@ }; mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j721s2-r5f"; + compatible = "ti,j721s2-mcu-r5f"; reg = <0x41400000 0x00010000>, <0x41410000 0x00010000>; reg-names = "atcm", "btcm"; @@ -380,4 +380,18 @@ #size-cells = <0>; }; }; + + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; + + wkup_esm: esm@42080000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x42080000 0x00 0x1000>; + ti,esm-pins = <63>; + bootph-pre-ram; + }; }; diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts index 9eb23ee196..ceb0d575be 100644 --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts @@ -139,6 +139,14 @@ >; }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + bootph-pre-ram; + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ + >; + }; + wkup_uart0_pins_default: wkup-uart0-pins-default { bootph-pre-ram; pinctrl-single,pins = < @@ -312,4 +320,26 @@ ti,sci = <&dm_tifs>; }; +&wkup_i2c0 { + bootph-pre-ram; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + tps659413: tps659413@48 { + compatible = "ti,tps659413"; + reg = <0x48>; + bootph-pre-ram; + + regulators: regulators { + bootph-pre-ram; + }; + + esm: esm { + compatible = "ti,tps659413-esm"; + bootph-pre-ram; + }; + }; +}; + #include "k3-j721s2-common-proc-board-u-boot.dtsi" diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi b/arch/arm/dts/k3-j721s2-som-p0.dtsi index 080bc0e5c9..11d620a78c 100644 --- a/arch/arm/dts/k3-j721s2-som-p0.dtsi +++ b/arch/arm/dts/k3-j721s2-som-p0.dtsi @@ -395,8 +395,8 @@ ospi0_nand: nand@0 { compatible = "spi-nand"; reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; spi-max-frequency = <25000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; diff --git a/arch/arm/dts/k3-j721s2.dtsi b/arch/arm/dts/k3-j721s2.dtsi index fe5234c40f..b602b453ef 100644 --- a/arch/arm/dts/k3-j721s2.dtsi +++ b/arch/arm/dts/k3-j721s2.dtsi @@ -114,6 +114,7 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi index c86ab875be..78fa4b80a0 100644 --- a/arch/arm/dts/k3-j784s4-binman.dtsi +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -19,6 +19,7 @@ <&combined_dm_cfg>, <&sysfw_inner_cert>; combined; dm-data; + core-opts = <2>; sysfw-inner-cert; keyfile = "custMpk.pem"; sw-rev = <1>; @@ -64,6 +65,7 @@ <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; combined; dm-data; + core-opts = <2>; sysfw-inner-cert; keyfile = "custMpk.pem"; sw-rev = <1>; @@ -110,6 +112,7 @@ <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; combined; dm-data; + core-opts = <2>; content-sbl = <&u_boot_spl_unsigned>; load = <0x41c00000>; content-sysfw = <&ti_fs_gp>; diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi index dba6a41476..965aeed652 100644 --- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi @@ -192,10 +192,26 @@ bootph-pre-ram; }; +&wkup_gpio_pins_default { + bootph-pre-ram; +}; + +&wkup_gpio0 { + bootph-pre-ram; +}; + +&mcu_fss0_ospi0_pins_default { + bootph-pre-ram; +}; + +&mcu_fss0_ospi0_pins1_default { + bootph-pre-ram; +}; + &ospi0 { bootph-pre-ram; - flash@0 { + ospi0_nor: flash@0 { bootph-pre-ram; partitions { @@ -208,10 +224,14 @@ }; }; +&ospi0_nand { + bootph-pre-ram; +}; + &ospi1 { bootph-pre-ram; +}; - flash@0 { - bootph-pre-ram; - }; +&ospi1_nor { + bootph-pre-ram; }; diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts index 1118960916..19e4bf72c9 100644 --- a/arch/arm/dts/k3-j784s4-evm.dts +++ b/arch/arm/dts/k3-j784s4-evm.dts @@ -334,6 +334,11 @@ >; }; + wkup_gpio_pins_default: wkup_gpio_pins_default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 7) /* (L37) WKUP_GPIO0_6 */ + >; + }; }; &wkup_pmx0 { @@ -692,7 +697,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_pins1_default>; - flash@0{ + ospi0_nor: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -746,13 +751,74 @@ }; }; }; + + ospi0_nand: nand@0 { + compatible = "spi-nand"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + status = "disabled"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi_nand.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi_nand.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi_nand.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi_nand.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi_nand.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@2000000 { + label = "ospi_nand.rootfs"; + reg = <0x2000000 0x5fc0000>; + }; + + partition@7fc0000 { + label = "ospi_nand.phypattern"; + reg = <0x7fc0000 0x40000>; + }; + }; + }; +}; + +&wkup_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; }; &ospi1 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - flash@0{ + ospi1_nor: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/k3-j784s4-main.dtsi b/arch/arm/dts/k3-j784s4-main.dtsi index f52689de08..f3f689c166 100644 --- a/arch/arm/dts/k3-j784s4-main.dtsi +++ b/arch/arm/dts/k3-j784s4-main.dtsi @@ -1253,4 +1253,12 @@ resets = <&k3_reset 40 1>; firmware-name = "j784s4-c71_3-fw"; }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x700000 0x00 0x1000>; + ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>, + <695>; + bootph-pre-ram; + }; }; diff --git a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi index 64300e3292..ac63266ead 100644 --- a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi @@ -339,7 +339,7 @@ mcu_r5fss0: r5fss@41000000 { compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; + ti,cluster-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x41000000 0x00 0x41000000 0x20000>, @@ -347,7 +347,7 @@ power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j721s2-r5f"; + compatible = "ti,j721s2-mcu-r5f"; reg = <0x41000000 0x00010000>, <0x41010000 0x00010000>; reg-names = "atcm", "btcm"; @@ -362,7 +362,7 @@ }; mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j721s2-r5f"; + compatible = "ti,j721s2-mcu-r5f"; reg = <0x41400000 0x00010000>, <0x41410000 0x00010000>; reg-names = "atcm", "btcm"; @@ -415,4 +415,17 @@ #size-cells = <0>; }; }; + mcu_esm: esm@40800000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x40800000 0x00 0x1000>; + ti,esm-pins = <95>; + bootph-pre-ram; + }; + + wkup_esm: esm@42080000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x42080000 0x00 0x1000>; + ti,esm-pins = <63>; + bootph-pre-ram; + }; }; diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts index 79ab4dc5c8..c38deb49a4 100644 --- a/arch/arm/dts/k3-j784s4-r5-evm.dts +++ b/arch/arm/dts/k3-j784s4-r5-evm.dts @@ -107,6 +107,22 @@ }; }; +&wkup_pmx2 { + bootph-pre-ram; + wkup_gpio_pins_default: wkup_gpio_pins_default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 7) /* (L37) WKUP_GPIO0_6 */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + bootph-pre-ram; + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; +}; &sms { mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; @@ -171,11 +187,20 @@ maximum-speed = "super-speed"; }; +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; + &ospi0 { reg = <0x0 0x47040000 0x0 0x100>, <0x0 0x50000000 0x0 0x8000000>; }; +&ospi0_nand { + status = "okay"; +}; + &ospi1 { reg = <0x0 0x47050000 0x0 0x100>, <0x0 0x58000000 0x0 0x8000000>; @@ -188,3 +213,34 @@ &mcu_udmap { ti,sci = <&dm_tifs>; }; + +&wkup_i2c0 { + bootph-pre-ram; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + tps659413: tps659413@48 { + compatible = "ti,tps659413"; + reg = <0x48>; + bootph-pre-ram; + + regulators: regulators { + bootph-pre-ram; + buck12_reg: buck12 { + /*VDD_DDR_1V1*/ + regulator-name = "buck12"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + bootph-pre-ram; + }; + }; + + esm: esm { + compatible = "ti,tps659413-esm"; + bootph-pre-ram; + }; + }; +}; diff --git a/arch/arm/dts/k3-j784s4.dtsi b/arch/arm/dts/k3-j784s4.dtsi index 3eb0d05689..2aa064a955 100644 --- a/arch/arm/dts/k3-j784s4.dtsi +++ b/arch/arm/dts/k3-j784s4.dtsi @@ -232,6 +232,7 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ diff --git a/arch/arm/dts/k3-pinctrl.h b/arch/arm/dts/k3-pinctrl.h new file mode 100644 index 0000000000..2a4e0e084d --- /dev/null +++ b/arch/arm/dts/k3-pinctrl.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for pinctrl bindings for TI's K3 SoC + * family. + * + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ +#ifndef DTS_ARM64_TI_K3_PINCTRL_H +#define DTS_ARM64_TI_K3_PINCTRL_H + +#define PULLUDEN_SHIFT (16) +#define PULLTYPESEL_SHIFT (17) +#define RXACTIVE_SHIFT (18) +#define DEBOUNCE_SHIFT (11) + +#define PULL_DISABLE (1 << PULLUDEN_SHIFT) +#define PULL_ENABLE (0 << PULLUDEN_SHIFT) + +#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) +#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) + +#define INPUT_EN (1 << RXACTIVE_SHIFT) +#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) + +/* Only these macros are expected be used directly in device tree files */ +#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) + +#define PIN_DEBOUNCE_DISABLE (0 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF1 (1 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF2 (2 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF3 (3 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF4 (4 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) + +#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#endif diff --git a/arch/arm/dts/k3-security.h b/arch/arm/dts/k3-security.h new file mode 100644 index 0000000000..33609caa8f --- /dev/null +++ b/arch/arm/dts/k3-security.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef DTS_ARM64_TI_K3_FIREWALL_H +#define DTS_ARM64_TI_K3_FIREWALL_H + +#define FWPRIVID_ALL 0xc3 +#define FWPRIVID_ARMV8 1 +#define FWPRIVID_SHIFT 16 + +#define FWCTRL_EN 0xA +#define FWCTRL_LOCK (1 << 4) +#define FWCTRL_BG (1 << 8) +#define FWCTRL_CACHE (1 << 9) + +#define FWPERM_SECURE_PRIV_WRITE (1 << 0) +#define FWPERM_SECURE_PRIV_READ (1 << 1) +#define FWPERM_SECURE_PRIV_CACHEABLE (1 << 2) +#define FWPERM_SECURE_PRIV_DEBUG (1 << 3) + +#define FWPERM_SECURE_PRIV_RWCD (FWPERM_SECURE_PRIV_READ | \ + FWPERM_SECURE_PRIV_WRITE | \ + FWPERM_SECURE_PRIV_CACHEABLE | \ + FWPERM_SECURE_PRIV_DEBUG) + +#define FWPERM_SECURE_USER_WRITE (1 << 4) +#define FWPERM_SECURE_USER_READ (1 << 5) +#define FWPERM_SECURE_USER_CACHEABLE (1 << 6) +#define FWPERM_SECURE_USER_DEBUG (1 << 7) + +#define FWPERM_SECURE_USER_RWCD (FWPERM_SECURE_USER_READ | \ + FWPERM_SECURE_USER_WRITE | \ + FWPERM_SECURE_USER_CACHEABLE | \ + FWPERM_SECURE_USER_DEBUG) + +#define FWPERM_NON_SECURE_PRIV_WRITE (1 << 8) +#define FWPERM_NON_SECURE_PRIV_READ (1 << 9) +#define FWPERM_NON_SECURE_PRIV_CACHEABLE (1 << 10) +#define FWPERM_NON_SECURE_PRIV_DEBUG (1 << 11) + +#define FWPERM_NON_SECURE_PRIV_RWCD (FWPERM_NON_SECURE_PRIV_READ | \ + FWPERM_NON_SECURE_PRIV_WRITE | \ + FWPERM_NON_SECURE_PRIV_CACHEABLE | \ + FWPERM_NON_SECURE_PRIV_DEBUG) + +#define FWPERM_NON_SECURE_USER_WRITE (1 << 12) +#define FWPERM_NON_SECURE_USER_READ (1 << 13) +#define FWPERM_NON_SECURE_USER_CACHEABLE (1 << 14) +#define FWPERM_NON_SECURE_USER_DEBUG (1 << 15) + +#define FWPERM_NON_SECURE_USER_RWCD (FWPERM_NON_SECURE_USER_READ | \ + FWPERM_NON_SECURE_USER_WRITE | \ + FWPERM_NON_SECURE_USER_CACHEABLE | \ + FWPERM_NON_SECURE_USER_DEBUG) + +#endif diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 1fe0ab318a..2a946efcb6 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -25,6 +25,9 @@ config SOC_K3_AM62A7 config SOC_K3_J784S4 bool "TI's K3 based J784S4 SoC Family Support" +config SOC_K3_AM62P5 + bool "TI's K3 based AM62P5 SoC Family Support" + endchoice config SYS_SOC @@ -32,7 +35,7 @@ config SYS_SOC config SYS_K3_NON_SECURE_MSRAM_SIZE hex - default 0x80000 if SOC_K3_AM654 + default 0x80000 if SOC_K3_AM654 || SOC_K3_AM62P5 default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 default 0x1c0000 if SOC_K3_AM642 default 0x3c000 if SOC_K3_AM625 || SOC_K3_AM62A7 @@ -77,6 +80,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX default 0x43c3f290 if SOC_K3_AM625 default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R default 0x7000f290 if SOC_K3_AM62A7 && ARM64 + default 0x43c4f290 if SOC_K3_AM62P5 help Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media. @@ -176,7 +180,7 @@ config K3_ATF_LOAD_ADDR config K3_DM_FW bool "Separate DM firmware image" - depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_J784S4) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on SPL && CPU_V7R && !SOC_K3_AM642 && !SOC_K3_AM654 && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM @@ -195,6 +199,7 @@ source "board/ti/am65x/Kconfig" source "board/ti/am64x/Kconfig" source "board/ti/am62x/Kconfig" source "board/ti/am62ax/Kconfig" +source "board/ti/am62px/Kconfig" source "board/ti/j721e/Kconfig" source "board/siemens/iot2050/Kconfig" source "board/ti/j721s2/Kconfig" diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index c690616b4c..a6803453cb 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ obj-$(CONFIG_SOC_K3_AM625) += am62x/ obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ obj-$(CONFIG_SOC_K3_J784S4) += j784s4/ +obj-$(CONFIG_SOC_K3_AM62P5) += am62px/ obj-$(CONFIG_ARM64) += arm64-mmu.o obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-$(CONFIG_ARM64) += cache.o @@ -26,6 +27,7 @@ obj-$(CONFIG_SOC_K3_AM642) += am642_init.o obj-$(CONFIG_SOC_K3_AM625) += am625_init.o obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o +obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o endif obj-y += common.o security.o diff --git a/arch/arm/mach-k3/am62p5_init.c b/arch/arm/mach-k3/am62p5_init.c new file mode 100644 index 0000000000..55535a3ff9 --- /dev/null +++ b/arch/arm/mach-k3/am62p5_init.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62P5: SoC specific initialization + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sysfw-loader.h> +#include "common.h" +#include <dm.h> +#include <dm/uclass-internal.h> +#include <dm/pinctrl.h> + +struct fwl_data cbass_main_fwls[] = { + { "FSS_DAT_REG3", 7, 8 }, +}; + +/* + * This uninitialized global variable would normal end up in the .bss section, + * but the .bss is cleared between writing and reading this variable, so move + * it to the .data section. + */ +u32 bootindex __section(".data"); +static struct rom_extended_boot_data bootdata __section(".data"); + +static void store_boot_info_from_rom(void) +{ + bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); + memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO, + sizeof(struct rom_extended_boot_data)); +} + +static void ctrl_mmr_unlock(void) +{ + /* Unlock all WKUP_CTRL_MMR0 module registers */ + mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 4); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 5); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); + + /* Unlock all CTRL_MMR0 module registers */ + mmr_unlock(CTRL_MMR0_BASE, 0); + mmr_unlock(CTRL_MMR0_BASE, 1); + mmr_unlock(CTRL_MMR0_BASE, 2); + mmr_unlock(CTRL_MMR0_BASE, 4); + mmr_unlock(CTRL_MMR0_BASE, 5); + mmr_unlock(CTRL_MMR0_BASE, 6); + + /* Unlock all MCU_CTRL_MMR0 module registers */ + mmr_unlock(MCU_CTRL_MMR0_BASE, 0); + mmr_unlock(MCU_CTRL_MMR0_BASE, 1); + mmr_unlock(MCU_CTRL_MMR0_BASE, 2); + mmr_unlock(MCU_CTRL_MMR0_BASE, 3); + mmr_unlock(MCU_CTRL_MMR0_BASE, 4); + mmr_unlock(MCU_CTRL_MMR0_BASE, 6); + + /* Unlock PADCFG_CTRL_MMR padconf registers */ + mmr_unlock(PADCFG_MMR0_BASE, 1); + mmr_unlock(PADCFG_MMR1_BASE, 1); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + +#if defined(CONFIG_CPU_V7R) + setup_k3_mpu_regions(); +#endif + + /* + * Cannot delay this further as there is a chance that + * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. + */ + store_boot_info_from_rom(); + + ctrl_mmr_unlock(); + + /* Init DM early */ + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed: %d\n", ret); + + /* + * Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and + * MAIN_UART1 modules and continue regardless of the result of pinctrl. + * Do this without probing the device, but instead by searching the + * device that would request the given sequence number if probed. The + * UARTs will be used by the DM firmware and TIFS firmware images + * respectively and the firmware depend on SPL to initialize the pin + * settings. + */ + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + +#ifdef CONFIG_K3_EARLY_CONS + /* + * Allow establishing an early console as required for example when + * doing a UART-based boot. Note that this console may not "survive" + * through a SYSFW PM-init step and will need a re-init in some way + * due to changing module clock frequencies. + */ + ret = early_console_init(); + if (ret) + panic("early_console_init() failed: %d\n", ret); +#endif + +#if defined(CONFIG_K3_LOAD_SYSFW) + /* + * Configure and start up system controller firmware. Provide + * the U-Boot console init function to the SYSFW post-PM configuration + * callback hook, effectively switching on (or over) the console + * output. + */ + ret = is_rom_loaded_sysfw(&bootdata); + if (!ret) + panic("ROM has not loaded TIFS firmware\n"); + + k3_sysfw_loader(true, NULL, NULL); +#endif + + /* + * Force probe of clk_k3 driver here to ensure basic default clock + * configuration is always done. + */ + if (IS_ENABLED(CONFIG_SPL_CLK_K3)) { + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(ti_clk), + &dev); + if (ret) + printf("Failed to initialize clk-k3!\n"); + } + + preloader_console_init(); + + /* Output System Firmware version info */ + k3_sysfw_print_ver(); + + /* Disable ROM configured firewalls right after loading sysfw */ + remove_fwl_configs(cbass_main_fwls, ARRAY_SIZE(cbass_main_fwls)); + +#if defined(CONFIG_K3_AM62A_DDRSS) + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("DRAM init failed: %d\n", ret); +#endif + + debug("am62px_init: %s done\n", __func__); +} + +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_EMMC: + return MMCSD_MODE_EMMCBOOT; + case BOOT_DEVICE_MMC: + if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) + return MMCSD_MODE_RAW; + default: + return MMCSD_MODE_FS; + } +} + +static u32 __get_backup_bootmedia(u32 devstat) +{ + u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_USB; + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 devstat) +{ + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_SPI_NAND: + return BOOT_DEVICE_SPINAND; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + +u32 spl_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmedia; + + if (bootindex == K3_PRIMARY_BOOTMODE) + bootmedia = __get_primary_bootmedia(devstat); + else + bootmedia = __get_backup_bootmedia(devstat); + + debug("am62px_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n", + __func__, devstat, bootmedia, bootindex); + return bootmedia; +} diff --git a/arch/arm/mach-k3/am62px/Makefile b/arch/arm/mach-k3/am62px/Makefile new file mode 100644 index 0000000000..50b0df20a3 --- /dev/null +++ b/arch/arm/mach-k3/am62px/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/am62px/clk-data.c b/arch/arm/mach-k3/am62px/clk-data.c new file mode 100644 index 0000000000..4b9892fe05 --- /dev/null +++ b/arch/arm/mach-k3/am62px/clk-data.c @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62PX specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof <bb@ti.com>. + * + * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <linux/clk-provider.h> +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + NULL, + NULL, + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + NULL, +}; + +static const char * const clk_32k_rc_sel_out0_parents[] = { + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_hfosc0_clkout", + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_lfosc0_clkout", +}; + +static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { + "board_0_ospi0_dqs_out", + "board_0_ospi0_lbclko_out", +}; + +static const char * const main_usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const main_usb1_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const clkout0_ctrl_out0_parents[] = { + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", +}; + +static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_gtcclk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout1_clk", + "postdiv1_16fft_main_1_hsdivout5_clk", +}; + +static const char * const main_timerclkn_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "clk_32k_rc_sel_out0", + "postdiv4_16ff_main_0_hsdivout7_clk", + "gluelogic_rcosc_clkout", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + "board_0_cp_gemac_cpts0_rft_clk_out", + "hsdiv4_16fft_main_1_hsdivout3_clk", + "postdiv4_16ff_main_2_hsdivout6_clk", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +static const char * const wkup_clkout_sel_out0_parents[] = { + NULL, + "gluelogic_lfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "postdiv4_16ff_main_2_hsdivout9_clk", + "clk_32k_rc_sel_out0", + "gluelogic_rcosc_clkout", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clkout_sel_io_out0_parents[] = { + "wkup_clkout_sel_out0", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clksel_out0_parents[] = { + "hsdiv3_16fft_main_15_hsdivout0_clk", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const main_usart0_fclk_sel_out0_parents[] = { + "usart_programmable_clock_divider_out0", + "hsdiv4_16fft_main_1_hsdivout1_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0), + CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0), + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0, 1920000000), + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0), + CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0), + CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x68009c, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0), + CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0), + CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0), + CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0), + CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0), + CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x68108c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), + CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), + CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), + CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), + CLK_MUX("main_timerclkn_sel_out0", main_timerclkn_sel_out0_parents, 16, 0x1081b0, 0, 4, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000), + CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0), + CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0), + CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0), + CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 5, "board_0_ext_refclk1_out"), + DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"), + DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 9, "board_0_ext_refclk1_out"), + DEV_CLK(16, 10, "gluelogic_rcosc_clkout"), + DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(36, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(36, 2, "main_timerclkn_sel_out0"), + DEV_CLK(36, 3, "gluelogic_hfosc0_clkout"), + DEV_CLK(36, 4, "clk_32k_rc_sel_out0"), + DEV_CLK(36, 5, "postdiv4_16ff_main_0_hsdivout7_clk"), + DEV_CLK(36, 6, "gluelogic_rcosc_clkout"), + DEV_CLK(36, 7, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(36, 8, "board_0_ext_refclk1_out"), + DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), + DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), + DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), + DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), + DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), + DEV_CLK(58, 2, "board_0_mmc1_clk_out"), + DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"), + DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(61, 0, "main_gtcclk_sel_out0"), + DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 9, "wkup_clksel_out0"), + DEV_CLK(61, 10, "hsdiv3_16fft_main_15_hsdivout0_clk"), + DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(75, 0, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"), + DEV_CLK(75, 3, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"), + DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"), + DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"), + DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 1, "board_0_i2c0_scl_out"), + DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"), + DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"), + DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 36, "clkout0_ctrl_out0"), + DEV_CLK(157, 37, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 38, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 54, "mshsi2c_main_0_porscl"), + DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 145, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 161, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 163, "dmtimer_dmc1ms_main_0_timer_pwm"), + DEV_CLK(157, 174, "wkup_clkout_sel_io_out0"), + DEV_CLK(157, 175, "wkup_clkout_sel_out0"), + DEV_CLK(157, 176, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"), + DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(161, 10, "board_0_tck_out"), + DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"), + DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(162, 10, "board_0_tck_out"), + DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(170, 2, "board_0_tck_out"), + DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata am62px_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = ARRAY_SIZE(clk_list), + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data), +}; diff --git a/arch/arm/mach-k3/am62px/dev-data.c b/arch/arm/mach-k3/am62px/dev-data.c new file mode 100644 index 0000000000..3cc211ea20 --- /dev/null +++ b/arch/arm/mach-k3/am62px/dev-data.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62PX specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof <bb@ti.com>. + * + * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x00400000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(3, &soc_psc_list[0], &soc_pd_list[0]), + [2] = PSC_PD(4, &soc_psc_list[0], &soc_pd_list[1]), + [3] = PSC_PD(13, &soc_psc_list[0], &soc_pd_list[0]), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), + [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]), + [10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]), + [11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), + [12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), + [13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(16, &soc_lpsc_list[0]), + PSC_DEV(77, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(178, &soc_lpsc_list[1]), + PSC_DEV(179, &soc_lpsc_list[2]), + PSC_DEV(57, &soc_lpsc_list[3]), + PSC_DEV(58, &soc_lpsc_list[4]), + PSC_DEV(161, &soc_lpsc_list[5]), + PSC_DEV(162, &soc_lpsc_list[6]), + PSC_DEV(75, &soc_lpsc_list[7]), + PSC_DEV(36, &soc_lpsc_list[8]), + PSC_DEV(102, &soc_lpsc_list[8]), + PSC_DEV(146, &soc_lpsc_list[8]), + PSC_DEV(166, &soc_lpsc_list[9]), + PSC_DEV(135, &soc_lpsc_list[10]), + PSC_DEV(170, &soc_lpsc_list[11]), + PSC_DEV(177, &soc_lpsc_list[12]), + PSC_DEV(55, &soc_lpsc_list[13]), +}; + +const struct ti_k3_pd_platdata am62px_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = ARRAY_SIZE(soc_psc_list), + .num_pd = ARRAY_SIZE(soc_pd_list), + .num_lpsc = ARRAY_SIZE(soc_lpsc_list), + .num_devs = ARRAY_SIZE(soc_dev_list), +}; diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 077612ff80..811f323ff0 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -351,6 +351,9 @@ static u32 __get_primary_bootmedia(u32 main_devstat) case BOOT_DEVICE_EMMC: return BOOT_DEVICE_MMC1; + case BOOT_DEVICE_NAND: + return BOOT_DEVICE_NAND; + case BOOT_DEVICE_MMC: if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 7f61d1ab00..732a9ede02 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -235,7 +235,7 @@ struct mm_region *mem_map = j721s2_mem_map; #endif /* CONFIG_SOC_K3_J721S2 */ #if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) || \ - defined(CONFIG_SOC_K3_AM62A7) + defined(CONFIG_SOC_K3_AM62A7) || defined(CONFIG_SOC_K3_AM62P5) /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) @@ -275,7 +275,7 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = { }; struct mm_region *mem_map = am64_mem_map; -#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ +#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 || ... */ #if defined(CONFIG_SOC_K3_J784S4) #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 03edbf6e06..3d2595c5a1 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -233,6 +233,31 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) if (ret) panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret); +#if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) && IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) + /* Authenticate ATF */ + void *image_addr = (void *)fit_image_info[IMAGE_ID_ATF].image_start; + + debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__, + fit_image_info[IMAGE_ID_ATF].image_start, + fit_image_info[IMAGE_ID_ATF].image_len, + image_os_match[IMAGE_ID_ATF]); + + ti_secure_image_post_process(&image_addr, + (size_t *)&fit_image_info[IMAGE_ID_ATF].image_len); + + /* Authenticate OPTEE */ + image_addr = (void *)fit_image_info[IMAGE_ID_OPTEE].image_start; + + debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__, + fit_image_info[IMAGE_ID_OPTEE].image_start, + fit_image_info[IMAGE_ID_OPTEE].image_len, + image_os_match[IMAGE_ID_OPTEE]); + + ti_secure_image_post_process(&image_addr, + (size_t *)&fit_image_info[IMAGE_ID_OPTEE].image_len); + +#endif + if (!fit_image_info[IMAGE_ID_DM_FW].image_len && !(size > 0 && valid_elf_image(loadaddr))) { shut_cpu = 1; @@ -311,8 +336,20 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, return; } + /* + * Only DM and the DTBs are being authenticated here, + * rest will be authenticated when A72 cluster is up + */ + if (i != IMAGE_ID_ATF && i != IMAGE_ID_OPTEE) +#endif + { + ti_secure_image_check_binary(p_image, p_size); + ti_secure_image_post_process(p_image, p_size); + } +#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF) + else + ti_secure_image_check_binary(p_image, p_size); #endif - ti_secure_image_post_process(p_image, p_size); } #endif diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 711bd692ae..64a2e49eaa 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -42,3 +42,5 @@ void spl_enable_cache(void); void mmr_unlock(phys_addr_t base, u32 partition); bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data); enum k3_device_type get_device_type(void); +void ti_secure_image_post_process(void **p_image, size_t *p_size); +void ti_secure_image_check_binary(void **p_image, size_t *p_size); diff --git a/arch/arm/mach-k3/include/mach/am62_spl.h b/arch/arm/mach-k3/include/mach/am62_spl.h index e9949b52c1..28235fa08e 100644 --- a/arch/arm/mach-k3/include/mach/am62_spl.h +++ b/arch/arm/mach-k3/include/mach/am62_spl.h @@ -19,6 +19,7 @@ #define BOOT_DEVICE_UART 0x07 #define BOOT_DEVICE_MMC 0x08 #define BOOT_DEVICE_EMMC 0x09 +#define BOOT_DEVICE_SPINAND 0x10 #define BOOT_DEVICE_USB 0x2A #define BOOT_DEVICE_DFU 0x0A @@ -29,7 +30,6 @@ /* U-Boot used aliases */ #define BOOT_DEVICE_ETHERNET 0x04 -#define BOOT_DEVICE_SPINAND 0x07 #define BOOT_DEVICE_MMC2 0x08 #define BOOT_DEVICE_MMC1 0x09 #define BOOT_DEVICE_RAM 0x0F diff --git a/arch/arm/mach-k3/include/mach/am62p_hardware.h b/arch/arm/mach-k3/include/mach/am62p_hardware.h new file mode 100644 index 0000000000..923466c41f --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62p_hardware.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: AM62Px SoC definitions, structures etc. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __ASM_ARCH_AM62P_HARDWARE_H +#define __ASM_ARCH_AM62P_HARDWARE_H + +#include <config.h> +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + +#define PADCFG_MMR0_BASE 0x04080000 +#define PADCFG_MMR1_BASE 0x000f0000 +#define CTRL_MMR0_BASE 0x00100000 +#define MCU_CTRL_MMR0_BASE 0x04500000 +#define WKUP_CTRL_MMR0_BASE 0x43000000 + +#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13 + +/* Primary Bootmode MMC Config macros */ +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4 +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0 + +/* Primary Bootmode USB Config macros */ +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1 +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02 + +/* Backup Bootmode USB Config macros */ +#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 + +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism + * shared register definitions. The same registers are also used for + * PADCFG_MMR lock/kick-mechanism. + */ +#define CTRLMMR_LOCK_KICK0 0x1008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK1 0x100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + +#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038) +#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c) +#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7) + +#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058) +#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3) + +#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c4f1e0 + +#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290 + +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000 + +#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) + +static const u32 put_device_ids[] = {}; + +static const u32 put_core_ids[] = {}; + +#endif + +#endif /* __ASM_ARCH_AM62P_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am62p_spl.h b/arch/arm/mach-k3/include/mach/am62p_spl.h new file mode 100644 index 0000000000..db145a7bc8 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62p_spl.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef _ASM_ARCH_AM62P_SPL_H_ +#define _ASM_ARCH_AM62P_SPL_H_ + +/* Primary BootMode devices */ +#define BOOT_DEVICE_SPI_NAND 0x00 +#define BOOT_DEVICE_RAM 0xFF +#define BOOT_DEVICE_OSPI 0x01 +#define BOOT_DEVICE_QSPI 0x02 +#define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_CPGMAC 0x04 +#define BOOT_DEVICE_ETHERNET_RGMII 0x04 +#define BOOT_DEVICE_ETHERNET_RMII 0x05 +#define BOOT_DEVICE_I2C 0x06 +#define BOOT_DEVICE_UART 0x07 +#define BOOT_DEVICE_MMC 0x08 +#define BOOT_DEVICE_EMMC 0x09 + +#define BOOT_DEVICE_USB 0x2A +#define BOOT_DEVICE_DFU 0x0A +#define BOOT_DEVICE_GPMC_NAND 0x0B +#define BOOT_DEVICE_GPMC_NOR 0x0C +#define BOOT_DEVICE_XSPI 0x0E +#define BOOT_DEVICE_NOBOOT 0x0F + +/* U-Boot used aliases */ +#define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_SPINAND 0x10 +#define BOOT_DEVICE_MMC2 0x08 +#define BOOT_DEVICE_MMC1 0x09 +/* Invalid */ +#define BOOT_DEVICE_MMC2_2 0x1F + +/* Backup BootMode devices */ +#define BACKUP_BOOT_DEVICE_DFU 0x01 +#define BACKUP_BOOT_DEVICE_UART 0x03 +#define BACKUP_BOOT_DEVICE_ETHERNET 0x04 +#define BACKUP_BOOT_DEVICE_MMC 0x05 +#define BACKUP_BOOT_DEVICE_SPI 0x06 +#define BACKUP_BOOT_DEVICE_I2C 0x07 +#define BACKUP_BOOT_DEVICE_USB 0x09 + +#define K3_PRIMARY_BOOTMODE 0x0 + +#endif /* _ASM_ARCH_AM62P_SPL_H_ */ diff --git a/arch/arm/mach-k3/include/mach/am64_spl.h b/arch/arm/mach-k3/include/mach/am64_spl.h index b4f396b2c0..a0a517019c 100644 --- a/arch/arm/mach-k3/include/mach/am64_spl.h +++ b/arch/arm/mach-k3/include/mach/am64_spl.h @@ -22,6 +22,7 @@ #define BOOT_DEVICE_USB 0x2A #define BOOT_DEVICE_DFU 0x0A +#define BOOT_DEVICE_NAND 0x0B #define BOOT_DEVICE_GPMC_NOR 0x0C #define BOOT_DEVICE_PCIE 0x0D #define BOOT_DEVICE_XSPI 0x0E diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 21fd880896..ca53b43962 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -37,6 +37,10 @@ #include "j784s4_hardware.h" #endif +#ifdef CONFIG_SOC_K3_AM62P5 +#include "am62p_hardware.h" +#endif + /* Assuming these addresses and definitions stay common across K3 devices */ #define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14) #define JTAG_ID_VARIANT_SHIFT 28 @@ -51,6 +55,7 @@ #define JTAG_ID_PARTNO_AM62X 0xbb7e #define JTAG_ID_PARTNO_AM62AX 0xbb8d #define JTAG_ID_PARTNO_J784S4 0xbb80 +#define JTAG_ID_PARTNO_AM62PX 0xbb9d #define K3_SOC_ID(id, ID) \ static inline bool soc_is_##id(void) \ @@ -67,6 +72,7 @@ K3_SOC_ID(j721s2, J721S2) K3_SOC_ID(am62x, AM62X) K3_SOC_ID(am62ax, AM62AX) K3_SOC_ID(j784s4, J784S4) +K3_SOC_ID(am62px, AM62PX) #define K3_SEC_MGR_SYS_STATUS 0x44234100 #define SYS_STATUS_DEV_TYPE_SHIFT 0 diff --git a/arch/arm/mach-k3/include/mach/j784s4_spl.h b/arch/arm/mach-k3/include/mach/j784s4_spl.h index 7f6293e628..ec5d3c0e60 100644 --- a/arch/arm/mach-k3/include/mach/j784s4_spl.h +++ b/arch/arm/mach-k3/include/mach/j784s4_spl.h @@ -13,6 +13,7 @@ #define BOOT_DEVICE_QSPI 0x02 #define BOOT_DEVICE_SPI 0x03 #define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_SPINAND 0x05 #define BOOT_DEVICE_I2C 0x06 #define BOOT_DEVICE_UART 0x07 #define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h index 82f57347e6..86e2fc0327 100644 --- a/arch/arm/mach-k3/include/mach/spl.h +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -34,4 +34,8 @@ #include "j784s4_spl.h" #endif +#ifdef CONFIG_SOC_K3_AM62P5 +#include "am62p_spl.h" +#endif + #endif /* _ASM_ARCH_SPL_H_ */ diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 092588f4b5..091c528e23 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -39,19 +39,16 @@ static size_t ti_secure_cert_length(void *p_image) return seq_length + 4; } -void ti_secure_image_post_process(void **p_image, size_t *p_size) +void ti_secure_image_check_binary(void **p_image, size_t *p_size) { - struct ti_sci_handle *ti_sci = get_ti_sci_handle(); - struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops; - size_t cert_length; - u64 image_addr; u32 image_size; - int ret; - + size_t cert_length; image_size = *p_size; - if (!image_size) + if (!image_size) { + debug("%s: Image size is %d\n", __func__, image_size); return; + } if (get_device_type() == K3_DEVICE_TYPE_GP) { if (ti_secure_cert_detected(*p_image)) { @@ -71,6 +68,24 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size) return; } +} + +void ti_secure_image_post_process(void **p_image, size_t *p_size) +{ + struct ti_sci_handle *ti_sci = get_ti_sci_handle(); + struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops; + u64 image_addr; + u32 image_size; + int ret; + + image_size = *p_size; + if (!image_size) { + debug("%s: Image size is %d\n", __func__, image_size); + return; + } + + if (get_device_type() == K3_DEVICE_TYPE_GP) + return; if (get_device_type() != K3_DEVICE_TYPE_HS_SE && !ti_secure_cert_detected(*p_image)) { diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 9ea507a8e9..7d7a88509a 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -194,6 +194,162 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 0x0 }; +static const u32 AM571x_DDR3L_666MHz_TI_AM571x_IDK_emif1_ext_phy_regs[] = { + 0x04040100, /* EMIF1_EXT_PHY_CTRL_1 */ + 0x006B00C0, /* EMIF1_EXT_PHY_CTRL_2 */ + 0x006B00BC, /* EMIF1_EXT_PHY_CTRL_3 */ + 0x006B00C7, /* EMIF1_EXT_PHY_CTRL_4 */ + 0x006B00C3, /* EMIF1_EXT_PHY_CTRL_5 */ + 0x006B00D1, /* EMIF1_EXT_PHY_CTRL_6 */ + 0x002F002F, /* EMIF1_EXT_PHY_CTRL_7 */ + 0x002F002F, /* EMIF1_EXT_PHY_CTRL_8 */ + 0x002F002F, /* EMIF1_EXT_PHY_CTRL_9 */ + 0x002F002F, /* EMIF1_EXT_PHY_CTRL_10 */ + 0x002F002F, /* EMIF1_EXT_PHY_CTRL_11 */ + 0x00600071, /* EMIF1_EXT_PHY_CTRL_12 */ + 0x00600075, /* EMIF1_EXT_PHY_CTRL_13 */ + 0x0060007E, /* EMIF1_EXT_PHY_CTRL_14 */ + 0x00600082, /* EMIF1_EXT_PHY_CTRL_15 */ + 0x00600086, /* EMIF1_EXT_PHY_CTRL_16 */ + 0x00400051, /* EMIF1_EXT_PHY_CTRL_17 */ + 0x00400055, /* EMIF1_EXT_PHY_CTRL_18 */ + 0x0040005E, /* EMIF1_EXT_PHY_CTRL_19 */ + 0x00400062, /* EMIF1_EXT_PHY_CTRL_20 */ + 0x00400066, /* EMIF1_EXT_PHY_CTRL_21 */ + 0x00800080, /* EMIF1_EXT_PHY_CTRL_22 */ + 0x00800080, /* EMIF1_EXT_PHY_CTRL_23 */ + 0x40010080, /* EMIF1_EXT_PHY_CTRL_24 */ + 0x08102040, /* EMIF1_EXT_PHY_CTRL_25 */ + 0x000000B0, /* EMIF1_EXT_PHY_CTRL_26 */ + 0x000000AC, /* EMIF1_EXT_PHY_CTRL_27 */ + 0x000000B7, /* EMIF1_EXT_PHY_CTRL_28 */ + 0x000000B3, /* EMIF1_EXT_PHY_CTRL_29 */ + 0x000000C1, /* EMIF1_EXT_PHY_CTRL_30 */ + 0x00000041, /* EMIF1_EXT_PHY_CTRL_31 */ + 0x00000045, /* EMIF1_EXT_PHY_CTRL_32 */ + 0x0000004E, /* EMIF1_EXT_PHY_CTRL_33 */ + 0x00000052, /* EMIF1_EXT_PHY_CTRL_34 */ + 0x00000056, /* EMIF1_EXT_PHY_CTRL_35 */ + 0x00000077 /* EMIF1_EXT_PHY_CTRL_36 */ +}; + +static const u32 AM572x_DDR3L_532MHz_TI_AM572x_EVM_emif1_ext_phy_regs[] = { + 0x04040100, /* EMIF1_EXT_PHY_CTRL_1 */ + 0x006B0081, /* EMIF1_EXT_PHY_CTRL_2 */ + 0x006B0080, /* EMIF1_EXT_PHY_CTRL_3 */ + 0x006B0086, /* EMIF1_EXT_PHY_CTRL_4 */ + 0x006B0084, /* EMIF1_EXT_PHY_CTRL_5 */ + 0x006B006B, /* EMIF1_EXT_PHY_CTRL_6 */ + 0x00320032, /* EMIF1_EXT_PHY_CTRL_7 */ + 0x00320032, /* EMIF1_EXT_PHY_CTRL_8 */ + 0x00320032, /* EMIF1_EXT_PHY_CTRL_9 */ + 0x00320032, /* EMIF1_EXT_PHY_CTRL_10 */ + 0x00320032, /* EMIF1_EXT_PHY_CTRL_11 */ + 0x00600065, /* EMIF1_EXT_PHY_CTRL_12 */ + 0x00600066, /* EMIF1_EXT_PHY_CTRL_13 */ + 0x0060006A, /* EMIF1_EXT_PHY_CTRL_14 */ + 0x0060006C, /* EMIF1_EXT_PHY_CTRL_15 */ + 0x00600060, /* EMIF1_EXT_PHY_CTRL_16 */ + 0x00400045, /* EMIF1_EXT_PHY_CTRL_17 */ + 0x00400046, /* EMIF1_EXT_PHY_CTRL_18 */ + 0x0040004A, /* EMIF1_EXT_PHY_CTRL_19 */ + 0x0040004C, /* EMIF1_EXT_PHY_CTRL_20 */ + 0x00400040, /* EMIF1_EXT_PHY_CTRL_21 */ + 0x00800080, /* EMIF1_EXT_PHY_CTRL_22 */ + 0x00800080, /* EMIF1_EXT_PHY_CTRL_23 */ + 0x40010080, /* EMIF1_EXT_PHY_CTRL_24 */ + 0x08102040, /* EMIF1_EXT_PHY_CTRL_25 */ + 0x00000071, /* EMIF1_EXT_PHY_CTRL_26 */ + 0x00000070, /* EMIF1_EXT_PHY_CTRL_27 */ + 0x00000076, /* EMIF1_EXT_PHY_CTRL_28 */ + 0x00000074, /* EMIF1_EXT_PHY_CTRL_29 */ + 0x00000000, /* EMIF1_EXT_PHY_CTRL_30 */ + 0x00000035, /* EMIF1_EXT_PHY_CTRL_31 */ + 0x00000036, /* EMIF1_EXT_PHY_CTRL_32 */ + 0x0000003A, /* EMIF1_EXT_PHY_CTRL_33 */ + 0x0000003C, /* EMIF1_EXT_PHY_CTRL_34 */ + 0x00000000, /* EMIF1_EXT_PHY_CTRL_35 */ + 0x00000077 /* EMIF1_EXT_PHY_CTRL_36 */ +}; + +static const u32 AM572x_DDR3L_532MHz_TI_AM572x_IDK_emif1_ext_phy_regs[] = { + 0x04040100, /* EMIF1_EXT_PHY_CTRL_1 */ + 0x006B00AF, /* EMIF1_EXT_PHY_CTRL_2 */ + 0x006B00AB, /* EMIF1_EXT_PHY_CTRL_3 */ + 0x006B00B4, /* EMIF1_EXT_PHY_CTRL_4 */ + 0x006B00B1, /* EMIF1_EXT_PHY_CTRL_5 */ + 0x006B00BD, /* EMIF1_EXT_PHY_CTRL_6 */ + 0x00320032, /* EMIF1_EXT_PHY_CTRL_7 */ + 0x00320032, /* EMIF1_EXT_PHY_CTRL_8 */ + 0x00320032, /* EMIF1_EXT_PHY_CTRL_9 */ + 0x00320032, /* EMIF1_EXT_PHY_CTRL_10 */ + 0x00320032, /* EMIF1_EXT_PHY_CTRL_11 */ + 0x0060006E, /* EMIF1_EXT_PHY_CTRL_12 */ + 0x00600071, /* EMIF1_EXT_PHY_CTRL_13 */ + 0x00600078, /* EMIF1_EXT_PHY_CTRL_14 */ + 0x0060007B, /* EMIF1_EXT_PHY_CTRL_15 */ + 0x0060007F, /* EMIF1_EXT_PHY_CTRL_16 */ + 0x0040004E, /* EMIF1_EXT_PHY_CTRL_17 */ + 0x00400051, /* EMIF1_EXT_PHY_CTRL_18 */ + 0x00400058, /* EMIF1_EXT_PHY_CTRL_19 */ + 0x0040005B, /* EMIF1_EXT_PHY_CTRL_20 */ + 0x0040005F, /* EMIF1_EXT_PHY_CTRL_21 */ + 0x00800080, /* EMIF1_EXT_PHY_CTRL_22 */ + 0x00800080, /* EMIF1_EXT_PHY_CTRL_23 */ + 0x40010080, /* EMIF1_EXT_PHY_CTRL_24 */ + 0x08102040, /* EMIF1_EXT_PHY_CTRL_25 */ + 0x0000009F, /* EMIF1_EXT_PHY_CTRL_26 */ + 0x0000009B, /* EMIF1_EXT_PHY_CTRL_27 */ + 0x000000A4, /* EMIF1_EXT_PHY_CTRL_28 */ + 0x000000A1, /* EMIF1_EXT_PHY_CTRL_29 */ + 0x000000AD, /* EMIF1_EXT_PHY_CTRL_30 */ + 0x0000003E, /* EMIF1_EXT_PHY_CTRL_31 */ + 0x00000041, /* EMIF1_EXT_PHY_CTRL_32 */ + 0x00000048, /* EMIF1_EXT_PHY_CTRL_33 */ + 0x0000004B, /* EMIF1_EXT_PHY_CTRL_34 */ + 0x0000004F, /* EMIF1_EXT_PHY_CTRL_35 */ + 0x00000077 /* EMIF1_EXT_PHY_CTRL_36 */ +}; + +static const u32 AM574x_DDR3L_666MHz_TI_AM574x_IDK_emif1_ext_phy_regs[] = { + 0x04040100, /* EMIF1_EXT_PHY_CTRL_1 */ + 0x006B00C0, /* EMIF1_EXT_PHY_CTRL_2 */ + 0x006B00BC, /* EMIF1_EXT_PHY_CTRL_3 */ + 0x006B00C7, /* EMIF1_EXT_PHY_CTRL_4 */ + 0x006B00C3, /* EMIF1_EXT_PHY_CTRL_5 */ + 0x006B00D1, /* EMIF1_EXT_PHY_CTRL_6 */ + 0x002F002F, /* EMIF1_EXT_PHY_CTRL_7 */ + 0x002F002F, /* EMIF1_EXT_PHY_CTRL_8 */ + 0x002F002F, /* EMIF1_EXT_PHY_CTRL_9 */ + 0x002F002F, /* EMIF1_EXT_PHY_CTRL_10 */ + 0x002F002F, /* EMIF1_EXT_PHY_CTRL_11 */ + 0x00600071, /* EMIF1_EXT_PHY_CTRL_12 */ + 0x00600075, /* EMIF1_EXT_PHY_CTRL_13 */ + 0x0060007E, /* EMIF1_EXT_PHY_CTRL_14 */ + 0x00600082, /* EMIF1_EXT_PHY_CTRL_15 */ + 0x00600086, /* EMIF1_EXT_PHY_CTRL_16 */ + 0x00400051, /* EMIF1_EXT_PHY_CTRL_17 */ + 0x00400055, /* EMIF1_EXT_PHY_CTRL_18 */ + 0x0040005E, /* EMIF1_EXT_PHY_CTRL_19 */ + 0x00400062, /* EMIF1_EXT_PHY_CTRL_20 */ + 0x00400066, /* EMIF1_EXT_PHY_CTRL_21 */ + 0x00800080, /* EMIF1_EXT_PHY_CTRL_22 */ + 0x00800080, /* EMIF1_EXT_PHY_CTRL_23 */ + 0x40010080, /* EMIF1_EXT_PHY_CTRL_24 */ + 0x08102040, /* EMIF1_EXT_PHY_CTRL_25 */ + 0x000000B0, /* EMIF1_EXT_PHY_CTRL_26 */ + 0x000000AC, /* EMIF1_EXT_PHY_CTRL_27 */ + 0x000000B7, /* EMIF1_EXT_PHY_CTRL_28 */ + 0x000000B3, /* EMIF1_EXT_PHY_CTRL_29 */ + 0x000000C1, /* EMIF1_EXT_PHY_CTRL_30 */ + 0x00000041, /* EMIF1_EXT_PHY_CTRL_31 */ + 0x00000045, /* EMIF1_EXT_PHY_CTRL_32 */ + 0x0000004E, /* EMIF1_EXT_PHY_CTRL_33 */ + 0x00000052, /* EMIF1_EXT_PHY_CTRL_34 */ + 0x00000056, /* EMIF1_EXT_PHY_CTRL_35 */ + 0x00000077 /* EMIF1_EXT_PHY_CTRL_36 */ +}; + static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .sdram_config_init = 0x61851b32, .sdram_config = 0x61851b32, @@ -257,6 +413,123 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 0x0 }; +static const u32 AM572x_DDR3L_532MHz_TI_AM572x_EVM_emif2_ext_phy_regs[] = { + 0x04040100, /* EMIF2_EXT_PHY_CTRL_1 */ + 0x006B0084, /* EMIF2_EXT_PHY_CTRL_2 */ + 0x006B0087, /* EMIF2_EXT_PHY_CTRL_3 */ + 0x006B007F, /* EMIF2_EXT_PHY_CTRL_4 */ + 0x006B0080, /* EMIF2_EXT_PHY_CTRL_5 */ + 0x006B006B, /* EMIF2_EXT_PHY_CTRL_6 */ + 0x00320032, /* EMIF2_EXT_PHY_CTRL_7 */ + 0x00320032, /* EMIF2_EXT_PHY_CTRL_8 */ + 0x00320032, /* EMIF2_EXT_PHY_CTRL_9 */ + 0x00320032, /* EMIF2_EXT_PHY_CTRL_10 */ + 0x00320032, /* EMIF2_EXT_PHY_CTRL_11 */ + 0x0060006A, /* EMIF2_EXT_PHY_CTRL_12 */ + 0x00600067, /* EMIF2_EXT_PHY_CTRL_13 */ + 0x00600065, /* EMIF2_EXT_PHY_CTRL_14 */ + 0x00600064, /* EMIF2_EXT_PHY_CTRL_15 */ + 0x00600060, /* EMIF2_EXT_PHY_CTRL_16 */ + 0x0040004A, /* EMIF2_EXT_PHY_CTRL_17 */ + 0x00400047, /* EMIF2_EXT_PHY_CTRL_18 */ + 0x00400045, /* EMIF2_EXT_PHY_CTRL_19 */ + 0x00400044, /* EMIF2_EXT_PHY_CTRL_20 */ + 0x00400040, /* EMIF2_EXT_PHY_CTRL_21 */ + 0x00800080, /* EMIF2_EXT_PHY_CTRL_22 */ + 0x00800080, /* EMIF2_EXT_PHY_CTRL_23 */ + 0x40010080, /* EMIF2_EXT_PHY_CTRL_24 */ + 0x08102040, /* EMIF2_EXT_PHY_CTRL_25 */ + 0x00000074, /* EMIF2_EXT_PHY_CTRL_26 */ + 0x00000077, /* EMIF2_EXT_PHY_CTRL_27 */ + 0x0000006F, /* EMIF2_EXT_PHY_CTRL_28 */ + 0x00000070, /* EMIF2_EXT_PHY_CTRL_29 */ + 0x00000000, /* EMIF2_EXT_PHY_CTRL_30 */ + 0x0000003A, /* EMIF2_EXT_PHY_CTRL_31 */ + 0x00000037, /* EMIF2_EXT_PHY_CTRL_32 */ + 0x00000035, /* EMIF2_EXT_PHY_CTRL_33 */ + 0x00000034, /* EMIF2_EXT_PHY_CTRL_34 */ + 0x00000000, /* EMIF2_EXT_PHY_CTRL_35 */ + 0x00000077 /* EMIF2_EXT_PHY_CTRL_36 */ +}; + +static const u32 AM572x_DDR3L_532MHz_TI_AM572x_IDK_emif2_ext_phy_regs[] = { + 0x04040100, /* EMIF2_EXT_PHY_CTRL_1 */ + 0x006B00AB, /* EMIF2_EXT_PHY_CTRL_2 */ + 0x006B00AB, /* EMIF2_EXT_PHY_CTRL_3 */ + 0x006B00B4, /* EMIF2_EXT_PHY_CTRL_4 */ + 0x006B00B2, /* EMIF2_EXT_PHY_CTRL_5 */ + 0x006B006B, /* EMIF2_EXT_PHY_CTRL_6 */ + 0x00320032, /* EMIF2_EXT_PHY_CTRL_7 */ + 0x00320032, /* EMIF2_EXT_PHY_CTRL_8 */ + 0x00320032, /* EMIF2_EXT_PHY_CTRL_9 */ + 0x00320032, /* EMIF2_EXT_PHY_CTRL_10 */ + 0x00320032, /* EMIF2_EXT_PHY_CTRL_11 */ + 0x00600073, /* EMIF2_EXT_PHY_CTRL_12 */ + 0x00600074, /* EMIF2_EXT_PHY_CTRL_13 */ + 0x00600078, /* EMIF2_EXT_PHY_CTRL_14 */ + 0x0060007A, /* EMIF2_EXT_PHY_CTRL_15 */ + 0x00600060, /* EMIF2_EXT_PHY_CTRL_16 */ + 0x00400053, /* EMIF2_EXT_PHY_CTRL_17 */ + 0x00400054, /* EMIF2_EXT_PHY_CTRL_18 */ + 0x00400058, /* EMIF2_EXT_PHY_CTRL_19 */ + 0x0040005A, /* EMIF2_EXT_PHY_CTRL_20 */ + 0x00400040, /* EMIF2_EXT_PHY_CTRL_21 */ + 0x00800080, /* EMIF2_EXT_PHY_CTRL_22 */ + 0x00800080, /* EMIF2_EXT_PHY_CTRL_23 */ + 0x40010080, /* EMIF2_EXT_PHY_CTRL_24 */ + 0x08102040, /* EMIF2_EXT_PHY_CTRL_25 */ + 0x0000009B, /* EMIF2_EXT_PHY_CTRL_26 */ + 0x0000009B, /* EMIF2_EXT_PHY_CTRL_27 */ + 0x000000A4, /* EMIF2_EXT_PHY_CTRL_28 */ + 0x000000A2, /* EMIF2_EXT_PHY_CTRL_29 */ + 0x00000000, /* EMIF2_EXT_PHY_CTRL_30 */ + 0x00000043, /* EMIF2_EXT_PHY_CTRL_31 */ + 0x00000044, /* EMIF2_EXT_PHY_CTRL_32 */ + 0x00000048, /* EMIF2_EXT_PHY_CTRL_33 */ + 0x0000004A, /* EMIF2_EXT_PHY_CTRL_34 */ + 0x00000000, /* EMIF2_EXT_PHY_CTRL_35 */ + 0x00000077 /* EMIF2_EXT_PHY_CTRL_36 */ +}; + +static const u32 AM574x_DDR3L_666MHz_TI_AM574x_IDK_emif2_ext_phy_regs[] = { + 0x04040100, /* EMIF2_EXT_PHY_CTRL_1 */ + 0x006B00BC, /* EMIF2_EXT_PHY_CTRL_2 */ + 0x006B00BB, /* EMIF2_EXT_PHY_CTRL_3 */ + 0x006B00C7, /* EMIF2_EXT_PHY_CTRL_4 */ + 0x006B00C4, /* EMIF2_EXT_PHY_CTRL_5 */ + 0x006B006B, /* EMIF2_EXT_PHY_CTRL_6 */ + 0x002F002F, /* EMIF2_EXT_PHY_CTRL_7 */ + 0x002F002F, /* EMIF2_EXT_PHY_CTRL_8 */ + 0x002F002F, /* EMIF2_EXT_PHY_CTRL_9 */ + 0x002F002F, /* EMIF2_EXT_PHY_CTRL_10 */ + 0x002F002F, /* EMIF2_EXT_PHY_CTRL_11 */ + 0x00600078, /* EMIF2_EXT_PHY_CTRL_12 */ + 0x00600079, /* EMIF2_EXT_PHY_CTRL_13 */ + 0x0060007E, /* EMIF2_EXT_PHY_CTRL_14 */ + 0x00600081, /* EMIF2_EXT_PHY_CTRL_15 */ + 0x00600060, /* EMIF2_EXT_PHY_CTRL_16 */ + 0x00400058, /* EMIF2_EXT_PHY_CTRL_17 */ + 0x00400059, /* EMIF2_EXT_PHY_CTRL_18 */ + 0x0040005E, /* EMIF2_EXT_PHY_CTRL_19 */ + 0x00400061, /* EMIF2_EXT_PHY_CTRL_20 */ + 0x00400040, /* EMIF2_EXT_PHY_CTRL_21 */ + 0x00800080, /* EMIF2_EXT_PHY_CTRL_22 */ + 0x00800080, /* EMIF2_EXT_PHY_CTRL_23 */ + 0x40010080, /* EMIF2_EXT_PHY_CTRL_24 */ + 0x08102040, /* EMIF2_EXT_PHY_CTRL_25 */ + 0x000000AC, /* EMIF2_EXT_PHY_CTRL_26 */ + 0x000000AB, /* EMIF2_EXT_PHY_CTRL_27 */ + 0x000000B7, /* EMIF2_EXT_PHY_CTRL_28 */ + 0x000000B4, /* EMIF2_EXT_PHY_CTRL_29 */ + 0x00000000, /* EMIF2_EXT_PHY_CTRL_30 */ + 0x00000048, /* EMIF2_EXT_PHY_CTRL_31 */ + 0x00000049, /* EMIF2_EXT_PHY_CTRL_32 */ + 0x0000004E, /* EMIF2_EXT_PHY_CTRL_33 */ + 0x00000051, /* EMIF2_EXT_PHY_CTRL_34 */ + 0x00000000, /* EMIF2_EXT_PHY_CTRL_35 */ + 0x00000077 /* EMIF2_EXT_PHY_CTRL_36 */ +}; + static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .sdram_config_init = 0x61863332, .sdram_config = 0x61863332, @@ -334,12 +607,44 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) { switch (emif_nr) { case 1: - *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; - *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); + if (board_is_am572x_evm()) { + *regs = AM572x_DDR3L_532MHz_TI_AM572x_EVM_emif1_ext_phy_regs; + *size = ARRAY_SIZE + (AM572x_DDR3L_532MHz_TI_AM572x_EVM_emif1_ext_phy_regs); + } else if (board_is_am574x_idk()) { + *regs = AM574x_DDR3L_666MHz_TI_AM574x_IDK_emif1_ext_phy_regs; + *size = ARRAY_SIZE + (AM574x_DDR3L_666MHz_TI_AM574x_IDK_emif1_ext_phy_regs); + } else if (board_is_am572x_idk()) { + *regs = AM572x_DDR3L_532MHz_TI_AM572x_IDK_emif1_ext_phy_regs; + *size = ARRAY_SIZE + (AM572x_DDR3L_532MHz_TI_AM572x_IDK_emif1_ext_phy_regs); + } else if (board_is_am571x_idk()) { + *regs = AM571x_DDR3L_666MHz_TI_AM571x_IDK_emif1_ext_phy_regs; + *size = ARRAY_SIZE + (AM571x_DDR3L_666MHz_TI_AM571x_IDK_emif1_ext_phy_regs); + } else { + *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; + *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); + } break; case 2: - *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; - *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); + if (board_is_am572x_evm()) { + *regs = AM572x_DDR3L_532MHz_TI_AM572x_EVM_emif2_ext_phy_regs; + *size = ARRAY_SIZE + (AM572x_DDR3L_532MHz_TI_AM572x_EVM_emif2_ext_phy_regs); + } else if (board_is_am574x_idk()) { + *regs = AM574x_DDR3L_666MHz_TI_AM574x_IDK_emif2_ext_phy_regs; + *size = ARRAY_SIZE + (AM574x_DDR3L_666MHz_TI_AM574x_IDK_emif2_ext_phy_regs); + } else if (board_is_am572x_idk()) { + *regs = AM572x_DDR3L_532MHz_TI_AM572x_IDK_emif2_ext_phy_regs; + *size = ARRAY_SIZE + (AM572x_DDR3L_532MHz_TI_AM572x_IDK_emif2_ext_phy_regs); + } else { + *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; + *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); + } break; } } diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c index 9065038756..71fbc9e9c2 100644 --- a/board/ti/am62ax/evm.c +++ b/board/ti/am62ax/evm.c @@ -15,12 +15,17 @@ #include <fdt_support.h> #include <spl.h> +#include "../common/rtc.c" + #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CTRLMMR_USB1_PHY_CTRL 0x43004018 #define CORE_VOLTAGE 0x80000000 int board_init(void) { + if (IS_ENABLED(CONFIG_BOARD_HAS_32K_RTC_CRYSTAL)) + board_rtc_init(); + return 0; } diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml index 0e11bd3e3c..b9f3668c07 100644 --- a/board/ti/am62ax/rm-cfg.yaml +++ b/board/ti/am62ax/rm-cfg.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ # -# Resource management configuration for AM62ax +# Resource management configuration for AM62A # --- @@ -18,234 +18,234 @@ rm-cfg: host_cfg_entries: - #1 host_id: 12 - allowed_atype : 0x2A - allowed_qos : 0xAAAA - allowed_orderid : 0xAAAAAAAA - allowed_priority : 0xAAAA - allowed_sched_priority : 0xAA + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #2 - host_id: 30 - allowed_atype : 0x2A - allowed_qos : 0xAAAA - allowed_orderid : 0xAAAAAAAA - allowed_priority : 0xAAAA - allowed_sched_priority : 0xAA + host_id: 20 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #3 - host_id: 36 - allowed_atype : 0x2A - allowed_qos : 0xAAAA - allowed_orderid : 0xAAAAAAAA - allowed_priority : 0xAAAA - allowed_sched_priority : 0xAA + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #4 - host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #5 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #6 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #7 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #8 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #9 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #10 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #11 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #12 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #13 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #14 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #15 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #16 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #17 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #18 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #19 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #20 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #21 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #22 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #23 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #24 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #25 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #26 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #27 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #28 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #29 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #30 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #31 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #32 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 resasg: subhdr: magic: 0x7B25 - size : 8 - resasg_entries_size: 1032 - reserved : 0 + size: 8 + resasg_entries_size: 1064 + reserved: 0 resasg_entries: - start_resource: 0 @@ -253,896 +253,792 @@ rm-cfg: type: 64 host_id: 12 reserved: 0 - - start_resource: 16 num_resource: 4 type: 64 host_id: 35 reserved: 0 - - start_resource: 16 num_resource: 4 type: 64 host_id: 36 reserved: 0 - - start_resource: 20 num_resource: 22 type: 64 host_id: 30 reserved: 0 - - start_resource: 0 num_resource: 16 type: 192 host_id: 12 reserved: 0 - - start_resource: 34 num_resource: 2 type: 192 host_id: 30 reserved: 0 - - start_resource: 0 - num_resource: 4 + num_resource: 2 type: 320 host_id: 12 reserved: 0 - + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 35 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 36 + reserved: 0 - start_resource: 4 num_resource: 4 type: 320 host_id: 30 reserved: 0 - - start_resource: 0 num_resource: 26 type: 384 host_id: 128 reserved: 0 - - start_resource: 50176 num_resource: 164 type: 1666 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 1 type: 1667 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 18 type: 1677 host_id: 12 reserved: 0 - - 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0 - - start_resource: 12288 num_resource: 128 type: 12813 host_id: 12 reserved: 0 - - start_resource: 3072 num_resource: 6 type: 12828 host_id: 128 reserved: 0 - - start_resource: 3584 num_resource: 6 type: 12829 host_id: 128 reserved: 0 - - start_resource: 4096 num_resource: 6 diff --git a/board/ti/am62px/Kconfig b/board/ti/am62px/Kconfig new file mode 100644 index 0000000000..3ef1ff113a --- /dev/null +++ b/board/ti/am62px/Kconfig @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# + +choice + prompt "TI K3 AM62Px based boards" + optional + +config TARGET_AM62P5_A53_EVM + bool "TI K3 based AM62P5 EVM running on A53" + select ARM64 + select BINMAN + imply BOARD + imply SPL_BOARD + imply TI_I2C_BOARD_DETECT + +config TARGET_AM62P5_R5_EVM + bool "TI K3 based AM62P5 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + +endchoice + +if TARGET_AM62P5_R5_EVM || TARGET_AM62P5_A53_EVM + +config SYS_BOARD + default "am62px" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am62px_evm" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_AM62P5_R5_EVM + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +endif diff --git a/board/ti/am62px/MAINTAINERS b/board/ti/am62px/MAINTAINERS new file mode 100644 index 0000000000..57c86ddbc4 --- /dev/null +++ b/board/ti/am62px/MAINTAINERS @@ -0,0 +1,9 @@ +AM62Px BOARD +M: Vignesh Raghavendra <vigneshr@ti.com> +M: Bryan Brattlof <bb@ti.com> +M: Tom Rini <trini@konsulko.com> +S: Maintained +F: board/ti/am62px/ +F: include/configs/am62p5_evm.h +F: configs/am62px_evm_r5_defconfig +F: configs/am62px_evm_a53_defconfig diff --git a/board/ti/am62px/Makefile b/board/ti/am62px/Makefile new file mode 100644 index 0000000000..921afdff27 --- /dev/null +++ b/board/ti/am62px/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evm.o diff --git a/board/ti/am62px/am62px.env b/board/ti/am62px/am62px.env new file mode 100644 index 0000000000..9ed3ef5f71 --- /dev/null +++ b/board/ti/am62px/am62px.env @@ -0,0 +1,27 @@ +#include <environment/ti/ti_armv7_common.env> +#include <environment/ti/mmc.env> +#include <environment/ti/k3_dfu.env> +#include <environment/ti/ospi_nand.env> +#if CONFIG_CMD_REMOTEPROC +#include <environment/ti/k3_rproc.env> +#endif + +default_device_tree=ti/k3-am62p5-sk.dtb +findfdt= + setenv name_fdt ${default_device_tree}; + setenv fdtfile ${name_fdt} +name_kern=Image +console=ttyS2,115200n8 +args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 + ${mtdparts} +run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr} + +boot=mmc +mmcdev=1 +bootpart=1:2 +bootdir=/boot +rd_spec=- + +#if CONFIG_CMD_ABOOTIMG +#include <environment/ti/mmc_android.env> +#endif diff --git a/board/ti/am62px/board-cfg.yaml b/board/ti/am62px/board-cfg.yaml new file mode 100644 index 0000000000..2a741d8d4f --- /dev/null +++ b/board/ti/am62px/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for AM62Px SoCs +# + +--- +board-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable: 0x5A + main_isolation_hostid: 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor: 0x1 + scaling_profile: 0x1 + disable_main_nav_secure_proxy: 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size: 0x10 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables: 0x00 + trace_src_enables: 0x00 diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c new file mode 100644 index 0000000000..60b5606dea --- /dev/null +++ b/board/ti/am62px/evm.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board specific initialization for AM62Px platforms + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#include <asm/arch/hardware.h> +#include <asm/io.h> +#include <common.h> +#include <dm/uclass.h> +#include <env.h> +#include <fdt_support.h> +#include <spl.h> + +#include "../common/rtc.c" + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_BOARD_HAS_32K_RTC_CRYSTAL)) + board_rtc_init(); + + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/board/ti/am62px/pm-cfg.yaml b/board/ti/am62px/pm-cfg.yaml new file mode 100644 index 0000000000..3ff27ce702 --- /dev/null +++ b/board/ti/am62px/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for AM62Px +# +# +--- +pm-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 diff --git a/board/ti/am62px/rm-cfg.yaml b/board/ti/am62px/rm-cfg.yaml new file mode 100644 index 0000000000..fe76feee0f --- /dev/null +++ b/board/ti/am62px/rm-cfg.yaml @@ -0,0 +1,987 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62P +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #11 + host_id: 0 + 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type: 12810 + host_id: 12 + reserved: 0 + - + start_resource: 12288 + num_resource: 128 + type: 12813 + host_id: 12 + reserved: 0 + - + start_resource: 3072 + num_resource: 6 + type: 12826 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 6 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/ti/am62px/sec-cfg.yaml b/board/ti/am62px/sec-cfg.yaml new file mode 100644 index 0000000000..9a6e52136d --- /dev/null +++ b/board/ti/am62px/sec-cfg.yaml @@ -0,0 +1,378 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security configuration for AM62Px +# +--- +sec-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - #1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - #1 + host_id: 0 + supervisor_host_id: 0 + - #2 + host_id: 0 + supervisor_host_id: 0 + - #3 + host_id: 0 + supervisor_host_id: 0 + - #4 + host_id: 0 + supervisor_host_id: 0 + - #5 + host_id: 0 + supervisor_host_id: 0 + - #6 + host_id: 0 + supervisor_host_id: 0 + - #7 + host_id: 0 + supervisor_host_id: 0 + - #8 + host_id: 0 + supervisor_host_id: 0 + - #9 + host_id: 0 + supervisor_host_id: 0 + - #10 + host_id: 0 + supervisor_host_id: 0 + - #11 + host_id: 0 + supervisor_host_id: 0 + - #12 + host_id: 0 + supervisor_host_id: 0 + - #13 + host_id: 0 + supervisor_host_id: 0 + - #14 + host_id: 0 + supervisor_host_id: 0 + - #15 + host_id: 0 + supervisor_host_id: 0 + - #16 + host_id: 0 + supervisor_host_id: 0 + - #17 + host_id: 0 + supervisor_host_id: 0 + - #18 + host_id: 0 + supervisor_host_id: 0 + - #19 + host_id: 0 + supervisor_host_id: 0 + - #20 + host_id: 0 + supervisor_host_id: 0 + - #21 + host_id: 0 + supervisor_host_id: 0 + - #22 + host_id: 0 + supervisor_host_id: 0 + - #23 + host_id: 0 + supervisor_host_id: 0 + - #24 + host_id: 0 + supervisor_host_id: 0 + - #25 + host_id: 0 + supervisor_host_id: 0 + - #26 + host_id: 0 + supervisor_host_id: 0 + - #27 + host_id: 0 + supervisor_host_id: 0 + - #28 + host_id: 0 + supervisor_host_id: 0 + - #29 + host_id: 0 + supervisor_host_id: 0 + - #30 + host_id: 0 + supervisor_host_id: 0 + - #31 + host_id: 0 + supervisor_host_id: 0 + - #32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + write_host_id: 0 + otp_entry: + - #1 + host_id: 0 + host_perms: 0 + - #2 + host_id: 0 + host_perms: 0 + - #3 + host_id: 0 + host_perms: 0 + - #4 + host_id: 0 + host_perms: 0 + - #5 + host_id: 0 + host_perms: 0 + - #6 + host_id: 0 + host_perms: 0 + - #7 + host_id: 0 + host_perms: 0 + - #8 + host_id: 0 + host_perms: 0 + - #9 + host_id: 0 + host_perms: 0 + - #10 + host_id: 0 + host_perms: 0 + - #11 + host_id: 0 + host_perms: 0 + - #12 + host_id: 0 + host_perms: 0 + - #13 + host_id: 0 + host_perms: 0 + - #14 + host_id: 0 + host_perms: 0 + - #15 + host_id: 0 + host_perms: 0 + - #16 + host_id: 0 + host_perms: 0 + - #17 + host_id: 0 + host_perms: 0 + - #18 + host_id: 0 + host_perms: 0 + - #19 + host_id: 0 + host_perms: 0 + - #20 + host_id: 0 + host_perms: 0 + - #21 + host_id: 0 + host_perms: 0 + - #22 + host_id: 0 + host_perms: 0 + - #23 + host_id: 0 + host_perms: 0 + - #24 + host_id: 0 + host_perms: 0 + - #25 + host_id: 0 + host_perms: 0 + - #26 + host_id: 0 + host_perms: 0 + - #27 + host_id: 0 + host_perms: 0 + - #28 + host_id: 0 + host_perms: 0 + - #29 + host_id: 0 + host_perms: 0 + - #30 + host_id: 0 + host_perms: 0 + - #31 + host_id: 0 + host_perms: 0 + - #32 + host_id: 0 + host_perms: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci: 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size: 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0x5A + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock: 0x5A + allow_wildcard_unlock: 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev: 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender: 0 + handover_to_host_id: 0 + rsvd: [0, 0, 0, 0] diff --git a/board/ti/am62px/tifs-rm-cfg.yaml b/board/ti/am62px/tifs-rm-cfg.yaml new file mode 100644 index 0000000000..a80a275046 --- /dev/null +++ b/board/ti/am62px/tifs-rm-cfg.yaml @@ -0,0 +1,879 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62P +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 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-0,0 +1,25 @@ +#include <board/ti/am62x/am62x.env> + +/* Android partitions + * note that += is needed because \n is converted by space in .env files */ +partitions= + name=bootloader,start=5M,size=8M,uuid=${uuid_gpt_bootloader}; +partitions+=name=misc,start=13824K,size=512K,uuid=${uuid_gpt_misc}; +partitions+=name=boot_a,size=40M,uuid=${uuid_gpt_boot_a}; +partitions+=name=boot_b,size=40M,uuid=${uuid_gpt_boot_b}; +partitions+=name=vendor_boot_a,size=32M,uuid=${uuid_gpt_vendor_boot_a}; +partitions+=name=vendor_boot_b,size=32M,uuid=${uuid_gpt_vendor_boot_b}; +partitions+=name=init_boot_a,size=8M,uuid=${uuid_gpt_init_boot_a}; +partitions+=name=init_boot_b,size=8M,uuid=${uuid_gpt_init_boot_b}; +partitions+=name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a}; +partitions+=name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b}; +partitions+=name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a}; +partitions+=name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b}; +partitions+=name=super,size=4608M,uuid=${uuid_gpt_super}; +partitions+=name=metadata,size=16M,uuid=${uuid_gpt_metadata}; +partitions+=name=persist,size=32M,uuid=${uuid_gpt_persist}; +partitions+=name=userdata,size=-,uuid=${uuid_gpt_userdata} + +/* fastboot variables */ +fastboot_raw_partition_tiboot3="0x0 0x800 mmcpart 1" +fastboot_raw_partition_bootenv="0x800 0x400 mmcpart 1" diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env index f02327d2e8..e507ca276c 100644 --- a/board/ti/am62x/am62x.env +++ b/board/ti/am62x/am62x.env @@ -12,6 +12,10 @@ findfdt= setenv name_fdt ${default_device_tree}; if test $board_name = am62x_skevm; then setenv name_fdt ti/k3-am625-sk.dtb; fi; + if test $board_name = am62b_p1_skevm; then + setenv name_fdt ti/k3-am625-sk.dtb; fi; + if test $board_name = am62x_sip_skevm; then + setenv name_fdt ti/k3-am625-sk.dtb; fi; if test $board_name = am62x_lp_skevm; then setenv name_fdt ti/k3-am62-lp-sk.dtb; fi; if test $board_name = am62x_beagleplay; then diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index bee00a7a9e..d84c85b122 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -23,8 +23,12 @@ #include <asm/gpio.h> #include <cpu_func.h> +#include <linux/sizes.h> + #include "../common/board_detect.h" +#include "../common/rtc.c" + DECLARE_GLOBAL_DATA_PTR; #define AM62X_MAX_DAUGHTER_CARDS 8 @@ -44,7 +48,9 @@ static struct gpio_desc board_det_gpios[AM62X_LPSK_BRD_DET_COUNT]; #define board_is_am62x_skevm() (board_ti_k3_is("AM62-SKEVM") || \ board_ti_k3_is("AM62B-SKEVM")) +#define board_is_am62b_p1_skevm() board_ti_k3_is("AM62B-SKEVM-P1") #define board_is_am62x_lp_skevm() board_ti_k3_is("AM62-LP-SKEVM") +#define board_is_am62x_sip_skevm() board_ti_k3_is("AM62SIP-SKEVM") #define board_is_am62x_play() board_ti_k3_is("BEAGLEPLAY-A0-") #if CONFIG_IS_ENABLED(SPLASH_SCREEN) @@ -72,6 +78,9 @@ int splash_screen_prepare(void) int board_init(void) { + if (IS_ENABLED(CONFIG_BOARD_HAS_32K_RTC_CRYSTAL)) + board_rtc_init(); + return 0; } @@ -85,6 +94,16 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } +phys_size_t get_effective_memsize(void) +{ + /* + * Just below 512MB are TF-A and OPTEE reserve regions, thus + * SPL/U-Boot RAM has to start below that. Leave 64MB space for + * all reserved memories. + */ + return gd->ram_size == SZ_512M ? SZ_512M - SZ_64M : gd->ram_size; +} + #if defined(CONFIG_SPL_BUILD) static int video_setup(void) { @@ -108,13 +127,6 @@ static int video_setup(void) #define CTRLMMR_USB1_PHY_CTRL 0x43004018 #define CORE_VOLTAGE 0x80000000 -#define WKUP_CTRLMMR_DBOUNCE_CFG1 0x04504084 -#define WKUP_CTRLMMR_DBOUNCE_CFG2 0x04504088 -#define WKUP_CTRLMMR_DBOUNCE_CFG3 0x0450408c -#define WKUP_CTRLMMR_DBOUNCE_CFG4 0x04504090 -#define WKUP_CTRLMMR_DBOUNCE_CFG5 0x04504094 -#define WKUP_CTRLMMR_DBOUNCE_CFG6 0x04504098 - void spl_board_init(void) { u32 val; @@ -129,29 +141,6 @@ void spl_board_init(void) val &= ~(CORE_VOLTAGE); writel(val, CTRLMMR_USB1_PHY_CTRL); - /* We have 32k crystal, so lets enable it */ - val = readl(MCU_CTRL_LFXOSC_CTRL); - val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL); - writel(val, MCU_CTRL_LFXOSC_CTRL); - /* Add any TRIM needed for the crystal here.. */ - /* Make sure to mux up to take the SoC 32k from the crystal */ - writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, - MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); - - /* Setup debounce conf registers - arbitrary values. Times are approx */ - /* 1.9ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG1, 0x1); - /* 5ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG2, 0x5); - /* 20ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG3, 0x14); - /* 46ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG4, 0x18); - /* 100ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG5, 0x1c); - /* 156ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG6, 0x1f); - video_setup(); enable_caches(); if (IS_ENABLED(CONFIG_SPL_SPLASH_SCREEN) && IS_ENABLED(CONFIG_SPL_BMP)) @@ -253,8 +242,12 @@ static void setup_board_eeprom_env(void) if (board_is_am62x_skevm()) name = "am62x_skevm"; + else if (board_is_am62b_p1_skevm()) + name = "am62b_p1_skevm"; else if (board_is_am62x_lp_skevm()) name = "am62x_lp_skevm"; + else if (board_is_am62x_sip_skevm()) + name = "am62x_sip_skevm"; else if (board_is_am62x_play()) name = "am62x_beagleplay"; else diff --git a/board/ti/am62x/rm-cfg.yaml b/board/ti/am62x/rm-cfg.yaml index 1e8678c30b..c06232f6dd 100644 --- a/board/ti/am62x/rm-cfg.yaml +++ b/board/ti/am62x/rm-cfg.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ # -# Resource management configuration for AM62 +# Resource management configuration for AM62X # --- @@ -18,234 +18,234 @@ rm-cfg: host_cfg_entries: - #1 host_id: 12 - allowed_atype : 0x2A - allowed_qos : 0xAAAA - allowed_orderid : 0xAAAAAAAA - allowed_priority : 0xAAAA - allowed_sched_priority : 0xAA + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #2 host_id: 30 - allowed_atype : 0x2A - allowed_qos : 0xAAAA - allowed_orderid : 0xAAAAAAAA - allowed_priority : 0xAAAA - allowed_sched_priority : 0xAA + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #3 host_id: 36 - allowed_atype : 0x2A - allowed_qos : 0xAAAA - allowed_orderid : 0xAAAAAAAA - allowed_priority : 0xAAAA - allowed_sched_priority : 0xAA + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - #4 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #5 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #6 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #7 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #8 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #9 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #10 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #11 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #12 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #13 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #14 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #15 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #16 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #17 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #18 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #19 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #20 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #21 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #22 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #23 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #24 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #25 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #26 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #27 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #28 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #29 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #30 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #31 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 - #32 host_id: 0 - allowed_atype : 0 - allowed_qos : 0 - allowed_orderid : 0 - allowed_priority : 0 - allowed_sched_priority : 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 resasg: subhdr: magic: 0x7B25 - size : 8 - resasg_entries_size: 960 - reserved : 0 + size: 8 + resasg_entries_size: 976 + reserved: 0 resasg_entries: - start_resource: 0 @@ -253,833 +253,726 @@ rm-cfg: type: 64 host_id: 12 reserved: 0 - - start_resource: 16 num_resource: 4 type: 64 host_id: 35 reserved: 0 - - start_resource: 16 num_resource: 4 type: 64 host_id: 36 reserved: 0 - - start_resource: 20 num_resource: 22 type: 64 host_id: 30 reserved: 0 - - start_resource: 0 num_resource: 16 type: 192 host_id: 12 reserved: 0 - - start_resource: 34 num_resource: 2 type: 192 host_id: 30 reserved: 0 - - start_resource: 0 - num_resource: 4 + num_resource: 2 type: 320 host_id: 12 reserved: 0 - + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 35 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 36 + reserved: 0 - start_resource: 4 num_resource: 4 type: 320 host_id: 30 reserved: 0 - - start_resource: 0 num_resource: 26 type: 384 host_id: 128 reserved: 0 - - start_resource: 50176 num_resource: 164 type: 1666 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 1 type: 1667 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 18 type: 1677 host_id: 12 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1677 host_id: 35 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1677 host_id: 36 reserved: 0 - - start_resource: 24 num_resource: 2 type: 1677 host_id: 30 reserved: 0 - - start_resource: 26 num_resource: 6 type: 1677 host_id: 128 reserved: 0 - - start_resource: 54 num_resource: 18 type: 1678 host_id: 12 reserved: 0 - - start_resource: 72 num_resource: 6 type: 1678 host_id: 35 reserved: 0 - - start_resource: 72 num_resource: 6 type: 1678 host_id: 36 reserved: 0 - - start_resource: 78 num_resource: 2 type: 1678 host_id: 30 reserved: 0 - - start_resource: 80 num_resource: 2 type: 1678 host_id: 128 reserved: 0 - - start_resource: 32 num_resource: 12 type: 1679 host_id: 12 reserved: 0 - - start_resource: 44 num_resource: 6 type: 1679 host_id: 35 reserved: 0 - - start_resource: 44 num_resource: 6 type: 1679 host_id: 36 reserved: 0 - - start_resource: 50 num_resource: 2 type: 1679 host_id: 30 reserved: 0 - - start_resource: 52 num_resource: 2 type: 1679 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 18 type: 1696 host_id: 12 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1696 host_id: 35 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1696 host_id: 36 reserved: 0 - - start_resource: 24 num_resource: 2 type: 1696 host_id: 30 reserved: 0 - - start_resource: 26 num_resource: 6 type: 1696 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 18 type: 1697 host_id: 12 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1697 host_id: 35 reserved: 0 - - start_resource: 18 num_resource: 6 type: 1697 host_id: 36 reserved: 0 - - start_resource: 24 num_resource: 2 type: 1697 host_id: 30 reserved: 0 - - start_resource: 26 num_resource: 2 type: 1697 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 12 type: 1698 host_id: 12 reserved: 0 - - start_resource: 12 num_resource: 6 type: 1698 host_id: 35 reserved: 0 - - start_resource: 12 num_resource: 6 type: 1698 host_id: 36 reserved: 0 - - start_resource: 18 num_resource: 2 type: 1698 host_id: 30 reserved: 0 - - start_resource: 20 num_resource: 2 type: 1698 host_id: 128 reserved: 0 - - start_resource: 5 num_resource: 35 type: 1802 host_id: 12 reserved: 0 - - - start_resource: 44 - num_resource: 36 + start_resource: 45 + num_resource: 35 type: 1802 host_id: 35 reserved: 0 - - - start_resource: 44 - num_resource: 36 + start_resource: 45 + num_resource: 35 type: 1802 host_id: 36 reserved: 0 - - start_resource: 168 num_resource: 8 type: 1802 host_id: 30 reserved: 0 - - - start_resource: 13 + start_resource: 14 num_resource: 512 type: 1805 host_id: 12 reserved: 0 - - - start_resource: 525 + start_resource: 526 num_resource: 256 type: 1805 host_id: 35 reserved: 0 - - - start_resource: 525 + start_resource: 526 num_resource: 256 type: 1805 host_id: 36 reserved: 0 - - - start_resource: 781 + start_resource: 782 num_resource: 128 type: 1805 host_id: 30 reserved: 0 - - - start_resource: 909 - num_resource: 627 + start_resource: 910 + num_resource: 626 type: 1805 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 1024 type: 1807 host_id: 128 reserved: 0 - - start_resource: 4096 num_resource: 29 type: 1808 host_id: 128 reserved: 0 - - start_resource: 4608 num_resource: 99 type: 1809 host_id: 128 reserved: 0 - - start_resource: 5120 num_resource: 24 type: 1810 host_id: 128 reserved: 0 - - start_resource: 5632 num_resource: 51 type: 1811 host_id: 128 reserved: 0 - - start_resource: 6144 num_resource: 51 type: 1812 host_id: 128 reserved: 0 - - start_resource: 6656 num_resource: 51 type: 1813 host_id: 128 reserved: 0 - - start_resource: 8192 num_resource: 32 type: 1814 host_id: 128 reserved: 0 - - start_resource: 8704 num_resource: 32 type: 1815 host_id: 128 reserved: 0 - - start_resource: 9216 num_resource: 32 type: 1816 host_id: 128 reserved: 0 - - start_resource: 9728 num_resource: 22 type: 1817 host_id: 128 reserved: 0 - - start_resource: 10240 num_resource: 22 type: 1818 host_id: 128 reserved: 0 - - start_resource: 10752 num_resource: 22 type: 1819 host_id: 128 reserved: 0 - - start_resource: 11264 num_resource: 28 type: 1820 host_id: 128 reserved: 0 - - start_resource: 11776 num_resource: 28 type: 1821 host_id: 128 reserved: 0 - - start_resource: 12288 num_resource: 28 type: 1822 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 1 type: 1923 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 10 type: 1936 host_id: 12 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1936 host_id: 35 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1936 host_id: 36 reserved: 0 - - start_resource: 13 num_resource: 3 type: 1936 host_id: 30 reserved: 0 - - start_resource: 16 num_resource: 3 type: 1936 host_id: 128 reserved: 0 - - start_resource: 19 num_resource: 64 type: 1937 host_id: 12 reserved: 0 - - start_resource: 19 num_resource: 64 type: 1937 host_id: 36 reserved: 0 - - start_resource: 83 num_resource: 8 type: 1938 host_id: 12 reserved: 0 - - start_resource: 91 num_resource: 8 type: 1939 host_id: 12 reserved: 0 - - start_resource: 99 num_resource: 10 type: 1942 host_id: 12 reserved: 0 - - start_resource: 109 num_resource: 3 type: 1942 host_id: 35 reserved: 0 - - start_resource: 109 num_resource: 3 type: 1942 host_id: 36 reserved: 0 - - start_resource: 112 num_resource: 3 type: 1942 host_id: 30 reserved: 0 - - start_resource: 115 num_resource: 3 type: 1942 host_id: 128 reserved: 0 - - start_resource: 118 num_resource: 16 type: 1943 host_id: 12 reserved: 0 - - start_resource: 118 num_resource: 16 type: 1943 host_id: 36 reserved: 0 - - start_resource: 134 num_resource: 8 type: 1944 host_id: 12 reserved: 0 - - start_resource: 134 num_resource: 8 type: 1945 host_id: 12 reserved: 0 - - start_resource: 142 num_resource: 8 type: 1946 host_id: 12 reserved: 0 - - start_resource: 142 num_resource: 8 type: 1947 host_id: 12 reserved: 0 - - start_resource: 0 num_resource: 10 type: 1955 host_id: 12 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1955 host_id: 35 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1955 host_id: 36 reserved: 0 - - start_resource: 13 num_resource: 3 type: 1955 host_id: 30 reserved: 0 - - start_resource: 16 num_resource: 3 type: 1955 host_id: 128 reserved: 0 - - start_resource: 19 num_resource: 8 type: 1956 host_id: 12 reserved: 0 - - start_resource: 19 num_resource: 8 type: 1956 host_id: 36 reserved: 0 - - start_resource: 27 num_resource: 1 type: 1957 host_id: 12 reserved: 0 - - start_resource: 28 num_resource: 1 type: 1958 host_id: 12 reserved: 0 - - start_resource: 0 num_resource: 10 type: 1961 host_id: 12 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1961 host_id: 35 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1961 host_id: 36 reserved: 0 - - start_resource: 13 num_resource: 3 type: 1961 host_id: 30 reserved: 0 - - start_resource: 16 num_resource: 3 type: 1961 host_id: 128 reserved: 0 - - start_resource: 0 num_resource: 10 type: 1962 host_id: 12 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1962 host_id: 35 reserved: 0 - - start_resource: 10 num_resource: 3 type: 1962 host_id: 36 reserved: 0 - - start_resource: 13 num_resource: 3 type: 1962 host_id: 30 reserved: 0 - - start_resource: 16 num_resource: 3 type: 1962 host_id: 128 reserved: 0 - - start_resource: 19 num_resource: 1 type: 1963 host_id: 12 reserved: 0 - - start_resource: 19 num_resource: 1 type: 1963 host_id: 36 reserved: 0 - - start_resource: 19 num_resource: 16 type: 1964 host_id: 12 reserved: 0 - - start_resource: 19 num_resource: 16 type: 1964 host_id: 36 reserved: 0 - - start_resource: 20 num_resource: 1 type: 1965 host_id: 12 reserved: 0 - - start_resource: 35 num_resource: 8 type: 1966 host_id: 12 reserved: 0 - - start_resource: 21 num_resource: 1 type: 1967 host_id: 12 reserved: 0 - - start_resource: 35 num_resource: 8 type: 1968 host_id: 12 reserved: 0 - - start_resource: 22 num_resource: 1 type: 1969 host_id: 12 reserved: 0 - - start_resource: 43 num_resource: 8 type: 1970 host_id: 12 reserved: 0 - - start_resource: 23 num_resource: 1 type: 1971 host_id: 12 reserved: 0 - - start_resource: 43 num_resource: 8 type: 1972 host_id: 12 reserved: 0 - - start_resource: 0 num_resource: 1 type: 2112 host_id: 128 reserved: 0 - - start_resource: 2 num_resource: 2 diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env index 5958c2ed03..cdb01bb6a1 100644 --- a/board/ti/am64x/am64x.env +++ b/board/ti/am64x/am64x.env @@ -1,6 +1,13 @@ #include <environment/ti/ti_armv7_common.env> #include <environment/ti/mmc.env> #include <environment/ti/k3_dfu_combined.env> +#include <environment/ti/nand.env> +#if CONFIG_CMD_REMOTEPROC +#include <environment/ti/k3_rproc.env> +#endif + +mtdids=nand0=omap2-nand.0 +mtdparts=omap2-nand.0:2m(NAND.tiboot3),2m(NAND.tispl),2m(NAND.tiboot3.backup),4m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup),-(NAND.file-system) findfdt= if test $board_name = am64x_gpevm; then @@ -21,6 +28,8 @@ bootpart=1:2 bootdir=/boot rd_spec=- +rproc_fw_binaries= 0 /lib/firmware/am64-main-r5f0_0-fw 1 /lib/firmware/am64-main-r5f0_1-fw 2 /lib/firmware/am64-main-r5f1_0-fw 3 /lib/firmware/am64-main-r5f1_1-fw + args_usb=run finduuid;setenv bootargs console=${console} ${optargs} root=PARTUUID=${uuid} rw diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index 577bdfd6f4..12b4f26325 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -35,6 +35,10 @@ enum { AM64X_EVM_BRD_DET_COUNT, }; +#define AM642_NAND_DTBO "k3-am642-evm-nand.dtbo" + +static struct gpio_desc board_det_gpios[AM64X_EVM_BRD_DET_COUNT]; + /* Max number of MAC addresses that are parsed/processed per daughter card */ #define DAUGHTER_CARD_NO_OF_MAC_ADDR 8 @@ -67,14 +71,20 @@ int dram_init_banksize(void) return ret; } +static bool is_nand; #if defined(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) { bool eeprom_read = board_ti_was_eeprom_read(); if (!eeprom_read || board_is_am64x_gpevm()) { - if (!strcmp(name, "k3-am642-r5-evm") || !strcmp(name, "k3-am642-evm")) - return 0; + if (is_nand) { + if (!strcmp(name, "k3-am642-r5-evm") || !strcmp(name, "k3-am642-evm-nand")) + return 0; + } else { + if (!strcmp(name, "k3-am642-r5-evm") || !strcmp(name, "k3-am642-evm")) + return 0; + } } else if (board_is_am64x_skevm()) { if (!strcmp(name, "k3-am642-r5-sk") || !strcmp(name, "k3-am642-sk")) return 0; @@ -236,7 +246,6 @@ static void setup_serial(void) #endif #endif -#ifdef CONFIG_BOARD_LATE_INIT static const char *k3_dtbo_list[AM64X_MAX_DAUGHTER_CARDS] = {NULL}; static int init_daughtercard_det_gpio(char *gpio_name, struct gpio_desc *desc) @@ -264,7 +273,6 @@ static int init_daughtercard_det_gpio(char *gpio_name, struct gpio_desc *desc) static int probe_daughtercards(void) { struct ti_am6_eeprom ep; - struct gpio_desc board_det_gpios[AM64X_EVM_BRD_DET_COUNT]; char mac_addr[DAUGHTER_CARD_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN]; u8 mac_addr_cnt; char name_overlays[1024] = { 0 }; @@ -292,7 +300,7 @@ static int probe_daughtercards(void) { AM64X_EVM_HSE_BRD_DET, "TMDS64DC02EVM", - "k3-am642-evm-nand.dtbo", + AM642_NAND_DTBO, 0, }, }; @@ -373,6 +381,9 @@ static int probe_daughtercards(void) dtboname = cards[i].dtbo_name; k3_dtbo_list[nb_dtbos++] = dtboname; + if (!strcmp(dtboname, AM642_NAND_DTBO)) + is_nand = true; + /* * Make sure we are not running out of buffer space by checking * if we can fit the new overlay, a trailing space to be used @@ -396,6 +407,7 @@ static int probe_daughtercards(void) return 0; } +#ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) { @@ -434,5 +446,9 @@ void spl_board_init(void) /* Init DRAM size for R5/A53 SPL */ dram_init_banksize(); + + /* Check for and probe any plugged-in daughtercards */ + if (board_is_am64x_gpevm()) + probe_daughtercards(); } #endif diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index 49edd98014..56a65c0a40 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -1,3 +1,11 @@ +config BOARD_HAS_32K_RTC_CRYSTAL + bool "Enable the 32k crystial for RTC" + help + Some of Texas Instrument's Starter-Kit boards have + an onboard 32k crystal. Select this option if you wish Uboot + to enable this crystal for Linux + default n + config TI_I2C_BOARD_DETECT bool "Support for Board detection for TI platforms" help diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index 9a53884c98..17fe8f8069 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -128,7 +128,7 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, rc = dm_i2c_read(dev, 0x1, &offset_test, sizeof(offset_test)); - if (*((u32 *)ep) != (header & 0xFF)) + if (offset_test != ((header >> 8) & 0xFF)) one_byte_addressing = false; /* Corrupted data??? */ diff --git a/board/ti/common/rtc.c b/board/ti/common/rtc.c new file mode 100644 index 0000000000..e117a92776 --- /dev/null +++ b/board/ti/common/rtc.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RTC setup for TI Platforms + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ +#include <asm/arch/hardware.h> +#include <asm/io.h> +#include <log.h> + +#define WKUP_CTRLMMR_DBOUNCE_CFG1 0x04504084 +#define WKUP_CTRLMMR_DBOUNCE_CFG2 0x04504088 +#define WKUP_CTRLMMR_DBOUNCE_CFG3 0x0450408c +#define WKUP_CTRLMMR_DBOUNCE_CFG4 0x04504090 +#define WKUP_CTRLMMR_DBOUNCE_CFG5 0x04504094 +#define WKUP_CTRLMMR_DBOUNCE_CFG6 0x04504098 + +void board_rtc_init(void) +{ + u32 val; + + /* We have 32k crystal, so lets enable it */ + val = readl(MCU_CTRL_LFXOSC_CTRL); + val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL); + writel(val, MCU_CTRL_LFXOSC_CTRL); + + /* Add any TRIM needed for the crystal here.. */ + /* Make sure to mux up to take the SoC 32k from the crystal */ + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, + MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); + + /* Setup debounce conf registers - arbitrary values. + * Times are approx + */ + /* 1.9ms debounce @ 32k */ + writel(WKUP_CTRLMMR_DBOUNCE_CFG1, 0x1); + /* 5ms debounce @ 32k */ + writel(WKUP_CTRLMMR_DBOUNCE_CFG2, 0x5); + /* 20ms debounce @ 32k */ + writel(WKUP_CTRLMMR_DBOUNCE_CFG3, 0x14); + /* 46ms debounce @ 32k */ + writel(WKUP_CTRLMMR_DBOUNCE_CFG4, 0x18); + /* 100ms debounce @ 32k */ + writel(WKUP_CTRLMMR_DBOUNCE_CFG5, 0x1c); + /* 156ms debounce @ 32k */ + writel(WKUP_CTRLMMR_DBOUNCE_CFG6, 0x1f); +} diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index e82349ef24..d0077cebc4 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -571,10 +571,13 @@ void spl_board_init(void) if (board_ti_k3_is("J721EX-PM2-SOM") || board_ti_k3_is("J7200X-PM2-SOM") || board_is_bboneai_64_b0()) { - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(k3_esm), &dev); + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@700000", &dev); + if (ret) + printf("MISC init for esm@700000 failed: %d\n", ret); + + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@40800000", &dev); if (ret) - printf("ESM init failed: %d\n", ret); + printf("MISC init for esm@40800000 failed: %d\n", ret); } #endif diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index 492e6ae3c7..4f91859c2e 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -68,9 +68,9 @@ main_cpsw0_qsgmii_phyinit= #endif #if CONFIG_TARGET_J721E_A72_EVM -rproc_fw_binaries=2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw +rproc_fw_binaries= 1 /lib/firmware/j7-mcu-r5f0_1-fw 2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw #endif #if CONFIG_TARGET_J7200_A72_EVM -rproc_fw_binaries=2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw +rproc_fw_binaries= 1 /lib/firmware/j7200-mcu-r5f0_1-fw 2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw #endif diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 66d5b219b5..eea2c256b3 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -73,46 +73,41 @@ int dram_init_banksize(void) return 0; } -#if CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(OF_LIBFDT) /* Enables the spi-nand dts node, if onboard mux is set to spinand */ static void __maybe_unused detect_enable_spinand(void *blob) { - struct gpio_desc desc = {0}; - char *ospi_mux_sel_gpio = "6"; - int offset; - - if (dm_gpio_lookup_name(ospi_mux_sel_gpio, &desc)) - return; - - if (dm_gpio_request(&desc, ospi_mux_sel_gpio)) - return; - - if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN)) - return; - - if (dm_gpio_get_value(&desc)) { - offset = fdt_node_offset_by_compatible(blob, -1, "spi-nand"); - fdt_status_okay(blob, offset); - - offset = fdt_first_subnode(blob, - fdt_parent_offset(blob, offset)); - while (offset > 0) { - if (!fdt_node_check_compatible(blob, offset, - "jedec,spi-nor")) - fdt_status_disabled(blob, offset); - - offset = fdt_next_subnode(blob, offset); + if (IS_ENABLED(CONFIG_DM_GPIO) && IS_ENABLED(CONFIG_OF_LIBFDT)) { + struct gpio_desc desc = {0}; + char *ospi_mux_sel_gpio = "6"; + int nand_offset, nor_offset; + + if (dm_gpio_lookup_name(ospi_mux_sel_gpio, &desc)) + return; + + if (dm_gpio_request(&desc, ospi_mux_sel_gpio)) + return; + + if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN)) + return; + + nand_offset = fdt_node_offset_by_compatible(blob, -1, "spi-nand"); + nor_offset = fdt_node_offset_by_compatible(blob, + fdt_parent_offset(blob, nand_offset), + "jedec,spi-nor"); + + if (dm_gpio_get_value(&desc)) { + fdt_status_okay(blob, nand_offset); + fdt_del_node(blob, nor_offset); + } else { + fdt_del_node(blob, nand_offset); } } } -#endif -#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_TARGET_J721S2_A72_EVM) || \ - defined(CONFIG_TARGET_J721S2_R5_EVM)) +#if defined(CONFIG_SPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { - if (IS_ENABLED(CONFIG_DM_GPIO) && IS_ENABLED(CONFIG_OF_LIBFDT)) - detect_enable_spinand(spl_image->fdt_addr); + detect_enable_spinand(spl_image->fdt_addr); } #endif @@ -128,8 +123,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) if (ret) printf("%s: fixing up msmc ram failed %d\n", __func__, ret); - if (IS_ENABLED(CONFIG_DM_GPIO) && IS_ENABLED(CONFIG_OF_LIBFDT)) - detect_enable_spinand(blob); + detect_enable_spinand(blob); return ret; } @@ -381,8 +375,46 @@ int board_late_init(void) return 0; } +ofnode cadence_qspi_get_subnode(struct udevice *dev) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD) && + IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)) { + if (spl_boot_device() == BOOT_DEVICE_SPINAND) + return ofnode_by_compatible(dev_ofnode(dev), "spi-nand"); + } + + return dev_read_first_subnode(dev); +} + void spl_board_init(void) { + struct udevice *dev; + int ret; + + if (IS_ENABLED(CONFIG_ESM_K3)) { + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@700000", + &dev); + if (ret) + printf("MISC init for esm@700000 failed: %d\n", ret); + + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@40800000", + &dev); + if (ret) + printf("MISC init for esm@40800000 failed: %d\n", ret); + + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@42080000", + &dev); + if (ret) + printf("MISC init for esm@42080000 failed: %d\n", ret); + } + + if (IS_ENABLED(CONFIG_ESM_PMIC) && !board_is_am68_sk_som()) { + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(pmic_esm), + &dev); + if (ret) + printf("ESM PMIC init failed: %d\n", ret); + } } /* Support for the various EVM / SK families */ diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env index ef683ae7c6..1366f176fc 100644 --- a/board/ti/j721s2/j721s2.env +++ b/board/ti/j721s2/j721s2.env @@ -35,7 +35,7 @@ name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw #endif rd_spec=- -rproc_fw_binaries= 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw +rproc_fw_binaries= 1 /lib/firmware/j721s2-mcu-r5f0_1-fw 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw mtdids=nor0=47040000.spi.0,nand0=spi-nand0 mtdparts=mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);spi-nand0:512k(ospi_nand.tiboot3),2m(ospi_nand.tispl),4m(ospi_nand.u-boot),256k(ospi_nand.env),256k(ospi_nand.env.backup),98048k@32m(ospi_nand.rootfs),256k@130816k(ospi_nand.phypattern) diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c index a59adaf051..8f8cb4f1cf 100644 --- a/board/ti/j784s4/evm.c +++ b/board/ti/j784s4/evm.c @@ -72,6 +72,44 @@ int dram_init_banksize(void) return 0; } +/* Enables the spi-nand dts node, if onboard mux is set to spinand */ +static void __maybe_unused detect_enable_spinand(void *blob) +{ + if (IS_ENABLED(CONFIG_DM_GPIO) && IS_ENABLED(CONFIG_OF_LIBFDT)) { + struct gpio_desc desc = {0}; + char *ospi_mux_sel_gpio = "6"; + int nand_offset, nor_offset; + + if (dm_gpio_lookup_name(ospi_mux_sel_gpio, &desc)) + return; + + if (dm_gpio_request(&desc, ospi_mux_sel_gpio)) + return; + + if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN)) + return; + + nand_offset = fdt_node_offset_by_compatible(blob, -1, "spi-nand"); + nor_offset = fdt_node_offset_by_compatible(blob, + fdt_parent_offset(blob, nand_offset), + "jedec,spi-nor"); + + if (dm_gpio_get_value(&desc)) { + fdt_status_okay(blob, nand_offset); + fdt_del_node(blob, nor_offset); + } else { + fdt_del_node(blob, nand_offset); + } + } +} + +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + detect_enable_spinand(spl_image->fdt_addr); +} +#endif + #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { @@ -84,6 +122,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) if (ret) printf("%s: fixing up msmc ram failed %d\n", __func__, ret); + detect_enable_spinand(blob); + return ret; } #endif @@ -93,7 +133,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* * Functions specific to EVM and SK designs of J784S4/AM69 family. */ -#define board_is_j784s4_evm() board_ti_k3_is("J784S4-EVM") +#define board_is_j784s4_evm() board_ti_k3_is("J784S4X-EVM") #define board_is_am69_sk() board_ti_k3_is("AM69-SK") @@ -141,7 +181,7 @@ static void setup_board_eeprom_env(void) if (board_is_am69_sk()) name = "am69-sk"; - else + else if (!board_is_j784s4_evm()) printf("Unidentified board claims %s in eeprom header\n", board_ti_get_name()); @@ -198,6 +238,44 @@ int board_late_init(void) return 0; } +ofnode cadence_qspi_get_subnode(struct udevice *dev) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD) && + IS_ENABLED(CONFIG_TARGET_J784S4_R5_EVM)) { + if (spl_boot_device() == BOOT_DEVICE_SPINAND) + return ofnode_by_compatible(dev_ofnode(dev), "spi-nand"); + } + + return dev_read_first_subnode(dev); +} + void spl_board_init(void) { + struct udevice *dev; + int ret; + + if (IS_ENABLED(CONFIG_ESM_K3)) { + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@700000", + &dev); + if (ret) + printf("MISC init for esm@700000 failed: %d\n", ret); + + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@40800000", + &dev); + if (ret) + printf("MISC init for esm@40800000 failed: %d\n", ret); + + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@42080000", + &dev); + if (ret) + printf("MISC init for esm@42080000 failed: %d\n", ret); + } + + if (IS_ENABLED(CONFIG_ESM_PMIC)) { + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(pmic_esm), + &dev); + if (ret) + printf("ESM PMIC init failed: %d\n", ret); + } } diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env index 916f376bea..49772d89ea 100644 --- a/board/ti/j784s4/j784s4.env +++ b/board/ti/j784s4/j784s4.env @@ -2,6 +2,7 @@ #include <environment/ti/mmc.env> #include <environment/ti/ufs.env> #include <environment/ti/k3_dfu.env> +#include <environment/ti/ospi_nand.env> #if CONFIG_CMD_REMOTEPROC #include <environment/ti/k3_rproc.env> @@ -28,9 +29,25 @@ bootpart=1:2 bootdir=/boot rd_spec=- -rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw +#if CONFIG_TARGET_J784S4_A72_EVM +do_main_cpsw0_qsgmii_phyinit=1 +init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17; + gpio clear gpio@22_16 +main_cpsw0_qsgmii_phyinit= + if test $board_name = j784s4; then + do_main_cpsw0_qsgmii_phyinit=1; else + do_main_cpsw0_qsgmii_phyinit=0; fi; + if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && test ${boot} = mmc; then + run init_main_cpsw0_qsgmii_phy; + fi; +#endif + +rproc_fw_binaries= 1 /lib/firmware/j784s4-mcu-r5f0_1-fw 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw splashfile=ti.gz splashimage=0x82000000 splashpos=m,m splashsource=mmc + +mtdids=nor0=47040000.spi.0,nand0=spi-nand0 +mtdparts=mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);spi-nand0:512k(ospi_nand.tiboot3),2m(ospi_nand.tispl),4m(ospi_nand.u-boot),256k(ospi_nand.env),256k(ospi_nand.env.backup),98048k@32m(ospi_nand.rootfs),256k@130816k(ospi_nand.phypattern) diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 28fb98c33a..0df727f714 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -19,6 +19,7 @@ CONFIG_AHCI=y CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_CBSIZE=2048 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board" CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; " diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index d1f676d93e..4136bfda73 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -22,6 +22,7 @@ CONFIG_AHCI=y CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_CBSIZE=2048 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board" CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; " diff --git a/configs/am625_beagleplay_android_a53.config b/configs/am625_beagleplay_android_a53.config new file mode 100644 index 0000000000..5883945a0f --- /dev/null +++ b/configs/am625_beagleplay_android_a53.config @@ -0,0 +1,8 @@ +# Defconfig fragment to apply on top of am62x_evm_a53_defconfig + +CONFIG_ENV_SOURCE_FILE="am625_beagleplay_android" + +# Support emmc booting from mmc0boot0 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y +CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION=0 diff --git a/configs/am625_beagleplay_android_r5.config b/configs/am625_beagleplay_android_r5.config new file mode 100644 index 0000000000..8e66be372c --- /dev/null +++ b/configs/am625_beagleplay_android_r5.config @@ -0,0 +1,7 @@ +# Defconfig fragment to apply on top of: +# am62x_evm_r5_defconfig / am62x_evm_r5_usbdfu_defconfig + +# Support emmc booting from mmc0boot0 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y +CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION=0 diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index 9cb3a17449..45bbffada4 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_K3=y CONFIG_TI_SECURE_DEVICE=y CONFIG_SPL_GPIO=y CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_BOARD_HAS_32K_RTC_CRYSTAL=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index 4395a88a6b..96954a35fa 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -1,135 +1,151 @@ CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_BOARD_HAS_32K_RTC_CRYSTAL=y +CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_SOC_K3_AM654=y -CONFIG_TARGET_AM654_A53_EVM=y +CONFIG_SOC_K3_AM62P5=y +CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 +CONFIG_TARGET_AM62P5_A53_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x680000 +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_ENV_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board" +CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-sk" CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_ENV_OFFSET_REDUND=0x6A0000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -# CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y -CONFIG_OF_BOARD_SETUP=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_fit_${boot}; run get_overlaystring; run run_fit" -CONFIG_LOGLEVEL=7 -CONFIG_CONSOLE_MUX=y +CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80a00000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 +CONFIG_SPL_THERMAL=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 -CONFIG_CMD_ASKENV=y +CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y +CONFIG_CMD_MTD=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_TIME=y -CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs)" +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y CONFIG_DFU_MMC=y +CONFIG_DFU_MTD=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y -CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000 +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 CONFIG_TI_SCI_PROTOCOL=y +CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y +CONFIG_DA8XX_GPIO=y CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_I2C_EEPROM=y +CONFIG_SPL_I2C_EEPROM=y +CONFIG_FS_LOADER=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_SPI_FLASH_MTD=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y CONFIG_PHY_TI_DP83867=y -CONFIG_PHY_FIXED=y -CONFIG_E1000=y -CONFIG_CMD_E1000=y CONFIG_TI_AM65_CPSW_NUSS=y -CONFIG_PCI=y -CONFIG_PCI_KEYSTONE=y -CONFIG_PHY=y -CONFIG_AM654_PHY=y -CONFIG_OMAP_USB2_PHY=y CONFIG_PINCTRL=y -# CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_GENERIC is not set CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_REMOTEPROC_TI_K3_DSP=y CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y @@ -139,19 +155,26 @@ CONFIG_SOC_TI=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y +CONFIG_CADENCE_QSPI_PHY=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_KEYBOARD=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_DWC3_AM62=y +CONFIG_SPL_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0x6162 -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_SPL_DFU=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 diff --git a/configs/am65x_hs_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index d14d07add6..25505167f0 100644 --- a/configs/am65x_hs_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -1,39 +1,45 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_TI_SECURE_DEVICE=y -CONFIG_SYS_MALLOC_F_LEN=0x55000 -CONFIG_SPL_GPIO=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SOC_K3_AM654=y -CONFIG_K3_EARLY_CONS=y -CONFIG_TARGET_AM654_R5_EVM=y +CONFIG_SOC_K3_AM62P5=y +CONFIG_TARGET_AM62P5_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c7effc +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c4a7f0 +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_SF_DEFAULT_MODE=0 CONFIG_ENV_SIZE=0x20000 -CONFIG_DM_GPIO=y +CONFIG_ENV_OFFSET=0x680000 CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" -CONFIG_SPL_TEXT_BASE=0x41c00000 +CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-r5-sk" +CONFIG_SPL_TEXT_BASE=0x43c00000 CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_SIZE_LIMIT=0x3C000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y -CONFIG_USE_BOOTCOMMAND=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x3B000 +CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x41c7effc -CONFIG_SPL_BSS_MAX_SIZE=0xc00 +CONFIG_SPL_BSS_START_ADDR=0x43c4b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y @@ -43,8 +49,8 @@ CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y -CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y @@ -55,14 +61,12 @@ CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SPL_THERMAL=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=64 -CONFIG_CMD_BOOTZ=y -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set @@ -70,54 +74,55 @@ CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FAT=y -CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +# CONFIG_NET is not set CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_CLK_TI_SCI=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y -CONFIG_DA8XX_GPIO=y +# CONFIG_GPIO is not set CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y -CONFIG_K3_AVS0=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_GENERIC is not set CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y -CONFIG_TI_SCI_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_SPL_DM_REGULATOR=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_DM_REGULATOR_GPIO=y -CONFIG_DM_REGULATOR_TPS62360=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y +CONFIG_TI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y @@ -125,10 +130,8 @@ CONFIG_SOC_TI=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y -CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y -CONFIG_SYSRESET_TI_SCI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_OMAP_TIMER=y -CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/configs/am62px_evm_r5_usbdfu_defconfig b/configs/am62px_evm_r5_usbdfu_defconfig new file mode 100644 index 0000000000..bd56b77c12 --- /dev/null +++ b/configs/am62px_evm_r5_usbdfu_defconfig @@ -0,0 +1,137 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SOC_K3_AM62P5=y +CONFIG_TARGET_AM62P5_R5_EVM=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c4a7f0 +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x680000 +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-r5-sk" +CONFIG_SPL_TEXT_BASE=0x43c00000 +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_SIZE_LIMIT=0x3C000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x3B000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c4b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_DMA=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SPL_THERMAL=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MISC=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/configs/am62px_evm_r5_usbmsc_defconfig b/configs/am62px_evm_r5_usbmsc_defconfig new file mode 100644 index 0000000000..a5da903c3c --- /dev/null +++ b/configs/am62px_evm_r5_usbmsc_defconfig @@ -0,0 +1,138 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SOC_K3_AM62P5=y +CONFIG_TARGET_AM62P5_R5_EVM=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c4a7f0 +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x680000 +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-r5-sk" +CONFIG_SPL_TEXT_BASE=0x43c00000 +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_SIZE_LIMIT=0x3C000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x3B000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c4b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_DMA=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SPL_THERMAL=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DFU_RAM=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MISC=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_STORAGE=y +CONFIG_USB_HOST=y +CONFIG_USB_STORAGE=y +CONFIG_SPL_USB_GADGET=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/configs/am62x_android_a53.config b/configs/am62x_android_a53.config index fc949f65d7..1c1406128a 100644 --- a/configs/am62x_android_a53.config +++ b/configs/am62x_android_a53.config @@ -20,7 +20,8 @@ CONFIG_CMD_AVB=y CONFIG_LIBAVB=y # Store env in eMMC for dtbo overlays CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x680000 +CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_NOWHERE=n CONFIG_SYS_MMC_ENV_PART=1 CONFIG_SPL_ENV_IS_NOWHERE=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index cc91adf496..9774efed73 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -4,6 +4,7 @@ CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TI_I2C_BOARD_DETECT=y CONFIG_SPL_GPIO=y +CONFIG_BOARD_HAS_32K_RTC_CRYSTAL=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 @@ -103,7 +104,7 @@ CONFIG_CLK_TI_SCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y -CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y diff --git a/configs/am62xsip_sk_r5.config b/configs/am62xsip_sk_r5.config new file mode 100644 index 0000000000..75acc4cedc --- /dev/null +++ b/configs/am62xsip_sk_r5.config @@ -0,0 +1,5 @@ +# Defconfig fragment to apply on top of am62x_evm_r5_defconfig + +CONFIG_DEFAULT_DEVICE_TREE="k3-am62sip-r5-sk" +CONFIG_SPL_OF_LIST="k3-am62sip-r5-sk" +CONFIG_OF_LIST="k3-am62sip-r5-sk" diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 412e742e60..518af9b820 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -44,7 +44,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ETH=y @@ -74,10 +74,15 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:2m(NAND.tiboot3),2m(NAND.tispl),2m(NAND.tiboot3.backup),4m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup),-(NAND.file-system)" +CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="k3-am642-evm k3-am642-sk" @@ -100,6 +105,8 @@ CONFIG_CLK_TI_SCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_DFU_NAND=y +CONFIG_DFU_NAND_TRIMFFS=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y @@ -120,6 +127,8 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -152,6 +161,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_TPS65219=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y @@ -182,3 +192,31 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ=0x100000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x1000000 +CONFIG_MEMORY=y +CONFIG_SPL_MEMORY=y +CONFIG_TI_GPMC=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_OMAP_GPMC=y +CONFIG_CMD_NAND=y +CONFIG_NAND_OMAP_ELM=y +CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW=y +CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_PAGE_SIZE=0x1000 +CONFIG_SYS_NAND_PAGE_COUNT=0x40 +CONFIG_SYS_NAND_OOBSIZE=0x100 +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_NAND_DRIVERS=y +CONFIG_SPL_NAND_BASE=y +CONFIG_SPL_NAND_IDENT=y +CONFIG_SPL_NAND_ECC=y +CONFIG_SYS_NAND_MAX_CHIPS=1 +CONFIG_SYS_MAX_NAND_DEVICE=1 +# CONFIG_SPL_NAND_AM33XX_BCH is not set +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x600000 diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 10dcaeb42b..222aeb887d 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -51,7 +51,7 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ETH=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index e6556b3e4c..c10b2c34af 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_TI_I2C_BOARD_DETECT=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -27,11 +29,12 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_FIT_SIGNATURE_ENFORCE is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_OF_BOARD_SETUP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" CONFIG_LOGLEVEL=7 CONFIG_CONSOLE_MUX=y CONFIG_SPL_MAX_SIZE=0x58000 @@ -79,11 +82,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 694915d637..fa9c1f2de7 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_F_LEN=0x55000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig index 90ef96f8c6..8fc53795a6 100644 --- a/configs/am65x_evm_r5_usbmsc_defconfig +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -87,6 +87,7 @@ CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_MISC=y +CONFIG_SPL_MISC=y CONFIG_K3_AVS0=y # CONFIG_MMC is not set CONFIG_PHY=y @@ -123,6 +124,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index f740a541f3..fc54456922 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -117,6 +117,8 @@ CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_FS_LOADER=y CONFIG_SPL_FS_LOADER=y +CONFIG_ESM_K3=y +CONFIG_ESM_PMIC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y @@ -150,6 +152,11 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65941=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_TPS65941=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y @@ -182,4 +189,4 @@ CONFIG_FS_EXT4=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_PANIC_HANG=y CONFIG_LIB_RATIONAL=y -CONFIG_SPL_LIB_RATIONAL=y
\ No newline at end of file +CONFIG_SPL_LIB_RATIONAL=y diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 7426befed0..73a47c9074 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_J784S4=y CONFIG_TARGET_J784S4_A72_EVM=y -CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-j784s4-evm" @@ -52,6 +52,9 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD_LOAD=y +CONFIG_SYS_MTD_U_BOOT_OFFS=0x280000 +CONFIG_SPL_NAND_SPI_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y # CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y @@ -93,6 +96,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y @@ -142,6 +146,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y +CONFIG_MTD_SPI_NAND=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 3715f0eca3..2cb5be7da5 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_J784S4=y CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_J784S4_R5_EVM=y -CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-j784s4-r5-evm" @@ -57,6 +57,8 @@ CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD_LOAD=y +CONFIG_SPL_NAND_SPI_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y # CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y @@ -90,6 +92,7 @@ CONFIG_SPL_OF_LIST="k3-j784s4-r5-evm k3-am69-r5-sk" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y @@ -113,6 +116,8 @@ CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_FS_LOADER=y +CONFIG_ESM_K3=y +CONFIG_ESM_PMIC=y CONFIG_SPL_FS_LOADER=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPL_MMC_HS400_SUPPORT=y @@ -127,6 +132,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y +CONFIG_MTD_SPI_NAND=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -144,6 +150,11 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65941=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_TPS65941=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_DM_RESET=y diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 58e4ad2f6f..e9a65e00ee 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -103,6 +103,51 @@ firmware can be loaded on the now free core in the wakeup domain. For more information on the bootup process of your SoC, consult the device specific boot flow documentation. +Secure Boot +^^^^^^^^^^^ + +K3 HS-SE devices are used for authenticated boot flow with secure boot. +HS-FS devices have optional authentication in the flow and doesn't "require" +authentication unless converted to HS-SE devices. + +Chain of trust +"""""""""""""" + +1) SMS starts up and loads the authenticated ROM code in Wakeup Domain +2) ROM code starts up and loads the authenticated tiboot3.bin in Wakeup + Domain +3) Wakeup SPL (tiboot3.bin) would authenticate the next set of binaries + (ATF,OP-TEE,DM,SPL,etc.) +4) After ATF and OP-TEE load, ARMV8 U-boot authenticates the next set of + binaries (Linux and DTBs) if using FIT Image authentication and having a + signature node in U-boot. + +Steps 1-3 are all authenticated by either the ROM code or TIFS as the +authenticating entity and step 4 uses U-boot standard mechanism for +authenticating. + +All the authentication that are done for ROM/TIFS are done through x509 +certificates that are signed. + +Firewalls +""""""""" + +1) ROM comes up and sets up firewalls that are needed by itself +2) TIFS (in multicertificate will setup it's own firewalls) +3) R5 SPL comes along and opens up other firewalls ( that are not owned by + anyone - essentially firewalls that were setup by ROM but are not needed + anymore) +4) Each stage beyond this: such as tispl.bin containing TFA/OPTEE uses OIDs to + set up firewalls to protect themselves (enforced by TIFS) +5) TFA/OP-TEE can configure other firewalls at runtime if required as they + are already authenticated and firewalled off from illegal access. +6) A53 SPL and U-boot itself startups but has no ability to change the + protection firewalls enforced by x509 OIDs or any other firewalls + configured by ROM/TIFS in the beginning. + +Futhur, firewalls have a lockdown bit in hardware that enforces the setting +(and cannot be over-ridden) till the full system is resetted. + Software Sources ---------------- diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c index bf762c558e..c1158c1329 100644 --- a/drivers/clk/ti/clk-k3-pll.c +++ b/drivers/clk/ti/clk-k3-pll.c @@ -25,6 +25,23 @@ #define PLL_16FFT_FREQ_CTRL0 0x30 #define PLL_16FFT_FREQ_CTRL1 0x34 #define PLL_16FFT_DIV_CTRL 0x38 +#define PLL_16FFT_CAL_CTRL 0x60 +#define PLL_16FFT_CAL_STAT 0x64 + +/* CAL STAT register bits */ +#define PLL_16FFT_CAL_STAT_CAL_LOCK BIT(31) + +/* CFG register bits */ +#define PLL_16FFT_CFG_PLL_TYPE_SHIFT (0) +#define PLL_16FFT_CFG_PLL_TYPE_MASK (0x3 << 0) +#define PLL_16FFT_CFG_PLL_TYPE_FRACF 1 + +/* CAL CTRL register bits */ +#define PLL_16FFT_CAL_CTRL_CAL_EN BIT(31) +#define PLL_16FFT_CAL_CTRL_FAST_CAL BIT(20) +#define PLL_16FFT_CAL_CTRL_CAL_BYP BIT(15) +#define PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT 16 +#define PLL_16FFT_CAL_CTRL_CAL_CNT_MASK (0x7 << 16) /* CTRL register bits */ #define PLL_16FFT_CTRL_BYPASS_EN BIT(31) @@ -40,9 +57,14 @@ /* DIV CTRL register bits */ #define PLL_16FFT_DIV_CTRL_REF_DIV_MASK 0x3f -#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24 +/* HSDIV register bits*/ #define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN BIT(15) +/* FREQ_CTRL1 bits */ +#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24 +#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK 0xffffff +#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT 0 + /* KICK register magic values */ #define PLL_KICK0_VALUE 0x68ef3490 #define PLL_KICK1_VALUE 0xd172bc5a @@ -63,18 +85,65 @@ static int ti_pll_wait_for_lock(struct clk *clk) { struct ti_pll_clk *pll = to_clk_pll(clk); u32 stat; + u32 cfg; + u32 cal; + u32 freq_ctrl1; int i; + u32 pllfm; + u32 pll_type; + int success; for (i = 0; i < 100000; i++) { stat = readl(pll->reg + PLL_16FFT_STAT); - if (stat & PLL_16FFT_STAT_LOCK) - return 0; + if (stat & PLL_16FFT_STAT_LOCK) { + success = 1; + break; + } } - printf("%s: pll (%s) failed to lock\n", __func__, - clk->dev->name); + /* Enable calibration if not in fractional mode of the FRACF PLL */ + freq_ctrl1 = readl(pll->reg + PLL_16FFT_FREQ_CTRL1); + pllfm = freq_ctrl1 & PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK; + pllfm >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT; + cfg = readl(pll->reg + PLL_16FFT_CFG); + pll_type = (cfg & PLL_16FFT_CFG_PLL_TYPE_MASK) >> PLL_16FFT_CFG_PLL_TYPE_SHIFT; + + if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF && pllfm == 0) { + cal = readl(pll->reg + PLL_16FFT_CAL_CTRL); - return -EBUSY; + /* Enable calibration for FRACF */ + cal |= PLL_16FFT_CAL_CTRL_CAL_EN; + + /* Enable fast cal mode */ + cal |= PLL_16FFT_CAL_CTRL_FAST_CAL; + + /* Disable calibration bypass */ + cal &= ~PLL_16FFT_CAL_CTRL_CAL_BYP; + + /* Set CALCNT to 2 */ + cal &= ~PLL_16FFT_CAL_CTRL_CAL_CNT_MASK; + cal |= 2 << PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT; + + /* Note this register does not readback the written value. */ + writel(cal, pll->reg + PLL_16FFT_CAL_CTRL); + + success = 0; + for (i = 0; i < 100000; i++) { + stat = readl(pll->reg + PLL_16FFT_CAL_STAT); + if (stat & PLL_16FFT_CAL_STAT_CAL_LOCK) { + success = 1; + break; + } + } + } + + if (success == 0) { + printf("%s: pll (%s) failed to lock\n", __func__, + clk->dev->name); + return -EBUSY; + } else { + return 0; + } } static ulong ti_pll_clk_get_rate(struct clk *clk) diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index 39be0d9c19..81a112e518 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -92,6 +92,12 @@ static const struct soc_attr ti_k3_soc_clk_data[] = { .data = &j784s4_clk_platdata, }, #endif +#ifdef CONFIG_SOC_K3_AM62P5 + { + .family = "AM62PX", + .data = &am62px_clk_platdata, + }, +#endif { /* sentinel */ } }; diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index 9e0b13e8c0..e4732518b3 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -10,3 +10,4 @@ k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o k3-psil-data-$(CONFIG_SOC_K3_AM62A7) += k3-psil-am62a.o k3-psil-data-$(CONFIG_SOC_K3_J784S4) += k3-psil-j784s4.o +k3-psil-data-$(CONFIG_SOC_K3_AM62P5) += k3-psil-am62p.o diff --git a/drivers/dma/ti/k3-psil-am62p.c b/drivers/dma/ti/k3-psil-am62p.c new file mode 100644 index 0000000000..fda27a42bf --- /dev/null +++ b/drivers/dma/ti/k3-psil-am62p.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com + */ + +#include <linux/kernel.h> + +#include "k3-psil-priv.h" + +#define PSIL_PDMA_XY_TR(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .mapped_channel_id = -1, \ + .default_flow_id = -1, \ + }, \ + } + +#define PSIL_PDMA_XY_PKT(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .mapped_channel_id = -1, \ + .default_flow_id = -1, \ + .pkt_mode = 1, \ + }, \ + } + +#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 16, \ + .mapped_channel_id = ch, \ + .flow_start = flow_base, \ + .flow_num = flow_cnt, \ + .default_flow_id = flow_base, \ + }, \ + } + +#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 64, \ + .mapped_channel_id = ch, \ + .flow_start = flow_base, \ + .flow_num = flow_cnt, \ + .default_flow_id = default_flow, \ + .notdpkt = tx, \ + }, \ + } + +#define PSIL_PDMA_MCASP(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .pdma_acc32 = 1, \ + .pdma_burst = 1, \ + }, \ + } + +#define PSIL_CSI2RX(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep am62p_src_ep_map[] = { + /* SAUL */ + PSIL_SAUL(0x7504, 20, 35, 8, 35, 0), + PSIL_SAUL(0x7505, 21, 35, 8, 36, 0), + PSIL_SAUL(0x7506, 22, 43, 8, 43, 0), + PSIL_SAUL(0x7507, 23, 43, 8, 44, 0), + /* PDMA_MAIN0 - SPI0-3 */ + PSIL_PDMA_XY_PKT(0x4302), + PSIL_PDMA_XY_PKT(0x4303), + PSIL_PDMA_XY_PKT(0x4304), + PSIL_PDMA_XY_PKT(0x4305), + PSIL_PDMA_XY_PKT(0x4306), + PSIL_PDMA_XY_PKT(0x4307), + PSIL_PDMA_XY_PKT(0x4308), + PSIL_PDMA_XY_PKT(0x4309), + PSIL_PDMA_XY_PKT(0x430a), + PSIL_PDMA_XY_PKT(0x430b), + PSIL_PDMA_XY_PKT(0x430c), + PSIL_PDMA_XY_PKT(0x430d), + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0x4400), + PSIL_PDMA_XY_PKT(0x4401), + PSIL_PDMA_XY_PKT(0x4402), + PSIL_PDMA_XY_PKT(0x4403), + PSIL_PDMA_XY_PKT(0x4404), + PSIL_PDMA_XY_PKT(0x4405), + PSIL_PDMA_XY_PKT(0x4406), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0x4500), + PSIL_PDMA_MCASP(0x4501), + PSIL_PDMA_MCASP(0x4502), + /* CPSW3G */ + PSIL_ETHERNET(0x4600, 19, 19, 16), + /* CSI2RX */ + PSIL_CSI2RX(0x5000), + PSIL_CSI2RX(0x5001), + PSIL_CSI2RX(0x5002), + PSIL_CSI2RX(0x5003), + PSIL_CSI2RX(0x5004), + PSIL_CSI2RX(0x5005), + PSIL_CSI2RX(0x5006), + PSIL_CSI2RX(0x5007), + PSIL_CSI2RX(0x5008), + PSIL_CSI2RX(0x5009), + PSIL_CSI2RX(0x500a), + PSIL_CSI2RX(0x500b), + PSIL_CSI2RX(0x500c), + PSIL_CSI2RX(0x500d), + PSIL_CSI2RX(0x500e), + PSIL_CSI2RX(0x500f), + PSIL_CSI2RX(0x5010), + PSIL_CSI2RX(0x5011), + PSIL_CSI2RX(0x5012), + PSIL_CSI2RX(0x5013), + PSIL_CSI2RX(0x5014), + PSIL_CSI2RX(0x5015), + PSIL_CSI2RX(0x5016), + PSIL_CSI2RX(0x5017), + PSIL_CSI2RX(0x5018), + PSIL_CSI2RX(0x5019), + PSIL_CSI2RX(0x501a), + PSIL_CSI2RX(0x501b), + PSIL_CSI2RX(0x501c), + PSIL_CSI2RX(0x501d), + PSIL_CSI2RX(0x501e), + PSIL_CSI2RX(0x501f), +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep am62p_dst_ep_map[] = { + /* SAUL */ + PSIL_SAUL(0xf500, 27, 83, 8, 83, 1), + PSIL_SAUL(0xf501, 28, 91, 8, 91, 1), + /* PDMA_MAIN0 - SPI0-3 */ + PSIL_PDMA_XY_PKT(0xc302), + PSIL_PDMA_XY_PKT(0xc303), + PSIL_PDMA_XY_PKT(0xc304), + PSIL_PDMA_XY_PKT(0xc305), + PSIL_PDMA_XY_PKT(0xc306), + PSIL_PDMA_XY_PKT(0xc307), + PSIL_PDMA_XY_PKT(0xc308), + PSIL_PDMA_XY_PKT(0xc309), + PSIL_PDMA_XY_PKT(0xc30a), + PSIL_PDMA_XY_PKT(0xc30b), + PSIL_PDMA_XY_PKT(0xc30c), + PSIL_PDMA_XY_PKT(0xc30d), + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0xc400), + PSIL_PDMA_XY_PKT(0xc401), + PSIL_PDMA_XY_PKT(0xc402), + PSIL_PDMA_XY_PKT(0xc403), + PSIL_PDMA_XY_PKT(0xc404), + PSIL_PDMA_XY_PKT(0xc405), + PSIL_PDMA_XY_PKT(0xc406), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0xc500), + PSIL_PDMA_MCASP(0xc501), + PSIL_PDMA_MCASP(0xc502), + /* CPSW3G */ + PSIL_ETHERNET(0xc600, 19, 19, 8), + PSIL_ETHERNET(0xc601, 20, 27, 8), + PSIL_ETHERNET(0xc602, 21, 35, 8), + PSIL_ETHERNET(0xc603, 22, 43, 8), + PSIL_ETHERNET(0xc604, 23, 51, 8), + PSIL_ETHERNET(0xc605, 24, 59, 8), + PSIL_ETHERNET(0xc606, 25, 67, 8), + PSIL_ETHERNET(0xc607, 26, 75, 8), +}; + +struct psil_ep_map am62p_ep_map = { + .name = "am62p", + .src = am62p_src_ep_map, + .src_count = ARRAY_SIZE(am62p_src_ep_map), + .dst = am62p_dst_ep_map, + .dst_count = ARRAY_SIZE(am62p_dst_ep_map), +}; diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h index 39f1e0150d..aa283d8c58 100644 --- a/drivers/dma/ti/k3-psil-priv.h +++ b/drivers/dma/ti/k3-psil-priv.h @@ -44,5 +44,6 @@ extern struct psil_ep_map am64_ep_map; extern struct psil_ep_map am62_ep_map; extern struct psil_ep_map am62a_ep_map; extern struct psil_ep_map j784s4_ep_map; +extern struct psil_ep_map am62p_ep_map; #endif /* K3_PSIL_PRIV_H_ */ diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c index 7f91154e85..bb0408fc08 100644 --- a/drivers/dma/ti/k3-psil.c +++ b/drivers/dma/ti/k3-psil.c @@ -30,6 +30,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id) soc_ep_map = &am62a_ep_map; else if (IS_ENABLED(CONFIG_SOC_K3_J784S4)) soc_ep_map = &j784s4_ep_map; + else if (IS_ENABLED(CONFIG_SOC_K3_AM62P5)) + soc_ep_map = &am62p_ep_map; } if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) { diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h index a0a41ffcce..00da76a3cb 100644 --- a/drivers/firmware/ti_sci_static_data.h +++ b/drivers/firmware/ti_sci_static_data.h @@ -84,7 +84,8 @@ static struct ti_sci_resource_static_data rm_static_data[] = { }; #endif /* CONFIG_SOC_K3_J721S2 */ -#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) +#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) || \ + IS_ENABLED(CONFIG_SOC_K3_AM62P5) static struct ti_sci_resource_static_data rm_static_data[] = { /* BC channels */ @@ -96,7 +97,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = { }, { }, }; -#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ +#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 || CONFIG_SOC_K3_AM62P5 */ #if IS_ENABLED(CONFIG_SOC_K3_J784S4) static struct ti_sci_resource_static_data rm_static_data[] = { diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 840148d090..dbf79040e0 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -15,6 +15,7 @@ #include <k3-avs.h> #include <dm/device_compat.h> #include <linux/bitops.h> +#include <linux/delay.h> #include <power/regulator.h> #define AM6_VTM_DEVINFO(i) (priv->base + 0x100 + 0x20 * (i)) @@ -25,11 +26,28 @@ #define AM6_VTM_OPP_SHIFT(opp) (8 * (opp)) #define AM6_VTM_OPP_MASK 0xff +#define K3_VTM_DEVINFO_PWR0_OFFSET 0x4 +#define K3_VTM_DEVINFO_PWR0_TEMPSENS_CT_MASK 0xf0 +#define K3_VTM_TMPSENS0_CTRL_OFFSET 0x300 +#define K3_VTM_TMPSENS_STAT_OFFSET 0x8 +#define K3_VTM_ANYMAXT_OUTRG_ALERT_EN 0x1 +#define K3_VTM_LOW_TEMP_OFFSET 0x10 +#define K3_VTM_MISC_CTRL2_OFFSET 0x10 +#define K3_VTM_MISC_CTRL1_OFFSET 0xc +#define K3_VTM_TMPSENS_CTRL1_SOC BIT(5) +#define K3_VTM_TMPSENS_CTRL_CLRZ BIT(6) +#define K3_VTM_TMPSENS_CTRL_MAXT_OUTRG_EN BIT(11) +#define K3_VTM_ADC_COUNT_FOR_123C 0x2f8 +#define K3_VTM_ADC_COUNT_FOR_105C 0x288 +#define K3_VTM_ADC_WA_VALUE 0x2c +#define K3_VTM_FUSE_MASK 0xc0000000 + #define VD_FLAG_INIT_DONE BIT(0) struct k3_avs_privdata { void *base; struct vd_config *vd_config; + struct udevice *dev; }; struct opp { @@ -237,6 +255,88 @@ static int k3_avs_configure(struct udevice *dev, struct k3_avs_privdata *priv) return 0; } +/* k3_avs_program_tshut : Program thermal shutdown value for SOC + * set the values corresponding to thresholds to ~123C and 105C + * This is optional feature, Few times OS driver takes care of + * tshut programing. + */ + +static void k3_avs_program_tshut(struct k3_avs_privdata *priv) +{ + int cnt, id, val; + int workaround_needed = 0; + u32 ctrl_offset; + void __iomem *cfg2_base; + void __iomem *fuse_base; + + cfg2_base = (void __iomem *)devfdt_get_addr_index(priv->dev, 1); + if (IS_ERR(cfg2_base)) { + dev_err(priv->dev, "cfg base is not defined\n"); + return; + } + + /* + * Some of TI's J721E SoCs require a software trimming procedure + * for the temperature monitors to function properly. To determine + * if this particular SoC is NOT affected, both bits in the + * WKUP_SPARE_FUSE0[31:30] will be set (0xC0000000) indicating + * when software trimming should NOT be applied. + * + * https://www.ti.com/lit/er/sprz455c/sprz455c.pdf + * This routine checks if workaround_needed to be applied or not + * based upon workaround_needed, adjust fixed value of tshut high and low + */ + + if (device_is_compatible(priv->dev, "ti,j721e-vtm")) { + fuse_base = (void __iomem *)devfdt_get_addr_index(priv->dev, 2); + if (IS_ERR(fuse_base)) { + dev_err(priv->dev, "fuse-base is not defined for J721E Soc\n"); + return; + } + + if (!((readl(fuse_base) & K3_VTM_FUSE_MASK) == K3_VTM_FUSE_MASK)) + workaround_needed = 1; + } + + dev_dbg(priv->dev, "Work around %sneeded\n", workaround_needed ? "" : "not "); + + /* Get the sensor count in the VTM */ + val = readl(priv->base + K3_VTM_DEVINFO_PWR0_OFFSET); + cnt = val & K3_VTM_DEVINFO_PWR0_TEMPSENS_CT_MASK; + cnt >>= __ffs(K3_VTM_DEVINFO_PWR0_TEMPSENS_CT_MASK); + + /* Program the thermal sensors */ + for (id = 0; id < cnt; id++) { + ctrl_offset = K3_VTM_TMPSENS0_CTRL_OFFSET + id * 0x20; + + val = readl(cfg2_base + ctrl_offset); + val |= (K3_VTM_TMPSENS_CTRL_MAXT_OUTRG_EN | + K3_VTM_TMPSENS_CTRL1_SOC | + K3_VTM_TMPSENS_CTRL_CLRZ | BIT(4)); + writel(val, cfg2_base + ctrl_offset); + } + + /* + * Program TSHUT thresholds + * Step 1: set the thresholds to ~123C and 105C WKUP_VTM_MISC_CTRL2 + * Step 2: WKUP_VTM_TMPSENS_CTRL_j set the MAXT_OUTRG_EN bit + * This is already taken care as per of init + * Step 3: WKUP_VTM_MISC_CTRL set the ANYMAXT_OUTRG_ALERT_EN bit + */ + + /* Low thresholds for tshut*/ + val = (K3_VTM_ADC_COUNT_FOR_105C - workaround_needed * K3_VTM_ADC_WA_VALUE) + << K3_VTM_LOW_TEMP_OFFSET; + /* high thresholds */ + val |= K3_VTM_ADC_COUNT_FOR_123C - workaround_needed * K3_VTM_ADC_WA_VALUE; + + writel(val, cfg2_base + K3_VTM_MISC_CTRL2_OFFSET); + /* ramp-up delay from Linux code */ + mdelay(100); + val = readl(cfg2_base + K3_VTM_MISC_CTRL1_OFFSET) | K3_VTM_ANYMAXT_OUTRG_ALERT_EN; + writel(val, cfg2_base + K3_VTM_MISC_CTRL1_OFFSET); +} + /** * k3_avs_probe: parses VD info from VTM, and re-configures the OPP data * @@ -255,6 +355,7 @@ static int k3_avs_probe(struct udevice *dev) int ret; priv = dev_get_priv(dev); + priv->dev = dev; k3_avs_priv = priv; @@ -294,6 +395,9 @@ static int k3_avs_probe(struct udevice *dev) k3_avs_program_voltage(priv, vd, vd->opp); } + if (!device_is_compatible(priv->dev, "ti,am654-avs")) + k3_avs_program_tshut(priv); + return 0; } diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 43f7363b9d..fc8383d84b 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -293,7 +293,7 @@ static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, break; case OMAP_ECC_BCH8_CODE_HW: bch_type = 1; - nsectors = chip->ecc.steps; + nsectors = 1; if (mode == NAND_ECC_READ) { wr_mode = BCH_WRAPMODE_1; ecc_size0 = BCH8R_ECC_SIZE0; @@ -306,7 +306,7 @@ static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, break; case OMAP_ECC_BCH16_CODE_HW: bch_type = 0x2; - nsectors = chip->ecc.steps; + nsectors = 1; if (mode == NAND_ECC_READ) { wr_mode = 0x01; ecc_size0 = 52; /* ECC bits in nibbles per sector */ @@ -345,17 +345,16 @@ static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, } /** - * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector + * omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector * @mtd: MTD device structure * @dat: The pointer to data on which ecc is computed * @ecc_code: The ecc_code buffer - * @sector: The sector number (for a multi sector page) * * Support calculating of BCH4/8/16 ECC vectors for one sector * within a page. Sector number is in @sector. */ -static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat, - u8 *ecc_code, int sector) +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat, + u8 *ecc_code) { struct nand_chip *chip = mtd_to_nand(mtd); struct omap_nand_info *info = nand_get_controller_data(chip); @@ -368,7 +367,7 @@ static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat, case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: #endif case OMAP_ECC_BCH8_CODE_HW: - ptr = &gpmc_cfg->bch_result_0_3[sector].bch_result_x[3]; + ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; val = readl(ptr); ecc_code[i++] = (val >> 0) & 0xFF; ptr--; @@ -383,21 +382,21 @@ static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat, break; case OMAP_ECC_BCH16_CODE_HW: - val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[2]); + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]); ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF; - val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[1]); + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF; - val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[0]); + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF; for (j = 3; j >= 0; j--) { - val = readl(&gpmc_cfg->bch_result_0_3[sector].bch_result_x[j] + val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j] ); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; @@ -431,22 +430,6 @@ static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat, return 0; } -/** - * omap_calculate_ecc_bch - ECC generator for 1 sector - * @mtd: MTD device structure - * @dat: The pointer to data on which ecc is computed - * @ecc_code: The ecc_code buffer - * - * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used - * when SW based correction is required as ECC is required for one sector - * at a time. - */ -static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd, - const u_char *dat, u_char *ecc_calc) -{ - return _omap_calculate_ecc_bch(mtd, dat, ecc_calc, 0); -} - static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { struct nand_chip *chip = mtd_to_nand(mtd); @@ -572,34 +555,6 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) #ifdef CONFIG_NAND_OMAP_ELM -/** - * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors - * @mtd: MTD device structure - * @dat: The pointer to data on which ecc is computed - * @ecc_code: The ecc_code buffer - * - * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go. - */ -static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd, - const u_char *dat, u_char *ecc_calc) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - int eccbytes = chip->ecc.bytes; - unsigned long nsectors; - int i, ret; - - nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1; - for (i = 0; i < nsectors; i++) { - ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i); - if (ret) - return ret; - - ecc_calc += eccbytes; - } - - return 0; -} - /* * omap_reverse_list - re-orders list elements in reverse order [internal] * @list: pointer to start of list @@ -752,32 +707,38 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, { int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; - int ecctotal = chip->ecc.total; int eccsteps = chip->ecc.steps; uint8_t *p = buf; uint8_t *ecc_calc = chip->buffers->ecccalc; uint8_t *ecc_code = chip->buffers->ecccode; uint32_t *eccpos = chip->ecc.layout->eccpos; uint8_t *oob = chip->oob_poi; + uint32_t data_pos; uint32_t oob_pos; + data_pos = 0; /* oob area start */ oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0]; oob += chip->ecc.layout->eccpos[0]; - /* Enable ECC engine */ - chip->ecc.hwctl(mtd, NAND_ECC_READ); + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize, + oob += eccbytes) { + /* Enable ECC engine */ + chip->ecc.hwctl(mtd, NAND_ECC_READ); - /* read entire page */ - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0, -1); - chip->read_buf(mtd, buf, mtd->writesize); + /* read data */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1); + chip->read_buf(mtd, p, eccsize); - /* read all ecc bytes from oob area */ - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1); - chip->read_buf(mtd, oob, ecctotal); + /* read respective ecc from oob area */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1); + chip->read_buf(mtd, oob, eccbytes); + /* read syndrome */ + chip->ecc.calculate(mtd, p, &ecc_calc[i]); - /* Calculate ecc bytes */ - omap_calculate_ecc_bch_multi(mtd, buf, ecc_calc); + data_pos += eccsize; + oob_pos += eccbytes; + } for (i = 0; i < chip->ecc.total; i++) ecc_code[i] = chip->oob_poi[eccpos[i]]; @@ -945,6 +906,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch_sw; nand->ecc.calculate = omap_calculate_ecc_bch; + nand->ecc.steps = eccsteps; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; @@ -987,6 +949,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.correct = omap_correct_data_bch; nand->ecc.calculate = omap_calculate_ecc_bch; nand->ecc.read_page = omap_read_page_bch; + nand->ecc.steps = eccsteps; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; for (i = 0; i < ecclayout->eccbytes; i++) @@ -1020,6 +983,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.correct = omap_correct_data_bch; nand->ecc.calculate = omap_calculate_ecc_bch; nand->ecc.read_page = omap_read_page_bch; + nand->ecc.steps = eccsteps; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; for (i = 0; i < ecclayout->eccbytes; i++) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 03bf3f0bdd..f7b9c472e9 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2119,6 +2119,36 @@ read_err: return ret; } +/** + * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters. + * @nor: pointer to a 'struct spi_nor' + * @addr: offset in the SFDP area to start reading data from + * @len: number of bytes to read + * @buf: buffer where the SFDP data are copied into + * + * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not + * guaranteed to be dma-safe. + * + * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp() + * otherwise. + */ +static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr, + size_t len, void *buf) +{ + void *dma_safe_buf; + int ret; + + dma_safe_buf = kmalloc(len, GFP_KERNEL); + if (!dma_safe_buf) + return -ENOMEM; + + ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf); + memcpy(buf, dma_safe_buf, len); + kfree(dma_safe_buf); + + return ret; +} + /* Fast Read settings. */ static void @@ -2292,7 +2322,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, bfpt_header->length * sizeof(u32)); addr = SFDP_PARAM_HEADER_PTP(bfpt_header); memset(&bfpt, 0, sizeof(bfpt)); - err = spi_nor_read_sfdp(nor, addr, len, &bfpt); + err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt); if (err < 0) return err; @@ -2618,7 +2648,7 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, int i, err; /* Get the SFDP header. */ - err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header); + err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header); if (err < 0) return err; diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index e13dbc9401..02660e4fbb 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -41,8 +41,10 @@ endchoice config TI_AM65_CPSW_NUSS bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver" depends on ARCH_K3 + imply DM_MDIO imply MISC_INIT_R imply MISC + imply SYSCON select PHYLIB help This driver supports TI K3 MCU CPSW Nuss Ethernet controller diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index f674b0baa3..51a8167d14 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -15,13 +15,16 @@ #include <dm.h> #include <dm/device_compat.h> #include <dm/lists.h> +#include <dm/pinctrl.h> #include <dma-uclass.h> #include <dm/of_access.h> #include <miiphy.h> #include <net.h> #include <phy.h> #include <power-domain.h> +#include <regmap.h> #include <soc.h> +#include <syscon.h> #include <linux/bitops.h> #include <linux/soc/ti/ti-udma.h> @@ -100,8 +103,6 @@ struct am65_cpsw_common { fdt_addr_t cpsw_base; fdt_addr_t mdio_base; fdt_addr_t ale_base; - fdt_addr_t gmii_sel; - fdt_addr_t mac_efuse; struct clk fclk; struct power_domain pwrdmn; @@ -223,23 +224,45 @@ out: return phy->link; } +#define AM65_GMII_SEL_PORT_OFFS(x) (0x4 * ((x) - 1)) + #define AM65_GMII_SEL_MODE_MII 0 #define AM65_GMII_SEL_MODE_RMII 1 #define AM65_GMII_SEL_MODE_RGMII 2 #define AM65_GMII_SEL_RGMII_IDMODE BIT(4) -static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, - phy_interface_t phy_mode, int slave) +static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, + phy_interface_t phy_mode) { - struct am65_cpsw_common *common = priv->cpsw_common; - u32 reg; - u32 mode = 0; + struct udevice *dev = priv->dev; + u32 offset, reg, phandle; bool rgmii_id = false; + fdt_addr_t gmii_sel; + u32 mode = 0; + ofnode node; + int ret; + + ret = ofnode_read_u32(dev_ofnode(dev), "phys", &phandle); + if (ret) + return ret; + + ret = ofnode_read_u32_index(dev_ofnode(dev), "phys", 1, &offset); + if (ret) + return ret; - reg = readl(common->gmii_sel); + node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(node)) + return -ENODEV; + + gmii_sel = ofnode_get_addr(node); + if (gmii_sel == FDT_ADDR_T_NONE) + return -ENODEV; - dev_dbg(common->dev, "old gmii_sel: %08x\n", reg); + gmii_sel += AM65_GMII_SEL_PORT_OFFS(offset); + reg = readl(gmii_sel); + + dev_dbg(dev, "old gmii_sel: %08x\n", reg); switch (phy_mode) { case PHY_INTERFACE_MODE_RMII: @@ -258,7 +281,7 @@ static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, break; default: - dev_warn(common->dev, + dev_warn(dev, "Unsupported PHY mode: %u. Defaulting to MII.\n", phy_mode); /* fallthrough */ @@ -271,15 +294,19 @@ static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, mode |= AM65_GMII_SEL_RGMII_IDMODE; reg = mode; - dev_dbg(common->dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n", + dev_dbg(dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n", phy_mode, reg); - writel(reg, common->gmii_sel); + writel(reg, gmii_sel); - reg = readl(common->gmii_sel); - if (reg != mode) - dev_err(common->dev, + reg = readl(gmii_sel); + if (reg != mode) { + dev_err(dev, "gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n", mode, reg); + return 0; + } + + return 0; } static int am65_cpsw_start(struct udevice *dev) @@ -513,24 +540,45 @@ static void am65_cpsw_stop(struct udevice *dev) common->started = false; } +static int am65_cpsw_am654_get_efuse_macid(struct udevice *dev, + int slave, u8 *mac_addr) +{ + u32 mac_lo, mac_hi, offset; + struct regmap *syscon; + int ret; + + syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-efuse"); + if (IS_ERR(syscon)) { + if (PTR_ERR(syscon) == -ENODEV) + return 0; + return PTR_ERR(syscon); + } + + ret = dev_read_u32_index(dev, "ti,syscon-efuse", 1, &offset); + if (ret) + return ret; + + regmap_read(syscon, offset, &mac_lo); + regmap_read(syscon, offset + 4, &mac_hi); + + mac_addr[0] = (mac_hi >> 8) & 0xff; + mac_addr[1] = mac_hi & 0xff; + mac_addr[2] = (mac_lo >> 24) & 0xff; + mac_addr[3] = (mac_lo >> 16) & 0xff; + mac_addr[4] = (mac_lo >> 8) & 0xff; + mac_addr[5] = mac_lo & 0xff; + + return 0; +} + static int am65_cpsw_read_rom_hwaddr(struct udevice *dev) { struct am65_cpsw_priv *priv = dev_get_priv(dev); - struct am65_cpsw_common *common = priv->cpsw_common; struct eth_pdata *pdata = dev_get_plat(dev); - u32 mac_hi, mac_lo; - if (common->mac_efuse == FDT_ADDR_T_NONE) - return -1; - - mac_lo = readl(common->mac_efuse); - mac_hi = readl(common->mac_efuse + 4); - pdata->enetaddr[0] = (mac_hi >> 8) & 0xff; - pdata->enetaddr[1] = mac_hi & 0xff; - pdata->enetaddr[2] = (mac_lo >> 24) & 0xff; - pdata->enetaddr[3] = (mac_lo >> 16) & 0xff; - pdata->enetaddr[4] = (mac_lo >> 8) & 0xff; - pdata->enetaddr[5] = mac_lo & 0xff; + am65_cpsw_am654_get_efuse_macid(dev, + priv->port_id, + pdata->enetaddr); return 0; } @@ -558,14 +606,62 @@ static const struct soc_attr k3_mdio_soc_data[] = { { /* sentinel */ }, }; +static ofnode am65_cpsw_find_mdio(ofnode parent) +{ + ofnode node; + + ofnode_for_each_subnode(node, parent) + if (ofnode_device_is_compatible(node, "ti,cpsw-mdio")) + return node; + + return ofnode_null(); +} + +static int am65_cpsw_mdio_setup(struct udevice *dev) +{ + struct am65_cpsw_priv *priv = dev_get_priv(dev); + struct am65_cpsw_common *cpsw_common = priv->cpsw_common; + struct udevice *mdio_dev; + ofnode mdio; + int ret; + + mdio = am65_cpsw_find_mdio(dev_ofnode(cpsw_common->dev)); + if (!ofnode_valid(mdio)) + return 0; + + /* + * The MDIO controller is represented in the DT binding by a + * subnode of the MAC controller. + * + * We don't have a DM driver for the MDIO device yet, and thus any + * pinctrl setting on its node will be ignored. + * + * However, we do need to make sure the pins states tied to the + * MDIO node are configured properly. Fortunately, the core DM + * does that for use when we get a device, so we can work around + * that whole issue by just requesting a dummy MDIO driver to + * probe, and our pins will get muxed. + */ + ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdio_dev); + if (ret) + return ret; + + return 0; +} + static int am65_cpsw_mdio_init(struct udevice *dev) { struct am65_cpsw_priv *priv = dev_get_priv(dev); struct am65_cpsw_common *cpsw_common = priv->cpsw_common; + int ret; if (!priv->has_phy || cpsw_common->bus) return 0; + ret = am65_cpsw_mdio_setup(dev); + if (ret) + return ret; + cpsw_common->bus = cpsw_mdio_init(dev->name, cpsw_common->mdio_base, cpsw_common->bus_freq, @@ -683,7 +779,9 @@ static int am65_cpsw_port_probe(struct udevice *dev) if (ret) goto out; - am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id); + ret = am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface); + if (ret) + goto out; ret = am65_cpsw_mdio_init(dev); if (ret) @@ -707,8 +805,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) cpsw_common->ss_base = dev_read_addr(dev); if (cpsw_common->ss_base == FDT_ADDR_T_NONE) return -EINVAL; - cpsw_common->mac_efuse = devfdt_get_addr_name(dev, "mac_efuse"); - /* no err check - optional */ ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0); if (ret) { @@ -780,19 +876,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET; } - node = dev_read_subnode(dev, "cpsw-phy-sel"); - if (!ofnode_valid(node)) { - dev_err(dev, "can't find cpsw-phy-sel\n"); - ret = -ENOENT; - goto out; - } - - cpsw_common->gmii_sel = ofnode_get_addr(node); - if (cpsw_common->gmii_sel == FDT_ADDR_T_NONE) { - dev_err(dev, "failed to get gmii_sel base\n"); - goto out; - } - cpsw_common->bus_freq = dev_read_u32_default(dev, "bus_freq", AM65_CPSW_MDIO_BUS_FREQ_DEF); @@ -834,3 +917,14 @@ U_BOOT_DRIVER(am65_cpsw_nuss_port) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE, }; + +static const struct udevice_id am65_cpsw_mdio_ids[] = { + { .compatible = "ti,cpsw-mdio" }, + { } +}; + +U_BOOT_DRIVER(am65_cpsw_mdio) = { + .name = "am65_cpsw_mdio", + .id = UCLASS_MDIO, + .of_match = am65_cpsw_mdio_ids, +}; diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index 0ff174e57e..de6e2b70c8 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -105,6 +105,12 @@ static const struct soc_attr ti_k3_soc_pd_data[] = { .data = &j784s4_pd_platdata, }, #endif +#ifdef CONFIG_SOC_K3_AM62P5 + { + .family = "AM62PX", + .data = &am62px_pd_platdata, + }, +#endif { /* sentinel */ } }; diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index fac8c9314b..81dc2666e8 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -65,7 +65,7 @@ choice default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 default K3_AM64_DDRSS if SOC_K3_AM642 default K3_AM64_DDRSS if SOC_K3_AM625 - default K3_AM62A_DDRSS if SOC_K3_AM62A7 + default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 config K3_J721E_DDRSS bool "Enable J721E DDRSS support" diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 7e445d2b73..75d13df8ad 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -667,9 +667,6 @@ int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; int bank; - if (ddrss->ecc_reserved_space == 0) - return 0; - for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) { if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) { ddrss->ecc_reserved_space -= bd->bi_dram[bank].size; diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c index 42a33a822e..8159b40a14 100644 --- a/drivers/remoteproc/ti_k3_dsp_rproc.c +++ b/drivers/remoteproc/ti_k3_dsp_rproc.c @@ -57,6 +57,7 @@ struct k3_dsp_boot_data { * @data: Pointer to DSP specific boot data structure * @mem: Array of available memories * @num_mem: Number of available memories + * @in_use: flag to tell if the core is already in use. */ struct k3_dsp_privdata { struct reset_ctl dsp_rst; @@ -64,6 +65,7 @@ struct k3_dsp_privdata { struct k3_dsp_boot_data *data; struct k3_dsp_mem *mem; int num_mems; + bool in_use; }; /* @@ -130,6 +132,13 @@ static int k3_dsp_load(struct udevice *dev, ulong addr, ulong size) void *image_addr = (void *)addr; int ret; + if (dsp->in_use) { + dev_err(dev, + "Invalid op: Trying to load/start on already running core %d\n", + dsp->tsp.proc_id); + return -EINVAL; + } + dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size); ret = ti_sci_proc_request(&dsp->tsp); if (ret) @@ -198,7 +207,7 @@ static int k3_dsp_start(struct udevice *dev) if (!data->uses_lreset) ti_sci_proc_power_domain_off(&dsp->tsp); } - + dsp->in_use = true; proc_release: ti_sci_proc_release(&dsp->tsp); @@ -211,6 +220,7 @@ static int k3_dsp_stop(struct udevice *dev) dev_dbg(dev, "%s\n", __func__); + dsp->in_use = false; ti_sci_proc_request(&dsp->tsp); reset_assert(&dsp->dsp_rst); ti_sci_proc_power_domain_off(&dsp->tsp); diff --git a/drivers/remoteproc/ti_k3_m4_rproc.c b/drivers/remoteproc/ti_k3_m4_rproc.c index 15477ec3d9..39e19e0bc3 100644 --- a/drivers/remoteproc/ti_k3_m4_rproc.c +++ b/drivers/remoteproc/ti_k3_m4_rproc.c @@ -20,6 +20,7 @@ #include <linux/err.h> #include <linux/sizes.h> #include <linux/soc/ti/ti_sci_protocol.h> +#include <mach/security.h> #include "ti_sci_proc.h" #include <mach/security.h> diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index 31c59f6862..cf3ab59be9 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -46,6 +46,7 @@ /* R5 TI-SCI Processor Control Flags */ #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 +#define PROC_BOOT_CTRL_FLAG_R5_LPSC 0x00000002 /* R5 TI-SCI Processor Status Flags */ #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001 @@ -71,6 +72,7 @@ struct k3_r5f_ip_data { bool tcm_is_double; bool tcm_ecc_autoinit; bool is_single_core; + bool is_dm_core; }; /** @@ -209,19 +211,28 @@ static int k3_r5f_split_release(struct k3_r5f_core *core) dev_dbg(core->dev, "%s\n", __func__); - ret = ti_sci_proc_power_domain_on(&core->tsp); - if (ret) { - dev_err(core->dev, "module-reset deassert failed, ret = %d\n", - ret); - return ret; - } + if (core->ipdata->is_dm_core) { + ret = ti_sci_proc_set_control(&core->tsp, + PROC_BOOT_CTRL_FLAG_R5_LPSC, 0); + if (ret) { + dev_err(core->dev, "LPSC on failed, ret = %d\n", ret); + return ret; + } + } else { + ret = ti_sci_proc_power_domain_on(&core->tsp); + if (ret) { + dev_err(core->dev, "module-reset deassert failed, ret = %d\n", + ret); + return ret; + } - ret = reset_deassert(&core->reset); - if (ret) { - dev_err(core->dev, "local-reset deassert failed, ret = %d\n", - ret); - if (ti_sci_proc_power_domain_off(&core->tsp)) - dev_warn(core->dev, "module-reset assert back failed\n"); + ret = reset_deassert(&core->reset); + if (ret) { + dev_err(core->dev, "local-reset deassert failed, ret = %d\n", + ret); + if (ti_sci_proc_power_domain_off(&core->tsp)) + dev_warn(core->dev, "module-reset assert back failed\n"); + } } return ret; @@ -443,15 +454,24 @@ proc_release: static int k3_r5f_split_reset(struct k3_r5f_core *core) { - int ret; + int ret = 0; dev_dbg(core->dev, "%s\n", __func__); - if (reset_assert(&core->reset)) - ret = -EINVAL; + if (core->ipdata->is_dm_core) { + ret = ti_sci_proc_set_control(&core->tsp, 0, + PROC_BOOT_CTRL_FLAG_R5_LPSC); + if (ret) { + dev_err(core->dev, "LPSC off failed, ret = %d\n", ret); + return ret; + } + } else { + if (reset_assert(&core->reset)) + ret = -EINVAL; - if (ti_sci_proc_power_domain_off(&core->tsp)) - ret = -EINVAL; + if (ti_sci_proc_power_domain_off(&core->tsp)) + ret = -EINVAL; + } return ret; } @@ -831,9 +851,21 @@ static int k3_r5f_probe(struct udevice *dev) return ret; if (core->in_use) { - dev_info(dev, "Core %d is already in use. No rproc commands work\n", - core->tsp.proc_id); - return 0; + /* + * If MCU R5F is booted in split mode by ROM code, core0 + * will run DM firmware and second core sits in WFI. + * Shut it down so that it can be probed as split core. + */ + if (core->ipdata->is_dm_core && !is_primary_core(core) && + core->cluster->mode == CLUSTER_MODE_SPLIT) { + dev_dbg(dev, "Core %d is in WFI mode, resetting core to use in split-mode.\n", + core->tsp.proc_id); + k3_r5f_stop(core->dev); + } else { + dev_info(dev, "Core %d is already in use. No rproc commands work\n", + core->tsp.proc_id); + return 0; + } } /* Make sure Local reset is asserted. Redundant? */ @@ -868,26 +900,47 @@ static const struct k3_r5f_ip_data k3_data = { .tcm_is_double = false, .tcm_ecc_autoinit = false, .is_single_core = false, + .is_dm_core = false, }; static const struct k3_r5f_ip_data j7200_j721s2_data = { .tcm_is_double = true, .tcm_ecc_autoinit = true, .is_single_core = false, + .is_dm_core = false, }; static const struct k3_r5f_ip_data am62_data = { .tcm_is_double = false, .tcm_ecc_autoinit = false, .is_single_core = true, + .is_dm_core = false, +}; + +static const struct k3_r5f_ip_data k3_mcu_data = { + .tcm_is_double = false, + .tcm_ecc_autoinit = false, + .is_single_core = false, + .is_dm_core = true, +}; + +static const struct k3_r5f_ip_data j7200_mcu_data = { + .tcm_is_double = true, + .tcm_ecc_autoinit = true, + .is_single_core = false, + .is_dm_core = true, }; static const struct udevice_id k3_r5f_rproc_ids[] = { { .compatible = "ti,am654-r5f", .data = (ulong)&k3_data, }, { .compatible = "ti,j721e-r5f", .data = (ulong)&k3_data, }, + { .compatible = "ti,j721e-mcu-r5f", .data = (ulong)&k3_mcu_data, }, { .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_j721s2_data, }, + { .compatible = "ti,j7200-mcu-r5f", .data = (ulong)&j7200_mcu_data, }, { .compatible = "ti,j721s2-r5f", .data = (ulong)&j7200_j721s2_data, }, + { .compatible = "ti,j721s2-mcu-r5f", .data = (ulong)&j7200_mcu_data, }, { .compatible = "ti,am62-r5f", .data = (ulong)&am62_data, }, + { .compatible = "ti,am64-r5f", .data = (ulong)&j7200_j721s2_data, }, {} }; @@ -932,6 +985,7 @@ static const struct udevice_id k3_r5fss_ids[] = { { .compatible = "ti,j7200-r5fss"}, { .compatible = "ti,j721s2-r5fss"}, { .compatible = "ti,am62-r5fss"}, + { .compatible = "ti,am64-r5fss"}, {} }; diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 332664e80b..7b9fdba5bc 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -48,7 +48,9 @@ static const char *get_family_string(u32 idreg) case JTAG_ID_PARTNO_J784S4: family = "J784S4"; break; - + case JTAG_ID_PARTNO_AM62PX: + family = "AM62PX"; + break; default: family = "Unknown Silicon"; }; diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 5abb86610c..298f83d3ed 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -41,6 +41,11 @@ __weak int cadence_qspi_versal_flash_reset(struct udevice *dev) return 0; } +__weak ofnode cadence_qspi_get_subnode(struct udevice *dev) +{ + return dev_read_first_subnode(dev); +} + static int cadence_spi_get_temp(int *temp) { struct udevice *dev; @@ -992,7 +997,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) plat->is_dma = dev_read_bool(bus, "cdns,is-dma"); /* All other parameters are embedded in the child node */ - subnode = dev_read_first_subnode(bus); + subnode = cadence_qspi_get_subnode(bus); if (!ofnode_valid(subnode)) { printf("Error: subnode with SPI flash config missing!\n"); return -ENODEV; diff --git a/drivers/usb/musb-new/ti-musb.c b/drivers/usb/musb-new/ti-musb.c index 91042935b0..291d6f1e2d 100644 --- a/drivers/usb/musb-new/ti-musb.c +++ b/drivers/usb/musb-new/ti-musb.c @@ -302,6 +302,7 @@ static int ti_musb_wrapper_bind(struct udevice *parent) dr_mode = usb_get_dr_mode(node); switch (dr_mode) { case USB_DR_MODE_PERIPHERAL: + case USB_DR_MODE_OTG: /* Bind MUSB device */ ret = device_bind_driver_to_node(parent, "ti-musb-peripheral", diff --git a/include/configs/am62px_evm.h b/include/configs/am62px_evm.h new file mode 100644 index 0000000000..9a95253888 --- /dev/null +++ b/include/configs/am62px_evm.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 AM62Px SoC family + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __CONFIG_AM62PX_EVM_H +#define __CONFIG_AM62PX_EVM_H + +#include <config_distro_bootcmd.h> +#include <environment/ti/mmc.h> + +/* Now for the remaining common defines */ +#include <configs/ti_armv7_common.h> + +/* include Android related settings */ +#if CONFIG_CMD_ABOOTIMG +#include <configs/am62x_evm_android.h> +#endif + +#endif /* __CONFIG_AM62PX_EVM_H */ diff --git a/include/configs/am62x_evm_android.h b/include/configs/am62x_evm_android.h index afabdb4afe..7a1e90c3ae 100644 --- a/include/configs/am62x_evm_android.h +++ b/include/configs/am62x_evm_android.h @@ -74,9 +74,18 @@ "if test $board_name = am62x_skevm; then " \ "echo \" Reading DTB for am62x_skevm...\"; " \ "setenv dtb_index 0;" \ + "elif test $board_name = am62b_p1_skevm; then " \ + "echo \" Reading DTB for am62b_p1_skevm...\"; " \ + "setenv dtb_index 0;" \ "elif test $board_name = am62x_lp_skevm; then " \ "echo \" Reading DTB for am62x_lp_skevm...\"; " \ "setenv dtb_index 1;" \ + "elif test $board_name = am62x_beagleplay; then " \ + "echo \" Reading DTB for am62x_beagleplay...\"; " \ + "setenv dtb_index 2;" \ + "elif test $board_name = am62px; then " \ + "echo \" Reading DTB for am62px...\"; " \ + "setenv dtb_index 3;" \ "else " \ "echo Error: Android boot is not supported for $board_name; " \ "exit; " \ @@ -138,6 +147,8 @@ #define BOOTENV_DEV_RECOVERY(devtypeu, devtypel, instance) \ "bootcmd_recovery=" \ "setenv run_recovery 0;" \ + "setenv ramdisk_addr_r 0xe9000000;" \ + "setenv vloadaddr 0xe0000000;" \ "if bcb load " __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) " " \ CONTROL_PARTITION "; then " \ "if bcb test command = boot-recovery; then; " \ @@ -163,10 +174,15 @@ "run avb_verify_cmd;" \ "part start mmc ${mmcdev} " RECOVERY_PARTITION "${slot_suffix} boot_start;" \ "part size mmc ${mmcdev} " RECOVERY_PARTITION "${slot_suffix} boot_size;" \ + "part start mmc ${mmcdev} vendor_boot${slot_suffix} vendor_boot_start;" \ + "part size mmc ${mmcdev} vendor_boot${slot_suffix} vendor_boot_size;" \ "if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \ - "run prepare_fdt_cmd;" \ - "echo Running Android Recovery...;" \ - BOOT_CMD \ + "if mmc read $vloadaddr ${vendor_boot_start} ${vendor_boot_size}; then " \ + "abootimg addr $loadaddr $vloadaddr;" \ + "run prepare_fdt_cmd;" \ + "echo Running Android Recovery...;" \ + BOOT_CMD \ + "fi;" \ "fi;" \ "echo Failed to boot Android...;" \ "reset;" \ @@ -182,13 +198,20 @@ "setenv bootargs ${bootargs} androidboot.serialno=${serial#};" \ "run ab_select_slot_cmd;" \ "run avb_verify_cmd;" \ + "setenv ramdisk_addr_r 0xe9000000;" \ + "setenv vloadaddr 0xe0000000;" \ "part start mmc ${mmcdev} " BOOT_PARTITION "${slot_suffix} boot_start;" \ "part size mmc ${mmcdev} " BOOT_PARTITION "${slot_suffix} boot_size;" \ + "part start mmc ${mmcdev} vendor_boot${slot_suffix} vendor_boot_start;" \ + "part size mmc ${mmcdev} vendor_boot${slot_suffix} vendor_boot_size;" \ "if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \ - "run prepare_fdt_cmd;" \ - "setenv bootargs \"${bootargs} " AB_BOOTARGS "\" ; " \ - "echo Running Android...;" \ - BOOT_CMD \ + "if mmc read $vloadaddr ${vendor_boot_start} ${vendor_boot_size}; then " \ + "abootimg addr $loadaddr $vloadaddr;" \ + "run prepare_fdt_cmd;" \ + "setenv bootargs \"${bootargs} " AB_BOOTARGS "\" ; " \ + "echo Running Android...;" \ + BOOT_CMD \ + "fi;" \ "fi;" \ "echo Failed to boot Android...\0" diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 1e37ab47b9..dc42f4ba3d 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -21,4 +21,20 @@ /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> +/* NAND Driver config */ +#define CFG_SYS_NAND_BASE 0x51000000 + +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CFG_SYS_NAND_ECCSIZE 512 + +#define CFG_SYS_NAND_ECCBYTES 14 +/*-- end NAND config --*/ + #endif /* __CONFIG_AM642_EVM_H */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 74a39c4078..6c81353882 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -239,20 +239,47 @@ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" +#define GET_OVERLAY_MMC_TI_ARGS \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay} &&" \ + "fdt apply ${dtboaddr};" \ + "done;\0" \ + #define BOOT_TARGET_DEVICES(func) \ + func(TI_MMC, ti_mmc, na) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) +#define BOOTENV_DEV_TI_MMC(devtypeu, devtypel, instance) \ + "bootcmd_ti_mmc= run get_name_kern; run mmcboot\0" + +#define BOOTENV_DEV_NAME_TI_MMC(devtyeu, devtypel, instance) \ + "ti_mmc " + #include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "get_name_kern=" \ + "if test $boot_fit -eq 1; then " \ + "setenv bootfile fitImage; " \ + "else " \ + "setenv bootfile zImage; " \ + "fi\0" \ DEFAULT_FIT_TI_ARGS \ + "get_fit_config=setenv name_fit_config ${fdtfile}\0" \ DEFAULT_COMMON_BOOT_TI_ARGS \ DEFAULT_FDT_TI_ARGS \ + GET_OVERLAY_MMC_TI_ARGS \ DFUARGS \ NETARGS \ NANDARGS \ diff --git a/include/environment/ti/k3_dfu_combined.env b/include/environment/ti/k3_dfu_combined.env index eea3ad0d58..643fcdbdbf 100644 --- a/include/environment/ti/k3_dfu_combined.env +++ b/include/environment/ti/k3_dfu_combined.env @@ -13,7 +13,7 @@ dfu_alt_info_emmc= tiboot3.bin.raw raw 0x0 0x800 mmcpart 1; tispl.bin.raw raw 0x800 0x1000 mmcpart 1; u-boot.img.raw raw 0x1800 0x2000 mmcpart 1; - u-env.raw raw 0x3400 0x100 mmcpart 1 + u-env.raw raw 0x3800 0x100 mmcpart 1 dfu_alt_info_ospi= tiboot3.bin raw 0x0 0x100000; @@ -26,3 +26,20 @@ dfu_alt_info_ram= tispl.bin ram 0x80080000 0x200000; u-boot.img ram 0x81000000 0x400000 +dfu_alt_info_nand= + NAND.tiboot3 part 0 1; + NAND.tispl part 0 2; + NAND.tiboot3.backup part 0 3; + NAND.u-boot part 0 4; + NAND.u-boot-env part 0 5; + NAND.u-boot-env.backup part 0 6; + NAND.file-system part 0 7 + +dfu_alt_info_ospi_nand= + ospi_nand.tiboot3 part 1; + ospi_nand.tispl part 2; + ospi_nand.u-boot part 3; + ospi_nand.env part 4; + ospi_nand.env.backup part 5; + ospi_nand.rootfs part 6; + ospi_nand.phypattern part 7 diff --git a/include/environment/ti/mmc.env b/include/environment/ti/mmc.env index 6fb47fb266..1e62bf85da 100644 --- a/include/environment/ti/mmc.env +++ b/include/environment/ti/mmc.env @@ -66,7 +66,7 @@ get_overlay_mmc= fdt resize 0x100000; for overlay in $name_overlays; do; - load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay} && + load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/ti/${overlay} && fdt apply ${dtboaddr}; done; get_kern_mmc=load mmc ${bootpart} ${loadaddr} diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h index 769ea9d5ef..09f8dccd3d 100644 --- a/include/environment/ti/mmc.h +++ b/include/environment/ti/mmc.h @@ -24,7 +24,7 @@ "env import -t ${loadaddr} ${filesize}\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \ "loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/dtb/${fdtfile}\0" \ "envboot=mmc dev ${mmcdev}; " \ "if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ @@ -44,6 +44,7 @@ "mmcloados=" \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ + "run get_overlay_mmc;" \ "bootz ${loadaddr} - ${fdtaddr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ diff --git a/include/environment/ti/mmc_android.env b/include/environment/ti/mmc_android.env index fbf5d25312..7981d54396 100644 --- a/include/environment/ti/mmc_android.env +++ b/include/environment/ti/mmc_android.env @@ -3,10 +3,13 @@ partitions= name=bootloader,start=5M,size=8M,uuid=${uuid_gpt_bootloader}; partitions+=name=tiboot3,start=4M,size=1M,uuid=${uuid_gpt_tiboot3}; -partitions+=name=uboot-env,start=13M,size=512K,uuid=${uuid_gpt_env}; partitions+=name=misc,start=13824K,size=512K,uuid=${uuid_gpt_misc}; partitions+=name=boot_a,size=40M,uuid=${uuid_gpt_boot_a}; partitions+=name=boot_b,size=40M,uuid=${uuid_gpt_boot_b}; +partitions+=name=vendor_boot_a,size=32M,uuid=${uuid_gpt_vendor_boot_a}; +partitions+=name=vendor_boot_b,size=32M,uuid=${uuid_gpt_vendor_boot_b}; +partitions+=name=init_boot_a,size=8M,uuid=${uuid_gpt_init_boot_a}; +partitions+=name=init_boot_b,size=8M,uuid=${uuid_gpt_init_boot_b}; partitions+=name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a}; partitions+=name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b}; partitions+=name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a}; @@ -16,6 +19,9 @@ partitions+=name=metadata,size=16M,uuid=${uuid_gpt_metadata}; partitions+=name=persist,size=32M,uuid=${uuid_gpt_persist}; partitions+=name=userdata,size=-,uuid=${uuid_gpt_userdata} +fastboot.partition-type:metadata=ext4 mmcdev=0 force_avb=0 envboot=run distro_bootcmd + +fastboot_raw_partition_bootenv="0x800 0x400 mmcpart 1" diff --git a/include/environment/ti/ti_armv7_common.env b/include/environment/ti/ti_armv7_common.env index e87a41a659..f5d84216e3 100644 --- a/include/environment/ti/ti_armv7_common.env +++ b/include/environment/ti/ti_armv7_common.env @@ -15,10 +15,10 @@ boot_fit=0 addr_fit=0x90000000 name_fit=fitImage update_to_fit=setenv loadaddr ${addr_fit}; setenv bootfile ${name_fit} -get_overlaystring= - for overlay in $name_overlays; - do; - setenv overlaystring ${overlaystring}'#'${overlay}; +get_fit_overlaystring= + for overlay in $name_overlays; do; + setexpr name_fit_overlay gsub / _ conf-${overlay}; + setenv overlaystring ${overlaystring}'#'${name_fit_overlay}; done; get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile} run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring} @@ -28,7 +28,7 @@ bootcmd_ti_mmc= run main_cpsw0_qsgmii_phyinit; run boot_rprocs; #endif if test ${boot_fit} -eq 1; - then run get_fit_${boot}; run get_overlaystring; run run_fit; + then run get_fit_${boot}; run get_fit_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi; diff --git a/include/k3-clk.h b/include/k3-clk.h index dac9af6487..71e8cfcc26 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -177,6 +177,7 @@ extern const struct ti_k3_clk_platdata j721s2_clk_platdata; extern const struct ti_k3_clk_platdata am62x_clk_platdata; extern const struct ti_k3_clk_platdata am62ax_clk_platdata; extern const struct ti_k3_clk_platdata j784s4_clk_platdata; +extern const struct ti_k3_clk_platdata am62px_clk_platdata; struct clk *clk_register_ti_pll(const char *name, const char *parent_name, void __iomem *reg); diff --git a/include/k3-dev.h b/include/k3-dev.h index 59970866f1..4908473ba3 100644 --- a/include/k3-dev.h +++ b/include/k3-dev.h @@ -81,6 +81,7 @@ extern const struct ti_k3_pd_platdata j721s2_pd_platdata; extern const struct ti_k3_pd_platdata am62x_pd_platdata; extern const struct ti_k3_pd_platdata am62ax_pd_platdata; extern const struct ti_k3_pd_platdata j784s4_pd_platdata; +extern const struct ti_k3_pd_platdata am62px_pd_platdata; u8 ti_pd_state(struct ti_pd *pd); u8 lpsc_get_state(struct ti_lpsc *lpsc); @@ -74,6 +74,16 @@ static long lmb_addrs_adjacent(phys_addr_t base1, phys_size_t size1, return 0; } +static long lmb_regions_overlap(struct lmb_region *rgn, unsigned long r1, + unsigned long r2) +{ + phys_addr_t base1 = rgn->region[r1].base; + phys_size_t size1 = rgn->region[r1].size; + phys_addr_t base2 = rgn->region[r2].base; + phys_size_t size2 = rgn->region[r2].size; + + return lmb_addrs_overlap(base1, size1, base2, size2); +} static long lmb_regions_adjacent(struct lmb_region *rgn, unsigned long r1, unsigned long r2) { @@ -81,7 +91,6 @@ static long lmb_regions_adjacent(struct lmb_region *rgn, unsigned long r1, phys_size_t size1 = rgn->region[r1].size; phys_addr_t base2 = rgn->region[r2].base; phys_size_t size2 = rgn->region[r2].size; - return lmb_addrs_adjacent(base1, size1, base2, size2); } @@ -105,6 +114,23 @@ static void lmb_coalesce_regions(struct lmb_region *rgn, unsigned long r1, lmb_remove_region(rgn, r2); } +/*Assumption : base addr of region 1 < base addr of region 2*/ +static void lmb_fix_over_lap_regions(struct lmb_region *rgn, unsigned long r1, + unsigned long r2) +{ + phys_addr_t base1 = rgn->region[r1].base; + phys_size_t size1 = rgn->region[r1].size; + phys_addr_t base2 = rgn->region[r2].base; + phys_size_t size2 = rgn->region[r2].size; + + if (base1 + size1 > base2 + size2) { + printf("This will not be a case any time\n"); + return; + } + rgn->region[r1].size = base2 + size2 - base1; + lmb_remove_region(rgn, r2); +} + void lmb_init(struct lmb *lmb) { #if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS) @@ -249,7 +275,6 @@ static long lmb_add_region_flags(struct lmb_region *rgn, phys_addr_t base, phys_size_t rgnflags = rgn->region[i].flags; phys_addr_t end = base + size - 1; phys_addr_t rgnend = rgnbase + rgnsize - 1; - if (rgnbase <= base && end <= rgnend) { if (flags == rgnflags) /* Already have this region, so we're done */ @@ -278,10 +303,14 @@ static long lmb_add_region_flags(struct lmb_region *rgn, phys_addr_t base, } } - if ((i < rgn->cnt - 1) && lmb_regions_adjacent(rgn, i, i + 1)) { - if (rgn->region[i].flags == rgn->region[i + 1].flags) { + if (i < rgn->cnt - 1 && rgn->region[i].flags == rgn->region[i + 1].flags) { + if (lmb_regions_adjacent(rgn, i, i + 1)) { lmb_coalesce_regions(rgn, i, i + 1); coalesced++; + } else if (lmb_regions_overlap(rgn, i, i + 1)) { + /* fix overlapping area */ + lmb_fix_over_lap_regions(rgn, i, i + 1); + coalesced++; } } diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 1628875035..15c68ce396 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -451,12 +451,23 @@ static int lib_test_lmb_overlapping_reserve(struct unit_test_state *uts) ut_asserteq(ret, 0); ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40010000, 0x10000, 0x40030000, 0x10000, 0, 0); - /* allocate 2nd region */ + /* allocate 2nd region , This should coalesced all region into one */ ret = lmb_reserve(&lmb, 0x40020000, 0x10000); ut_assert(ret >= 0); ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x30000, 0, 0, 0, 0); + /* allocate 2nd region, which should be added as first region */ + ret = lmb_reserve(&lmb, 0x40000000, 0x8000); + ut_assert(ret >= 0); + ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x8000, + 0x40010000, 0x30000, 0, 0); + + /* allocate 3rd region, coalesce with first and overlap with second */ + ret = lmb_reserve(&lmb, 0x40008000, 0x10000); + ut_assert(ret >= 0); + ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40000000, 0x40000, + 0, 0, 0, 0); return 0; } diff --git a/tools/binman/btool/openssl.py b/tools/binman/btool/openssl.py index aad3b61ae2..ac1eaf5ded 100644 --- a/tools/binman/btool/openssl.py +++ b/tools/binman/btool/openssl.py @@ -82,7 +82,7 @@ imageSize = INTEGER:{len(indata)} return self.run_cmd(*args) def x509_cert_sysfw(self, cert_fname, input_fname, key_fname, sw_rev, - config_fname, req_dist_name_dict): + config_fname, req_dist_name_dict, firewall_cert_data): """Create a certificate to be booted by system firmware Args: @@ -94,6 +94,13 @@ imageSize = INTEGER:{len(indata)} req_dist_name_dict (dict): Dictionary containing key-value pairs of req_distinguished_name section extensions, must contain extensions for C, ST, L, O, OU, CN and emailAddress + firewall_cert_data (dict): + - auth_in_place (int): The Priv ID for copying as the + specific host in firewall protected region + - num_firewalls (int): The number of firewalls in the + extended certificate + - certificate (str): Extended firewall certificate with + the information for the firewall configurations. Returns: str: Tool output @@ -121,6 +128,7 @@ basicConstraints = CA:true 1.3.6.1.4.1.294.1.3 = ASN1:SEQUENCE:swrv 1.3.6.1.4.1.294.1.34 = ASN1:SEQUENCE:sysfw_image_integrity 1.3.6.1.4.1.294.1.35 = ASN1:SEQUENCE:sysfw_image_load +1.3.6.1.4.1.294.1.37 = ASN1:SEQUENCE:firewall [ swrv ] swrv = INTEGER:{sw_rev} @@ -132,7 +140,11 @@ imageSize = INTEGER:{len(indata)} [ sysfw_image_load ] destAddr = FORMAT:HEX,OCT:00000000 -authInPlace = INTEGER:2 +authInPlace = INTEGER:{hex(firewall_cert_data['auth_in_place'])} + +[ firewall ] +numFirewallRegions = INTEGER:{firewall_cert_data['num_firewalls']} +{firewall_cert_data['certificate']} ''', file=outf) args = ['req', '-new', '-x509', '-key', key_fname, '-nodes', '-outform', 'DER', '-out', cert_fname, '-config', config_fname, @@ -155,6 +167,7 @@ authInPlace = INTEGER:2 C, ST, L, O, OU, CN and emailAddress cert_type (int): Certification type bootcore (int): Booting core + bootcore_opts(int): Booting core option (split/lockstep mode) load_addr (int): Load address of image sha (int): Hash function @@ -225,7 +238,7 @@ emailAddress = {req_dist_name_dict['emailAddress']} imagesize_sbl, hashval_sbl, load_addr_sysfw, imagesize_sysfw, hashval_sysfw, load_addr_sysfw_data, imagesize_sysfw_data, hashval_sysfw_data, sysfw_inner_cert_ext_boot_block, - dm_data_ext_boot_block): + dm_data_ext_boot_block, bootcore_opts): """Create a certificate Args: @@ -241,6 +254,7 @@ emailAddress = {req_dist_name_dict['emailAddress']} bootcore (int): Booting core load_addr (int): Load address of image sha (int): Hash function + bootcore_opts (int): Boot core option (split/lockstep mode) Returns: str: Tool output @@ -285,7 +299,7 @@ sysfw_data=SEQUENCE:sysfw_data [sbl] compType = INTEGER:1 bootCore = INTEGER:16 -compOpts = INTEGER:0 +compOpts = INTEGER:{bootcore_opts} destAddr = FORMAT:HEX,OCT:{load_addr:08x} compSize = INTEGER:{imagesize_sbl} shaType = OID:{sha_type} diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index f9900fe6be..fa6d1b6afa 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -1739,6 +1739,7 @@ Properties / Entry arguments: - core: core on which bootloader runs, valid cores are 'secure' and 'public' - content: phandle of SPL in case of legacy bootflow or phandles of component binaries in case of combined bootflow + - core-opts (optional): split-mode (0) or lockstep mode (1) set to 0 by default The following properties are only for generating a combined bootflow binary: - sysfw-inner-cert: boolean if binary contains sysfw inner certificate diff --git a/tools/binman/etype/ti_secure.py b/tools/binman/etype/ti_secure.py index b1f5d89198..f80eb542c9 100644 --- a/tools/binman/etype/ti_secure.py +++ b/tools/binman/etype/ti_secure.py @@ -7,9 +7,40 @@ from binman.entry import EntryArg from binman.etype.x509_cert import Entry_x509_cert +from dataclasses import dataclass from dtoc import fdt_util +@dataclass +class Firewall(): + id: int + region: int + control : int + permissions: list[hex] + start_address: str + end_address: str + + def __post_init__(self): + for key, val in self.__dict__.items(): + if val is None: + raise Exception(f"{key} can't be None in firewall node") + + def get_certificate(self) -> str: + unique_identifier = f"{self.id}{self.region}" + cert = f""" +firewallID{unique_identifier} = INTEGER:{self.id} +region{unique_identifier} = INTEGER:{self.region} +control{unique_identifier} = INTEGER:{hex(self.control)} +nPermissionRegs{unique_identifier} = INTEGER:{len(self.permissions)} +""" + for index, permission in enumerate(self.permissions): + cert += f"""permissions{unique_identifier}{index} = INTEGER:{hex(permission)} +""" + cert += f"""startAddress{unique_identifier} = FORMAT:HEX,OCT:{self.start_address:02x} +endAddress{unique_identifier} = FORMAT:HEX,OCT:{self.end_address:02x} +""" + return cert + class Entry_ti_secure(Entry_x509_cert): """Entry containing a TI x509 certificate binary @@ -17,6 +48,11 @@ class Entry_ti_secure(Entry_x509_cert): - content: List of phandles to entries to sign - keyfile: Filename of file containing key to sign binary with - sha: Hash function to be used for signing + - auth-in-place: This is an integer field that contains two pieces + of information + Lower Byte - Remains 0x02 as per our use case + ( 0x02: Move the authenticated binary back to the header ) + Upper Byte - The Host ID of the core owning the firewall Output files: - input.<unique_name> - input file passed to openssl @@ -25,6 +61,35 @@ class Entry_ti_secure(Entry_x509_cert): - cert.<unique_name> - output file generated by openssl (which is used as the entry contents) + Depending on auth-in-place information in the inputs, we read the + firewall nodes that describe the configurations of firewall that TIFS + will be doing after reading the certificate. + + The syntax of the firewall nodes are as such: + + firewall-257-0 { + id = <257>; /* The ID of the firewall being configured */ + region = <0>; /* Region number to configure */ + + control = /* The control register */ + <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; + + permissions = /* The permission registers */ + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>; + + /* More defines can be found in k3-security.h */ + + start_address = /* The Start Address of the firewall */ + <0x0 0x0>; + end_address = /* The End Address of the firewall */ + <0xff 0xffffffff>; + }; + + openssl signs the provided data, using the TI templated config file and writes the signature in this entry. This allows verification that the data is genuine. @@ -32,11 +97,20 @@ class Entry_ti_secure(Entry_x509_cert): def __init__(self, section, etype, node): super().__init__(section, etype, node) self.openssl = None + self.firewall_cert_data: dict = { + 'auth_in_place': 0x02, + 'num_firewalls': 0, + 'certificate': '', + } def ReadNode(self): super().ReadNode() self.key_fname = self.GetEntryArgsOrProps([ EntryArg('keyfile', str)], required=True)[0] + auth_in_place = fdt_util.GetInt(self._node, 'auth-in-place') + if auth_in_place: + self.firewall_cert_data['auth_in_place'] = auth_in_place + self.ReadFirewallNode() self.sha = fdt_util.GetInt(self._node, 'sha', 512) self.req_dist_name = {'C': 'US', 'ST': 'TX', @@ -46,6 +120,22 @@ class Entry_ti_secure(Entry_x509_cert): 'CN': 'TI Support', 'emailAddress': 'support@ti.com'} + def ReadFirewallNode(self): + self.firewall_cert_data['certificate'] = "" + self.firewall_cert_data['num_firewalls'] = 0 + for node in self._node.subnodes: + if 'firewall' in node.name: + firewall = Firewall( + fdt_util.GetInt(node, 'id'), + fdt_util.GetInt(node, 'region'), + fdt_util.GetInt(node, 'control'), + fdt_util.GetPhandleList(node, 'permissions'), + fdt_util.GetInt64(node, 'start_address'), + fdt_util.GetInt64(node, 'end_address'), + ) + self.firewall_cert_data['num_firewalls'] += 1 + self.firewall_cert_data['certificate'] += firewall.get_certificate() + def GetCertificate(self, required): """Get the contents of this entry diff --git a/tools/binman/etype/ti_secure_rom.py b/tools/binman/etype/ti_secure_rom.py index da03c90ef1..ff55d9d1a4 100644 --- a/tools/binman/etype/ti_secure_rom.py +++ b/tools/binman/etype/ti_secure_rom.py @@ -32,6 +32,7 @@ class Entry_ti_secure_rom(Entry_x509_cert): - core: core on which bootloader runs, valid cores are 'secure' and 'public' - content: phandle of SPL in case of legacy bootflow or phandles of component binaries in case of combined bootflow + - core-opts (optional): split-mode (0) or lockstep mode (1) set to 0 by default The following properties are only for generating a combined bootflow binary: - sysfw-inner-cert: boolean if binary contains sysfw inner certificate @@ -70,6 +71,7 @@ class Entry_ti_secure_rom(Entry_x509_cert): self.sw_rev = fdt_util.GetInt(self._node, 'sw-rev', 1) self.sha = fdt_util.GetInt(self._node, 'sha', 512) self.core = fdt_util.GetString(self._node, 'core', 'secure') + self.bootcore_opts = fdt_util.GetInt(self._node, 'core-opts') self.key_fname = self.GetEntryArgsOrProps([ EntryArg('keyfile', str)], required=True)[0] if self.combined: @@ -98,22 +100,19 @@ class Entry_ti_secure_rom(Entry_x509_cert): bytes content of the entry, which is the certificate binary for the provided data """ + if self.bootcore_opts is None: + self.bootcore_opts = 0 + if self.core == 'secure': if self.countersign: self.cert_type = 3 else: self.cert_type = 2 - - if self.fsstub: - self.bootcore_opts = 0 - else: - self.bootcore_opts = 32 - self.bootcore = 0 else: self.cert_type = 1 self.bootcore = 16 - self.bootcore_opts = 0 + return super().GetCertificate(required=required, type='rom') def CombinedGetCertificate(self, required): @@ -132,6 +131,9 @@ class Entry_ti_secure_rom(Entry_x509_cert): self.num_comps = 3 self.sha_type = SHA_OIDS[self.sha] + if self.bootcore_opts is None: + self.bootcore_opts = 0 + # sbl self.content = fdt_util.GetPhandleList(self._node, 'content-sbl') input_data_sbl = self.GetContents(required) diff --git a/tools/binman/etype/x509_cert.py b/tools/binman/etype/x509_cert.py index d028cfe38c..cd240559e5 100644 --- a/tools/binman/etype/x509_cert.py +++ b/tools/binman/etype/x509_cert.py @@ -98,7 +98,8 @@ class Entry_x509_cert(Entry_collection): key_fname=self.key_fname, config_fname=config_fname, sw_rev=self.sw_rev, - req_dist_name_dict=self.req_dist_name) + req_dist_name_dict=self.req_dist_name, + firewall_cert_data=self.firewall_cert_data) elif type == 'rom': stdout = self.openssl.x509_cert_rom( cert_fname=output_fname, @@ -136,7 +137,8 @@ class Entry_x509_cert(Entry_collection): imagesize_sysfw_data=self.imagesize_sysfw_data, hashval_sysfw_data=self.hashval_sysfw_data, sysfw_inner_cert_ext_boot_block=self.sysfw_inner_cert_ext_boot_block, - dm_data_ext_boot_block=self.dm_data_ext_boot_block + dm_data_ext_boot_block=self.dm_data_ext_boot_block, + bootcore_opts=self.bootcore_opts ) if stdout is not None: data = tools.read_file(output_fname) diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 1555ce9898..5a5da4f53d 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -6463,6 +6463,28 @@ fdt fdtmap Extract the devicetree blob from the fdtmap entry_args=entry_args)[0] self.assertGreater(len(data), len(TI_UNSECURE_DATA)) + def testPackTiSecureFirewall(self): + """Test that an image with a TI secured binary can be created""" + keyfile = self.TestFile('key.key') + entry_args = { + 'keyfile': keyfile, + } + data_no_firewall = self._DoReadFileDtb('296_ti_secure.dts', + entry_args=entry_args)[0] + data_firewall = self._DoReadFileDtb('319_ti_secure_firewall.dts', + entry_args=entry_args)[0] + self.assertGreater(len(data_firewall),len(data_no_firewall)) + + def testPackTiSecureFirewallMissingProperty(self): + """Test that an image with a TI secured binary can be created""" + keyfile = self.TestFile('key.key') + entry_args = { + 'keyfile': keyfile, + } + data_firewall = self._DoReadFileDtb('320_ti_secure_firewall_missing_property.dts', + entry_args=entry_args)[0] + self.assertRegex("can't be None in firewall node", str(e.exception)) + def testPackTiSecureMissingTool(self): """Test that an image with a TI secured binary (non-functional) can be created when openssl is missing""" diff --git a/tools/binman/test/280_ti_secure_rom.dts b/tools/binman/test/280_ti_secure_rom.dts index d1313769f4..1a3eca9425 100644 --- a/tools/binman/test/280_ti_secure_rom.dts +++ b/tools/binman/test/280_ti_secure_rom.dts @@ -9,6 +9,7 @@ binman { ti-secure-rom { content = <&unsecure_binary>; + core-opts = <2>; }; unsecure_binary: blob-ext { filename = "ti_unsecure.bin"; diff --git a/tools/binman/test/319_ti_secure_firewall.dts b/tools/binman/test/319_ti_secure_firewall.dts new file mode 100644 index 0000000000..7ec407fa67 --- /dev/null +++ b/tools/binman/test/319_ti_secure_firewall.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + ti-secure { + content = <&unsecure_binary>; + auth-in-place = <0xa02>; + + firewall-0-2 { + id = <0>; + region = <2>; + control = <0x31a>; + permissions = <0xc3ffff>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + + }; + unsecure_binary: blob-ext { + filename = "ti_unsecure.bin"; + }; + }; +}; diff --git a/tools/binman/test/320_ti_secure_firewall_missing_property.dts b/tools/binman/test/320_ti_secure_firewall_missing_property.dts new file mode 100644 index 0000000000..8e995ffa47 --- /dev/null +++ b/tools/binman/test/320_ti_secure_firewall_missing_property.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + ti-secure { + content = <&unsecure_binary>; + auth-in-place = <0xa02>; + + firewall-0-2 { + // id = <0>; + region = <2>; + control = <0x31a>; + permissions = <0xc3ffff>; + start_address = <0x0 0x9e800000>; + end_address = <0x0 0x9fffffff>; + }; + + }; + unsecure_binary: blob-ext { + filename = "ti_unsecure.bin"; + }; + }; +}; diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c index 7eabcab439..706b4a35f4 100644 --- a/tools/fdtgrep.c +++ b/tools/fdtgrep.c @@ -22,6 +22,8 @@ #include "fdt_host.h" #include "libfdt_internal.h" +#include <linux/kconfig.h> + /* Define DEBUG to get some debugging output on stderr */ #ifdef DEBUG #define debug(a, b...) fprintf(stderr, a, ## b) @@ -1234,6 +1236,12 @@ int main(int argc, char *argv[]) disp.fout = stdout; } + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY)) { + /* include symbol table */ + if (value_add(&disp, &disp.value_head, FDT_IS_NODE, 1, "/__symbols__")) + usage("Cannot add __symbols__ value"); + } + /* Run the grep and output the results */ ret = do_fdtgrep(&disp, filename); if (disp.output_fname) |