diff options
| author | Ye Li <ye.li@nxp.com> | 2018-07-30 08:51:15 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-08-05 19:29:52 -0700 |
| commit | e8bc2dd02211b6bc79f8c6563d79dbf3997ae1df (patch) | |
| tree | ae6b6921372cb6c3c01d10721b77c0ce24a6901e | |
| parent | e469bf980df3fa5c7d4e059aaaed4db296a0b002 (diff) | |
MLK-19086 imx8qxp: Change USDHC root clock to AVPLL for B0
Still meet DPLL unstable issue on iMX8QXP B0 when doing various stress tests.
So switch back to use AVPLL for usdhc on B0
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 099ddce37cf3100d0aeb0964db7b24e5a59ee1d0)
| -rw-r--r-- | arch/arm/mach-imx/imx8/clock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index f12efb32f9..e95a71d0f9 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -299,7 +299,7 @@ void init_clk_usdhc(u32 index) * USDHC2_CLK_ROOT to 200MHz, make eMMC HS400ES work at 166MHz, and SD * SDR104 work at 200MHz. */ - if (is_imx8qxp() && is_soc_rev(CHIP_REV_A)) { + if (is_imx8qxp()) { err = sc_pm_set_clock_parent(ipc, usdhcs[index], 2, SC_PM_PARENT_PLL1); if (err != SC_ERR_NONE) printf("SDHC_%d set clock parent failed!(error = %d)\n", index, err); |