diff options
| author | Tom Rini <trini@konsulko.com> | 2017-12-22 12:19:22 -0500 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-01-09 12:38:55 +0100 |
| commit | b4b9814f1c737d175213b85c5bf1cab0806e2a73 (patch) | |
| tree | 7ca8e73a00975bbb5698f2fb9884bff4ab94a1a9 | |
| parent | 08cc52abc9a5a6900af908a59cbaf8b1acfc88d2 (diff) | |
arm: socfpga: Guard commands with CONFIG_SPL_BUILD tests
In order for these commands to not be included in SPL we need to guard
compilation with CONFIG_SPL_BUILD checks. Reorganize some sections of
code slightly in order to avoid new warnings and mark the command
functions as static as they should have been before.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
| -rw-r--r-- | arch/arm/mach-socfpga/clock_manager.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/misc_gen5.c | 13 |
2 files changed, 11 insertions, 6 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index cb6ae03696..6b76221025 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -59,7 +59,8 @@ int set_cpu_clk_info(void) return 0; } -int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +#ifndef CONFIG_SPL_BUILD +static int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { cm_print_clock_quick_summary(); return 0; @@ -70,3 +71,4 @@ U_BOOT_CMD( "display clocks", "" ); +#endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 91ddb79f73..a7dcaccbb7 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -30,14 +30,10 @@ static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -static struct socfpga_reset_manager *reset_manager_base = - (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; -static struct socfpga_sdr_ctrl *sdr_ctrl = - (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; /* * DesignWare Ethernet initialization @@ -292,6 +288,12 @@ int arch_early_init_r(void) return 0; } +#ifndef CONFIG_SPL_BUILD +static struct socfpga_reset_manager *reset_manager_base = + (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; +static struct socfpga_sdr_ctrl *sdr_ctrl = + (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; + static void socfpga_sdram_apply_static_cfg(void) { const u32 applymask = 0x8; @@ -321,7 +323,7 @@ static void socfpga_sdram_apply_static_cfg(void) : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc"); } -int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (argc != 2) return CMD_RET_USAGE; @@ -357,3 +359,4 @@ U_BOOT_CMD( "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" "" ); +#endif |