sh: mpr2: Remove the board

Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Mark Jonas <mark.jonas@de.bosch.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

8 files changed, 0 insertions, 379 deletions

diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 0659fbbf8b..ea48ecb9a1 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -24,10 +24,6 @@ choice
 	prompt "Target select"
 	optional
 
-config TARGET_MPR2
-	bool "Magic Panel Release 2 board"
-	select CPU_SH3
-
 config TARGET_MS7720SE
 	bool "Support ms7720se"
 	select CPU_SH3
@@ -101,7 +97,6 @@ source "arch/sh/lib/Kconfig"
 
 source "board/alphaproject/ap_sh4a_4a/Kconfig"
 source "board/espt/Kconfig"
-source "board/mpr2/Kconfig"
 source "board/ms7720se/Kconfig"
 source "board/ms7722se/Kconfig"
 source "board/ms7750se/Kconfig"
diff --git a/board/mpr2/Kconfig b/board/mpr2/Kconfig
deleted file mode 100644
index 54176e8f6f..0000000000
--- a/board/mpr2/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MPR2
-
-config SYS_BOARD
-	default "mpr2"
-
-config SYS_CONFIG_NAME
-	default "mpr2"
-
-endif
diff --git a/board/mpr2/MAINTAINERS b/board/mpr2/MAINTAINERS
deleted file mode 100644
index beedf8dda6..0000000000
--- a/board/mpr2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPR2 BOARD
-M:	Mark Jonas <mark.jonas@de.bosch.com>
-S:	Maintained
-F:	board/mpr2/
-F:	include/configs/mpr2.h
-F:	configs/mpr2_defconfig
diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile
deleted file mode 100644
index 6a71803ac7..0000000000
--- a/board/mpr2/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# (C) Copyright 2008
-# Mark Jonas <mark.jonas@de.bosch.com>
-#
-# board/mpr2/Makefile
-#
-
-obj-y	:= mpr2.o
-extra-y	+= lowlevel_init.o
diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S
deleted file mode 100644
index e34a7a9a17..0000000000
--- a/board/mpr2/lowlevel_init.S
+++ /dev/null
@@ -1,117 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008
- * Mark Jonas <mark.jonas@de.bosch.com>
- *
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * board/mpr2/lowlevel_init.S
- */
-#include <asm/macro.h>
-
-	.global	lowlevel_init
-
-	.text
-	.align	2
-
-lowlevel_init:
-
-/*
- * Set frequency multipliers and dividers in FRQCR.
- */
-	write16	WTCSR_A, WTCSR_D
-
-	write16	WTCNT_A, WTCNT_D
-
-	write16	FRQCR_A, FRQCR_D
-
-/*
- * Setup CS0 (Flash).
- */
-	write32	CS0BCR_A, CS0BCR_D
-
-	write32	CS0WCR_A, CS0WCR_D
-
-/*
- * Setup CS3 (SDRAM).
- */
-	write32	CS3BCR_A, CS3BCR_D
-
-	write32	CS3WCR_A, CS3WCR_D
-
-	write32	SDCR_A, SDCR_D1
-
-	write32	RTCSR_A, RTCSR_D
-
-	write32	RTCNT_A, RTCNT_D
-
-	write32	RTCOR_A, RTCOR_D
-
-	write32	SDCR_A, SDCR_D2
-
-	mov.l	SDMR3_A, r1
-	mov.l	SDMR3_D, r0
-	add	r0, r1
-	mov	#0, r0
-	mov.w	r0, @r1
-
-	rts
-	nop
-
-	.align 4
-
-/*
- * Configuration for MPR2 A.3 through A.7
- */
-
-/*
- * PLL Settings
- */
-FRQCR_D:	.word	0x1103		/* I:B:P=8:4:2 */
-WTCNT_D:	.word	0x5A00		/* start counting at zero */
-WTCSR_D:	.word	0xA507		/* divide by 4096 */
-.align 2
-/*
- * Spansion S29GL256N11 @ 48 MHz
- */
-/* 1 idle cycle inserted, normal space, 16 bit */
-CS0BCR_D:	.long	0x12490400
-/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
-CS0WCR_D:	.long	0x00000340
-
-/*
- * Samsung K4S511632B-UL75 @ 48 MHz
- * Micron MT48LC32M16A2-75 @ 48 MHz
- */
-/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
-CS3BCR_D:	.long	0x10004400
-/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
-CS3WCR_D:	.long	0x00000091
-/* no refresh, 13 rows, 10 cols, NO bank active mode */
-SDCR_D1:	.long	0x00000012
-SDCR_D2:	.long	0x00000812	/* refresh */
-RTCSR_D:	.long	0xA55A0008	/* 1/4, once */
-RTCNT_D:	.long	0xA55A005D	/* count 93 */
-RTCOR_D:	.long	0xa55a005d	/* count 93 */
-/* mode register CL2, burst read and SINGLE WRITE */
-SDMR3_D:	.long	0x440
-
-/*
- * Registers
- */
-
-FRQCR_A:	.long	0xA415FF80
-WTCNT_A:	.long	0xA415FF84
-WTCSR_A:	.long	0xA415FF86
-
-#define BSC_BASE	0xA4FD0000
-CS0BCR_A:	.long	BSC_BASE + 0x04
-CS3BCR_A:	.long	BSC_BASE + 0x0C
-CS0WCR_A:	.long	BSC_BASE + 0x24
-CS3WCR_A:	.long	BSC_BASE + 0x2C
-SDCR_A:		.long	BSC_BASE + 0x44
-RTCSR_A:	.long	BSC_BASE + 0x48
-RTCNT_A:	.long	BSC_BASE + 0x4C
-RTCOR_A:	.long	BSC_BASE + 0x50
-SDMR3_A:	.long	BSC_BASE + 0x5000
diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c
deleted file mode 100644
index 9eb04907a4..0000000000
--- a/board/mpr2/mpr2.c
+++ /dev/null
@@ -1,137 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008
- * Mark Jonas <mark.jonas@de.bosch.com>
- *
- * board/mpr2/mpr2.c
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
-	puts("BOARD: MPR2\n");
-	return 0;
-}
-
-int board_init(void)
-{
-	/*
-	 * For MPR2 A.3 through A.7
-	 */
-
-	/* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */
-	__raw_writel(0x36db0400, CS2BCR);    /* 4 idle cycles, normal space, 16 bit data bus */
-	__raw_writel(0x000003c0, CS2WCR);    /* (WR:8), no ext. wait */
-
-	/* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */
-	__raw_writel(0x00000200, CS4BCR);    /* no idle cycles, normal space, 8 bit data bus */
-	__raw_writel(0x00100981, CS4WCR);    /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-
-	/* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */
-	__raw_writel(0x00000200, CS5ABCR);   /* no idle cycles, normal space, 8 bit data bus */
-	__raw_writel(0x00100981, CS5AWCR);   /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-
-	/* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */
-	__raw_writel(0x00000200, CS5BBCR);   /* no idle cycles, normal space, 8 bit data bus */
-	__raw_writel(0x00100981, CS5BWCR);   /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-
-	/* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */
-	__raw_writel(0x00000200, CS6ABCR);   /* no idle cycles, normal space, 8 bit data bus */
-	__raw_writel(0x001009C1, CS6AWCR);   /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
-
-	/* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */
-	__raw_writew(0xAABC, PSELA);  /*    10        10        10        10       10    11    11             00 */
-
-	/* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */
-	__raw_writew(0x3C00, PSELB);  /*       0           0         11         11        0        0  00000000 */
-
-	/* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */
-	__raw_writew(0x0000, PSELC);  /*     00         00         00         00  00000000 */
-
-	/* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */
-	__raw_writew(0x0000, PSELD);  /*     0         00        00          00        00          00        00         00         0 */
-
-	/* OTH:  (00) Other fuction
-	 * GPO:  (01) General Purpose Output
-	 * GPI:  (11) General Purpose Input
-	 * GPI+: (10) General Purpose Input with internal pull-up
-	 *-------------------------------------------------------
-	 * A7 GPO(LED8);     A6 GPO(LED7);     A5 GPO(LED6);        A4 GPO(LED5);
-	 * A3 GPO(LED4);     A2 GPO(LED3);     A1 GPO(LED2);        A0 GPO(LED1); */
-	__raw_writew(0x5555, PACR);   /* 01 01 01 01 01 01 01 01 */
-
-	/* B7 GPO(RST4);     B6 GPO(RST3);     B5 GPO(RST2);        B4 GPO(RST1);
-	 * B3 GPO(PB3);      B2 GPO(PB2);      B1 GPO(PB1);         B0 GPO(PB0); */
-	__raw_writew(0x5555, PBCR);   /* 01 01 01 01 01 01 01 01 */
-
-	/* C7 GPO(PC7);      C6 GPO(PC6);      C5 GPO(PC5);         C4 GPO(PC4);
-	 * C3 LCD_DATA3;     C2 LCD_DATA2;     C1 LCD_DATA1;        C0 LCD_DATA0; */
-	__raw_writew(0x5500, PCCR);   /* 01 01 01 01 00 00 00 00 */
-
-	/* D7 GPO(PD7);      D6 GPO(PD6);      D5 GPO(PD5);         D4 GPO(PD4);
-	 * D3 GPO(PD3);      D2 GPO(PD2);      D1 GPO(PD1);         D0 GPO(PD0); */
-	__raw_writew(0x5555, PDCR);   /* 01 01 01 01 01 01 01 01 */
-
-	/* E7 (x);           E6 GPI(nu);       E5 GPI(nu);          E4 LCD_M_DISP;
-	 * E3 LCD_CL1;       E2 LCD_CL2;       E1 LCD_DON;          E0 LCD_FLM; */
-	__raw_writew(0x2800, PECR);   /* 00 10 10 00 00 00 00 00 */
-
-	/* F7 (x);           F6 DA1(VLCD);     F5 DA0(nc);          F4 AN3;
-	 * F3 AN2(MID_AD);   F2 AN1(EARTH_AD); F1 AN0(TEMP);        F0 GPI+(nc); */
-	__raw_writew(0x0002, PFCR);   /* 00 00 00 00 00 00 00 10 */
-
-	/* G7 (x);          G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2);
-	 * G3 GPI(KEY1);     G2 GPO(LED11);      G1 GPO(LED10);     G0 GPO(LED9); */
-	__raw_writew(0x03D5, PGCR);   /* 00 00 00 11 11 01 01 01 */
-
-	/* H7 (x);            H6 /RAS(BRAS);      H5 /CAS(BCAS);    H4 CKE(BCKE);
-	 * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR;      H0 USB1_PWR; */
-	__raw_writew(0x0050, PHCR);   /* 00 00 00 00 01 01 00 00 */
-
-	/* J7 (x);           J6 AUDCK;         J5 ASEBRKAK;         J4 AUDATA3;
-	 * J3 AUDATA2;       J2 AUDATA1;       J1 AUDATA0;          J0 AUDSYNC; */
-	__raw_writew(0x0000, PJCR);   /* 00 00 00 00 00 00 00 00 */
-
-	/* K7 (x);           K6 (x);           K5 (x);              K4 (x)
-	 * K3 PINT7(/PWR2);  K2 PINT6(/PWR1);  K1 PINT5(nc);        K0 PINT4(FLASH_READY); */
-	__raw_writew(0x00FB, PKCR);   /* 00 00 00 00 11 11 10 11 */
-
-	/* L7 TRST;          L6 TMS;           L5 TDO;              L4 TDI;
-	 * L3 TCK;           L2 (x);           L1 (x);              L0 (x); */
-	__raw_writew(0x0000, PLCR);    /* 00 00 00 00 00 00 00 00 */
-
-	/* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH);  M5 GPO(LAN_SPEED);   M4 GPO(LAN_RESET);
-	 * M3 GPO(BUZZER);      M2 GPO(LCD_BL);      M1 CS5B(CAN3_CS);    M0 GPI+(nc); */
-	__raw_writew(0x5552, PMCR);   /* 01 01 01 01 01 01 00 10 */
-	__raw_writeb(0xF0, PMDR);     /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */
-
-	/* P7 (x);           P6 (x);           P5 (x);              P4 GPO(on pullup);
-	 * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ);   P0 IRQ0(CAN1_IRQ); */
-	__raw_writew(0x0100, PPCR);   /* 00 00 00 01 00 00 00 00 */
-	__raw_writeb(0x10, PPDR);     /* no current flow through pullup */
-
-	/* R7 A25;           R6 A24;           R5 A23;              R4 A22;
-	 * R3 A21;           R2 A20;           R1 A19;              R0 A0; */
-	__raw_writew(0x0000, PRCR);   /* 00 00 00 00 00 00 00 00 */
-
-	/* S7 (x);              S6 (x);        S5 (x);              S4 GPO(EEPROM_CS2);
-	 * S3 GPO(EEPROM_CS1);  S2 SIOF0_TXD;  S1 SIOF0_RXD;        S0 SIOF0_SCK; */
-	__raw_writew(0x0140, PSCR);   /* 00 00 00 01 01 00 00 00 */
-
-	/* T7 (x);           T6 (x);           T5 (x);              T4 COM1_CTS;
-	 * T3 COM1_RTS;      T2 COM1_TXD;      T1 COM1_RXD;         T0 GPO(WDOG); */
-	__raw_writew(0x0001, PTCR);   /* 00 00 00 00 00 00 00 01 */
-
-	/* U7 (x);           U6 (x);           U5 (x);              U4 GPI+(/AC_FAULT);
-	 * U3 GPO(TOUCH_CS); U2 TOUCH_TXD;     U1 TOUCH_RXD;        U0 TOUCH_SCK; */
-	__raw_writew(0x0240, PUCR);   /* 00 00 00 10 01 00 00 00 */
-
-	/* V7 (x);           V6 (x);           V5 (x);              V4 GPO(MID2);
-	 * V3 GPO(MID1);     V2 CARD_TxD;      V1 CARD_RxD;         V0 GPI+(/BAT_FAULT); */
-	__raw_writew(0x0142, PVCR);   /* 00 00 00 01 01 00 00 10 */
-
-	return 0;
-}
diff --git a/configs/mpr2_defconfig b/configs/mpr2_defconfig
deleted file mode 100644
index 3e50c555ca..0000000000
--- a/configs/mpr2_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FFC0000
-CONFIG_TARGET_MPR2=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_MISC is not set
-# CONFIG_NET is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
deleted file mode 100644
index e8594966e0..0000000000
--- a/include/configs/mpr2.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for MPR2
- *
- * Copyright (C) 2008
- * Mark Jonas <mark.jonas@de.bosch.com>
- */
-
-#ifndef __MPR2_H
-#define __MPR2_H
-
-/* Supported commands */
-
-/* Default environment variables */
-#define CONFIG_BOOTFILE		"/boot/zImage"
-#define CONFIG_LOADADDR		0x8E000000
-
-/* CPU and platform */
-#define CONFIG_CPU_SH7720	1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* U-Boot internals */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
-
-/* Memory */
-#define CONFIG_SYS_SDRAM_BASE		0x8C000000
-#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
-
-/* Flash */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BASE		0xA0000000
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
-#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-
-/* Clocks */
-#define CONFIG_SYS_CLK_FREQ	24000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* UART */
-#define CONFIG_CONS_SCIF0	1
-
-#endif	/* __MPR2_H */