diff options
author | Bai Ping <ping.bai@nxp.com> | 2018-07-18 18:01:00 +0800 |
---|---|---|
committer | Bai Ping <ping.bai@nxp.com> | 2018-07-20 17:46:03 +0800 |
commit | 72a06ef47c7c93de49730261adb8f251612d1883 (patch) | |
tree | 21f4a67def4c1fabfac2214ec17d635293999d47 | |
parent | 220d0cc79a3f340e0da664242bb19ccda7a071d1 (diff) |
MLK-18431-03 imx8mm_evk: use the more generic dram init flow on imx8mm evk
Refact the lpddr4 init flow on i.MX8MM EVK board. board level only need
to provide the necessary dram init related parameter.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
-rw-r--r-- | arch/arm/cpu/armv8/imx8m/Kconfig | 1 | ||||
-rw-r--r-- | board/freescale/imx8mm_evk/Makefile | 2 | ||||
-rwxr-xr-x | board/freescale/imx8mm_evk/ddr/Makefile | 13 | ||||
-rw-r--r-- | board/freescale/imx8mm_evk/ddr/ddr.h | 60 | ||||
-rw-r--r-- | board/freescale/imx8mm_evk/ddr/helper.c | 104 | ||||
-rw-r--r-- | board/freescale/imx8mm_evk/ddr/lpddr4_cfg_umctl2_m845.c | 255 | ||||
-rw-r--r-- | board/freescale/imx8mm_evk/ddr/lpddr4_define.h | 161 | ||||
-rw-r--r-- | board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_task.c | 154 | ||||
-rw-r--r-- | board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_train_3000mts_fw09.c | 943 | ||||
-rw-r--r-- | board/freescale/imx8mm_evk/ddr/lpddr4_pmu_training_3000mts_fw09.c | 167 | ||||
-rw-r--r-- | board/freescale/imx8mm_evk/lpddr4_timing.c | 1980 | ||||
-rw-r--r-- | board/freescale/imx8mm_evk/spl.c | 4 |
12 files changed, 1984 insertions, 1860 deletions
diff --git a/arch/arm/cpu/armv8/imx8m/Kconfig b/arch/arm/cpu/armv8/imx8m/Kconfig index dbbd8410077..d344afd22d1 100644 --- a/arch/arm/cpu/armv8/imx8m/Kconfig +++ b/arch/arm/cpu/armv8/imx8m/Kconfig @@ -50,6 +50,7 @@ config TARGET_IMX8MM_EVK bool "imx8mm evk" select IMX8MM select SUPPORT_SPL + select IMX8M_LPDDR4 endchoice diff --git a/board/freescale/imx8mm_evk/Makefile b/board/freescale/imx8mm_evk/Makefile index db8ccaa4b60..237be25c525 100644 --- a/board/freescale/imx8mm_evk/Makefile +++ b/board/freescale/imx8mm_evk/Makefile @@ -8,5 +8,5 @@ obj-y += imx8mm_evk.o ifdef CONFIG_SPL_BUILD obj-y += spl.o -obj-y += ddr/ +obj-y += lpddr4_timing.o endif diff --git a/board/freescale/imx8mm_evk/ddr/Makefile b/board/freescale/imx8mm_evk/ddr/Makefile deleted file mode 100755 index 2b9ee4e7115..00000000000 --- a/board/freescale/imx8mm_evk/ddr/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2018 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y += helper.o -obj-y += lpddr4_cfg_umctl2_m845.o -obj-y += lpddr4_phyinit_train_3000mts_fw09.o -obj-y += lpddr4_pmu_training_3000mts_fw09.o -obj-y += lpddr4_phyinit_task.o -endif diff --git a/board/freescale/imx8mm_evk/ddr/ddr.h b/board/freescale/imx8mm_evk/ddr/ddr.h deleted file mode 100644 index 2de9fadbec5..00000000000 --- a/board/freescale/imx8mm_evk/ddr/ddr.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2018 NXP - * - * SPDX-License-Identifier: GPL-2.0+ - * Common file for ddr code - */ - -#ifndef __M845S_DDR_H_ -#define __M845S_DDR_H_ - -#ifdef DDR_DEBUG -#define ddr_dbg(fmt, ...) printf("DDR: debug:" fmt "\n", ##__VA_ARGS__) -#else -#define ddr_dbg(fmt, ...) -#endif - -/******************************************************************* - Desc: user data type - - *******************************************************************/ -enum fw_type { - FW_1D_IMAGE, - FW_2D_IMAGE, -}; -/******************************************************************* - Desc: prototype - - *******************************************************************/ -void ddr_init(void); -void lpddr4_3000mts_cfg_umctl2(void); -void ddr_load_train_code(enum fw_type type); -void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate); -void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void); -void dwc_ddrphy_phyinit_userCustom_customPostTrain(void); -void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(void); -void dwc_ddrphy_phyinit_userCustom_A_bringupPower(void); -void dwc_ddrphy_phyinit_userCustom_overrideUserInput(void); -void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned long run_2D); -int dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void); -void lpddr4_750M_cfg_phy(void); - -/******************************************************************* - Desc: definition - - *******************************************************************/ -static inline void reg32_write(unsigned long addr, u32 val) -{ - writel(val, addr); -} - -static inline uint32_t reg32_read(unsigned long addr) -{ - return readl(addr); -} - -static inline void reg32setbit(unsigned long addr, u32 bit) -{ - setbits_le32(addr, (1 << bit)); -} -#endif diff --git a/board/freescale/imx8mm_evk/ddr/helper.c b/board/freescale/imx8mm_evk/ddr/helper.c deleted file mode 100644 index 639188c07cd..00000000000 --- a/board/freescale/imx8mm_evk/ddr/helper.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2018 NXP - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <spl.h> -#include <asm/io.h> -#include <errno.h> -#include <asm/io.h> -#include <asm/arch/ddr_memory_map.h> -#include <asm/sections.h> - -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define IMEM_LEN 32768//23400 //byte -#define DMEM_LEN 16384//1720 //byte -#define IMEM_2D_OFFSET 49152 - -#define IMEM_OFFSET_ADDR 0x00050000 -#define DMEM_OFFSET_ADDR 0x00054000 -#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) - -/* We need PHY iMEM PHY is 32KB padded */ -void ddr_load_train_code(enum fw_type type) -{ - u32 tmp32, i; - u32 error = 0; - unsigned long pr_to32, pr_from32; - unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; - unsigned long imem_start = (unsigned long)&_end + fw_offset; - unsigned long dmem_start = imem_start + IMEM_LEN; - - pr_from32 = imem_start; - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; - for(i = 0x0; i < IMEM_LEN; ){ - tmp32 = readl(pr_from32); - writew(tmp32 & 0x0000ffff, pr_to32); - pr_to32 += 4; - writew((tmp32 >> 16) & 0x0000ffff, pr_to32); - pr_to32 += 4; - pr_from32 += 4; - i += 4; - } - - pr_from32 = dmem_start; - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; - for(i = 0x0; i < DMEM_LEN;){ - tmp32 = readl(pr_from32); - writew(tmp32 & 0x0000ffff, pr_to32); - pr_to32 += 4; - writew((tmp32 >> 16) & 0x0000ffff, pr_to32); - pr_to32 += 4; - pr_from32 += 4; - i += 4; - } - - printf("check ddr4_pmu_train_imem code\n"); - pr_from32 = imem_start; - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; - for(i = 0x0; i < IMEM_LEN;){ - tmp32 = (readw(pr_to32) & 0x0000ffff); - pr_to32 += 4; - tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); - - if(tmp32 != readl(pr_from32)){ - printf("%lx %lx\n", pr_from32, pr_to32); - error++; - } - pr_from32 += 4; - pr_to32 += 4; - i += 4; - } - if(error){ - printf("check ddr4_pmu_train_imem code fail=%d\n",error); - }else{ - printf("check ddr4_pmu_train_imem code pass\n"); - } - - printf("check ddr4_pmu_train_dmem code\n"); - pr_from32 = dmem_start; - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; - for(i = 0x0; i < DMEM_LEN;){ - tmp32 = (readw(pr_to32) & 0x0000ffff); - pr_to32 += 4; - tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); - if(tmp32 != readl(pr_from32)){ - printf("%lx %lx\n", pr_from32, pr_to32); - error++; - } - pr_from32 += 4; - pr_to32 += 4; - i += 4; - } - - if(error){ - printf("check ddr4_pmu_train_dmem code fail=%d",error); - }else{ - printf("check ddr4_pmu_train_dmem code pass\n"); - } -} diff --git a/board/freescale/imx8mm_evk/ddr/lpddr4_cfg_umctl2_m845.c b/board/freescale/imx8mm_evk/ddr/lpddr4_cfg_umctl2_m845.c deleted file mode 100644 index c027446dae3..00000000000 --- a/board/freescale/imx8mm_evk/ddr/lpddr4_cfg_umctl2_m845.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright 2018 NXP - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <errno.h> -#include <asm/io.h> -#include <asm/arch/ddr_memory_map.h> -#include <asm/arch/clock.h> -#include "lpddr4_define.h" - -struct ddr_ctl_param -{ - u32 reg; /*reg address */ - u32 val; /*config param */ -}; - -static struct ddr_ctl_param ctl_init_cfg[] = -{ - { .reg =DDRC_DBG1(0), .val = 0x00000001}, - { .reg =DDRC_PWRCTL(0), .val = 0x00000001}, -#ifdef DDR_ONE_RANK - { .reg =DDRC_MSTR(0), .val = 0xa1080020}, -#else - { .reg =DDRC_MSTR(0), .val = 0xa3080020}, -#endif -#ifdef DDR_800M_CFG - { .reg =DDRC_RFSHTMG(0), .val = 0x006100E0}, -#else - { .reg =DDRC_RFSHTMG(0), .val = 0x005b00d2}, -#endif -#ifdef PHY_TRAIN - { .reg =DDRC_INIT0(0), .val = 0xC003061B}, -#else -#ifdef DDR_FAST_SIM - { .reg =DDRC_INIT0(0), .val = 0x00030003}, -#else - { .reg =DDRC_INIT0(0), .val = 0x0003061B}, -#endif -#endif -#ifdef DDR_FAST_SIM - { .reg =DDRC_INIT1(0), .val = 0x00060000}, -#else - { .reg =DDRC_INIT1(0), .val = 0x009D0000}, -#endif - { .reg =DDRC_INIT3(0), .val = 0x00D4002D}, -#ifdef WR_POST_EXT_3200 - { .reg =DDRC_INIT4(0), .val = 0x00330008}, -#else - - { .reg =DDRC_INIT4(0), .val = 0x00310000}, -#endif - { .reg =DDRC_INIT6(0), .val = 0x0066004a}, - { .reg =DDRC_INIT7(0), .val = 0x0006004a}, - - { .reg =DDRC_DRAMTMG0(0), .val = 0x1A201B22}, - { .reg =DDRC_DRAMTMG1(0), .val = 0x00060633}, - { .reg =DDRC_DRAMTMG3(0), .val = 0x00C0C000}, - { .reg =DDRC_DRAMTMG4(0), .val = 0x0F04080F}, - { .reg =DDRC_DRAMTMG5(0), .val = 0x02040C0C}, - { .reg =DDRC_DRAMTMG6(0), .val = 0x01010007}, - { .reg =DDRC_DRAMTMG7(0), .val = 0x00000401}, - { .reg =DDRC_DRAMTMG12(0), .val = 0x00020600}, - { .reg =DDRC_DRAMTMG13(0), .val = 0x0C100002}, - { .reg =DDRC_DRAMTMG14(0), .val = 0x000000E6}, - { .reg =DDRC_DRAMTMG17(0), .val = 0x00A00050}, - - { .reg =DDRC_ZQCTL0(0), .val = 0x03200018}, - { .reg =DDRC_ZQCTL1(0), .val = 0x028061A8}, - { .reg =DDRC_ZQCTL2(0), .val = 0x00000000}, - - { .reg =DDRC_DFITMG0(0), .val = 0x0497820A}, - { .reg =DDRC_DFITMG1(0), .val = 0x00080303}, - { .reg =DDRC_DFIUPD0(0), .val = 0xE0400018}, - - { .reg =DDRC_DFIUPD1(0), .val = 0x00DF00E4}, - { .reg =DDRC_DFIUPD2(0), .val = 0x80000000}, - { .reg =DDRC_DFIMISC(0), .val = 0x00000011}, - { .reg =DDRC_DFITMG2(0), .val = 0x0000170A}, - - { .reg =DDRC_DBICTL(0), .val = 0x00000001}, -#ifdef BUG_WR_DFI - { .reg =DDRC_DFIPHYMSTR(0), .val = 0x00000000}, -#else - { .reg =DDRC_DFIPHYMSTR(0), .val = 0x00000001}, -#endif - { .reg =DDRC_RANKCTL(0), .val = 0x00000c99}, - { .reg =DDRC_DRAMTMG2(0), .val = 0x070E171a}, -#ifdef M845S_4GBx2 -#ifdef DDR_ONE_RANK - { .reg =DDRC_ADDRMAP0(0), .val = 0x0000001f}, -#else - { .reg =DDRC_ADDRMAP0(0), .val = 0x00000017}, -#endif - { .reg =DDRC_ADDRMAP1(0), .val = 0x00080808}, - { .reg =DDRC_ADDRMAP2(0), .val = 0x00000000}, - { .reg =DDRC_ADDRMAP3(0), .val = 0x00000000}, - { .reg =DDRC_ADDRMAP4(0), .val = 0x00001f1f}, - { .reg =DDRC_ADDRMAP5(0), .val = 0x07070707}, - { .reg =DDRC_ADDRMAP6(0), .val = 0x07070707}, - { .reg =DDRC_ADDRMAP7(0), .val = 0x00000f0f}, -#else -#ifdef DDR_ONE_RANK - { .reg =DDRC_ADDRMAP0(0), .val = 0x0000001f}, -#else - { .reg =DDRC_ADDRMAP0(0), .val = 0x00000016}, -#endif - { .reg =DDRC_ADDRMAP1(0), .val = 0x00080808}, - { .reg =DDRC_ADDRMAP2(0), .val = 0x00000000}, - { .reg =DDRC_ADDRMAP3(0), .val = 0x00000000}, - { .reg =DDRC_ADDRMAP4(0), .val = 0x00001f1f}, - { .reg =DDRC_ADDRMAP5(0), .val = 0x07070707}, - { .reg =DDRC_ADDRMAP6(0), .val = 0x0f070707}, - { .reg =DDRC_ADDRMAP7(0), .val = 0x00000f0f}, - { .reg =DDRC_ADDRMAP8(0), .val = 0x00000000}, - { .reg =DDRC_ADDRMAP9(0), .val = 0x0a020b06}, - { .reg =DDRC_ADDRMAP10(0), .val = 0x0a0a0a0a}, - { .reg =DDRC_ADDRMAP11(0), .val = 0x00000000}, -#endif - -#ifdef PERF_TEST_2 - { .reg =DDRC_SCHED(0), .val = 0x29001701}, - { .reg =DDRC_SCHED1(0), .val = 0x0000002c}, - { .reg =DDRC_PERFLPR1(0), .val = 0x900093e7}, - { .reg =DDRC_PCCFG(0), .val = 0x00000111}, - { .reg =DDRC_PCFGW_0(0), .val = 0x000072ff}, - { .reg =DDRC_PCFGQOS0_0(0), .val = 0x02100e07}, - { .reg =DDRC_PCFGQOS1_0(0), .val = 0x00620096}, - { .reg =DDRC_PCFGWQOS0_0(0), .val = 0x01100e07}, - { .reg =DDRC_PCFGWQOS1_0(0), .val = 0x0000012c}, -#else - { .reg =DDRC_SCHED(0), .val = 0x29001701}, - { .reg =DDRC_SCHED1(0), .val = 0x0000002c}, - { .reg =DDRC_PERFHPR1(0), .val = 0x04000030}, - { .reg =DDRC_PERFLPR1(0), .val = 0x900093e7}, - { .reg =DDRC_PCCFG(0), .val = 0x00000111}, - { .reg =DDRC_PCFGW_0(0), .val = 0x000072ff}, - { .reg =DDRC_PCFGQOS0_0(0), .val = 0x02100e07}, - { .reg =DDRC_PCFGQOS1_0(0), .val = 0x00620096}, - { .reg =DDRC_PCFGWQOS0_0(0), .val = 0x01100e07}, - { .reg =DDRC_PCFGWQOS1_0(0), .val = 0x0000012c}, -#endif - -#ifdef P1_400 - { .reg =DDRC_FREQ1_DRAMTMG0(0), .val = 0x0d0b010c}, - { .reg =DDRC_FREQ1_DRAMTMG1(0), .val = 0x00030410}, - { .reg =DDRC_FREQ1_DRAMTMG2(0), .val = 0x0305090c}, - { .reg =DDRC_FREQ1_DRAMTMG3(0), .val = 0x00505006}, - { .reg =DDRC_FREQ1_DRAMTMG4(0), .val = 0x05040305}, - { .reg =DDRC_FREQ1_DRAMTMG5(0), .val = 0x0d0e0504}, - { .reg =DDRC_FREQ1_DRAMTMG6(0), .val = 0x0a060004}, - { .reg =DDRC_FREQ1_DRAMTMG7(0), .val = 0x0000090e}, - { .reg =DDRC_FREQ1_DRAMTMG14(0), .val = 0x00000032}, - { .reg =DDRC_FREQ1_DRAMTMG15(0), .val = 0x00000000}, - { .reg =DDRC_FREQ1_DRAMTMG17(0), .val = 0x0036001b}, - { .reg =DDRC_FREQ1_DERATEINT(0), .val = 0x7e9fbeb1}, - { .reg =DDRC_FREQ1_DFITMG0(0), .val = 0x03818200}, - { .reg =DDRC_FREQ1_DFITMG2(0), .val = 0x00000000}, - { .reg =DDRC_FREQ1_RFSHTMG(0), .val = 0x000C001c}, - { .reg =DDRC_FREQ1_INIT3(0), .val = 0x00840000}, - { .reg =DDRC_FREQ1_INIT4(0), .val = 0x00310000}, - { .reg =DDRC_FREQ1_INIT6(0), .val = 0x0066004a}, - { .reg =DDRC_FREQ1_INIT7(0), .val = 0x0006004a}, -#else -#ifdef WEI_667 - { .reg =DDRC_FREQ1_DRAMTMG0(0), .val = 0x0d0b0107}, - { .reg =DDRC_FREQ1_DRAMTMG1(0), .val = 0x00030410}, - { .reg =DDRC_FREQ1_DRAMTMG2(0), .val = 0x0305080c}, - { .reg =DDRC_FREQ1_DRAMTMG3(0), .val = 0x00505006}, - { .reg =DDRC_FREQ1_DRAMTMG4(0), .val = 0x05040305}, - { .reg =DDRC_FREQ1_DRAMTMG5(0), .val = 0x0f0b0504}, - { .reg =DDRC_FREQ1_DRAMTMG6(0), .val = 0x0e0c000c}, - { .reg =DDRC_FREQ1_DRAMTMG7(0), .val = 0x00000607}, - { .reg =DDRC_FREQ1_DRAMTMG14(0), .val = 0x00000066}, - { .reg =DDRC_FREQ1_DRAMTMG15(0), .val = 0x80000000}, - { .reg =DDRC_FREQ1_DRAMTMG17(0), .val = 0x0036001b}, - { .reg =DDRC_FREQ1_DFITMG0(0), .val = 0x03858202}, - { .reg =DDRC_FREQ1_DFITMG2(0), .val = 0x00000502}, - { .reg =DDRC_FREQ1_DERATEEN(0), .val = 0x00000001}, - { .reg =DDRC_FREQ1_DERATEINT(0), .val = 0x2545eb1c}, - { .reg =DDRC_FREQ1_RFSHTMG(0), .val = 0x0014002f}, - { .reg =DDRC_FREQ1_INIT3(0), .val = 0x00140009}, - { .reg =DDRC_FREQ1_INIT4(0), .val = 0x00310000}, - { .reg =DDRC_FREQ1_INIT6(0), .val = 0x0066004d}, - { .reg =DDRC_FREQ1_INIT7(0), .val = 0x0006004d}, -#else - { .reg =DDRC_FREQ1_DERATEEN(0), .val = 0x0000000}, - { .reg =DDRC_FREQ1_DERATEINT(0), .val = 0x0800000}, - { .reg =DDRC_FREQ1_RFSHCTL0(0), .val = 0x0210000}, - { .reg =DDRC_FREQ1_RFSHTMG(0), .val = 0x014001E}, - { .reg =DDRC_FREQ1_INIT3(0), .val = 0x0140009}, - { .reg =DDRC_FREQ1_INIT4(0), .val = 0x00310000}, - { .reg =DDRC_FREQ1_INIT6(0), .val = 0x0066004a}, - { .reg =DDRC_FREQ1_INIT7(0), .val = 0x0006004a}, - { .reg =DDRC_FREQ1_DRAMTMG0(0), .val = 0xB070A07}, - { .reg =DDRC_FREQ1_DRAMTMG1(0), .val = 0x003040A}, - { .reg =DDRC_FREQ1_DRAMTMG2(0), .val = 0x305080C}, - { .reg =DDRC_FREQ1_DRAMTMG3(0), .val = 0x0505000}, - { .reg =DDRC_FREQ1_DRAMTMG4(0), .val = 0x3040203}, - { .reg =DDRC_FREQ1_DRAMTMG5(0), .val = 0x2030303}, - { .reg =DDRC_FREQ1_DRAMTMG6(0), .val = 0x2020004}, - { .reg =DDRC_FREQ1_DRAMTMG7(0), .val = 0x0000302}, - { .reg =DDRC_FREQ1_DRAMTMG12(0), .val = 0x0020310}, - { .reg =DDRC_FREQ1_DRAMTMG13(0), .val = 0xA100002}, - { .reg =DDRC_FREQ1_DRAMTMG14(0), .val = 0x0000020}, - { .reg =DDRC_FREQ1_DRAMTMG17(0), .val = 0x0220011}, - { .reg =DDRC_FREQ1_ZQCTL0(0), .val = 0x0A70005}, - { .reg =DDRC_FREQ1_DFITMG0(0), .val = 0x3858202}, - { .reg =DDRC_FREQ1_DFITMG1(0), .val = 0x0000404}, - { .reg =DDRC_FREQ1_DFITMG2(0), .val = 0x0000502}, -#endif -#endif - { .reg =DDRC_FREQ2_DRAMTMG0(0), .val = 0x0d0b010c}, - { .reg =DDRC_FREQ2_DRAMTMG1(0), .val = 0x00030410}, - { .reg =DDRC_FREQ2_DRAMTMG2(0), .val = 0x0305090c}, - { .reg =DDRC_FREQ2_DRAMTMG3(0), .val = 0x00505006}, - { .reg =DDRC_FREQ2_DRAMTMG4(0), .val = 0x05040305}, - { .reg =DDRC_FREQ2_DRAMTMG5(0), .val = 0x0d0e0504}, - { .reg =DDRC_FREQ2_DRAMTMG6(0), .val = 0x0a060004}, - { .reg =DDRC_FREQ2_DRAMTMG7(0), .val = 0x0000090e}, - { .reg =DDRC_FREQ2_DRAMTMG14(0), .val = 0x00000032}, - { .reg =DDRC_FREQ2_DRAMTMG17(0), .val = 0x0036001b}, - { .reg =DDRC_FREQ2_DERATEINT(0), .val = 0x7e9fbeb1}, - { .reg =DDRC_FREQ2_DFITMG0(0), .val = 0x03818200}, - { .reg =DDRC_FREQ2_DFITMG2(0), .val = 0x00000000}, - { .reg =DDRC_FREQ2_RFSHTMG(0), .val = 0x00030007}, - { .reg =DDRC_FREQ2_INIT3(0), .val = 0x00840000}, - { .reg =DDRC_FREQ2_INIT4(0), .val = 0x00310000}, - { .reg =DDRC_FREQ2_INIT6(0), .val = 0x0066004a}, - { .reg =DDRC_FREQ2_INIT7(0), .val = 0x0006004a}, -#ifdef DDR_BOOT_P2 - { .reg =DDRC_MSTR2(0), .val = 0x2}, -#else -#ifdef DDR_BOOT_P1 - { .reg =DDRC_MSTR2(0), .val = 0x1}, -#else - { .reg =DDRC_MSTR2(0), .val = 0x0}, -#endif -#endif -}; - -void lpddr4_3000mts_cfg_umctl2(void) -{ - u32 index, reg, val, num; - - num = sizeof(ctl_init_cfg)/sizeof(struct ddr_ctl_param); - - for (index = 0; index < num; index++) { - val = ctl_init_cfg[index].val; - reg = ctl_init_cfg[index].reg; - writel(val, (void __iomem *)(u64)reg); - } -} diff --git a/board/freescale/imx8mm_evk/ddr/lpddr4_define.h b/board/freescale/imx8mm_evk/ddr/lpddr4_define.h deleted file mode 100644 index 712edf6b987..00000000000 --- a/board/freescale/imx8mm_evk/ddr/lpddr4_define.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright 2018 NXP - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef LPDDR4_DEFINE_H -#define LPDDR4_DEFINE_H - -#include "ddr.h" - -#define RUN_ON_SILICON -#define DFI_BUG_WR -#define DEVINIT_PHY - -#define DDR_ONE_RANK -#define BUG_WR_DFI -#define M845S_4GBx2 - -#ifdef LPDDR4_667MTS -#define P0_667 -#endif -#ifdef LPDDR4_1600MTS -#define P0_1600 -#endif -#ifdef LPDDR4_DVFS -#define DVFS_TEST -#define PHY_TRAIN -#define DDR_BOOT_P1 -#endif -#ifdef LPDDR4_RETENTION -#define NORMAL_RET_EN -#endif - -#ifdef P0_667 -#define P0_DRATE 667 -#else -#ifdef P0_1600 -#define P0_DRATE 1600 -#else -#define P0_DRATE 3000 -#endif -#endif - -#define P1_DRATE 667 -#define P2_DRATE 100 - -#ifdef RUN_ON_SILICON -#define PHY_TRAIN -#define ADD_P0_2D_BF_P1 -#ifdef HWFFC -#define ADD_TRAIN_1D_P2 -#endif -#else -#define DDR_FAST_SIM -#endif - -#ifdef PHY_TRAIN -#define ADD_TRAIN_1D_P0 -#ifdef DVFS_TEST -#define ADD_TRAIN_1D_P1 -#endif -#endif - -/* define BOOT FREQ, not modify */ -#ifdef DDR_BOOT_P1 -#define BOOT_FREQ P1_DRATE -#else -#ifdef DDR_BOOT_P2 -#define BOOT_FREQ P2_DRATE -#else -#define BOOT_FREQ P0_DRATE -#endif -#endif - -/* #define P1_FREQ 167 */ -#ifdef PHY_TRAIN -#define CLOCK_SWITCH_PLL P0_DRATE -#else -#define CLOCK_SWITCH_PLL BOOT_FREQ -#endif - -#define DDR_CSD2_BASE_ADDR 0x80000000 -#define GPC_PU_PWRHSK 0x303A01FC - -//---------------------------------------------------------------- -// PHY training feature -//---------------------------------------------------------------- -#define LPDDR4_HDT_CTL_2D 0xC8 //stage completion -#define LPDDR4_HDT_CTL_3200_1D 0xC8 //stage completion -#define LPDDR4_HDT_CTL_400_1D 0xC8 //stage completion -#define LPDDR4_HDT_CTL_100_1D 0xC8 //stage completion - -#define LPDDR4_HDT_CTL_2D 0xC8 //stage completion -#define LPDDR4_HDT_CTL_3200_1D 0xC8 //stage completion -#define LPDDR4_HDT_CTL_400_1D 0xC8 //stage completion -#define LPDDR4_HDT_CTL_100_1D 0xC8 //stage completion - -#ifdef RUN_ON_SILICON -// 400/100 training seq -#define LPDDR4_TRAIN_SEQ_P2 0x121f -#define LPDDR4_TRAIN_SEQ_P1 0x121f -#define LPDDR4_TRAIN_SEQ_P0 0x121f -#else -#define LPDDR4_TRAIN_SEQ_P2 0x7 -#define LPDDR4_TRAIN_SEQ_P1 0x7 -#define LPDDR4_TRAIN_SEQ_P0 0x7 -#endif - -//2D share & weight -#define LPDDR4_2D_WEIGHT 0x1f7f -#define LPDDR4_2D_SHARE 1 -#define LPDDR4_CATRAIN_3200_1d 0 -#define LPDDR4_CATRAIN_400 0 -#define LPDDR4_CATRAIN_100 0 -#define LPDDR4_CATRAIN_3200_2d 0 - -/* MRS parameter */ -/* for LPDDR4 Rtt */ -#define LPDDR4_RTT40 6 -#define LPDDR4_RTT48 5 -#define LPDDR4_RTT60 4 -#define LPDDR4_RTT80 3 -#define LPDDR4_RTT120 2 -#define LPDDR4_RTT240 1 -#define LPDDR4_RTT_DIS 0 - -/* for LPDDR4 Ron */ -#define LPDDR4_RON34 7 -#define LPDDR4_RON40 6 -#define LPDDR4_RON48 5 -#define LPDDR4_RON60 4 -#define LPDDR4_RON80 3 - -#define LPDDR4_PHY_ADDR_RON60 0x1 -#define LPDDR4_PHY_ADDR_RON40 0x3 -#define LPDDR4_PHY_ADDR_RON30 0x7 -#define LPDDR4_PHY_ADDR_RON24 0xf -#define LPDDR4_PHY_ADDR_RON20 0x1f - -/* for read channel */ -#define LPDDR4_RON LPDDR4_RON40 /* MR3[5:3] */ -#define LPDDR4_PHY_RTT 30 /* //30//40//28 */ -/* #define LPDDR4_PHY_VREF_VALUE 27//17//17//20//16///17,//for M845S */ -#define LPDDR4_PHY_VREF_VALUE 17 /*//17//20//16///17,//for M850D*/ - -/* for write channel */ -#define LPDDR4_PHY_RON 30 -#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 -#define LPDDR4_RTT_DQ LPDDR4_RTT40 -#define LPDDR4_RTT_CA LPDDR4_RTT40 -#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 -#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 -#define LPDDR4_VREF_VALUE_CA ((1 << 6)|0xd) -#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6)|0xd) -#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6)|0xd) -#define LPDDR4_MR22_RANK0 ((0 << 5)|(0 << 4)|(0 << 3)|(LPDDR4_RTT40)) -#define LPDDR4_MR22_RANK1 ((1 << 5)|(0 << 4)|(1 << 3)|(LPDDR4_RTT40)) -#define LPDDR4_MR3_PU_CAL 1 - -#endif diff --git a/board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_task.c b/board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_task.c deleted file mode 100644 index d19892f7d1e..00000000000 --- a/board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_task.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright 2018 NXP - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <errno.h> -#include <asm/io.h> -#include <asm/arch/ddr_memory_map.h> -#include <asm/arch/clock.h> -#include "lpddr4_define.h" - -void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate) -{ - if(pstate==2) - dram_pll_init(DRAM_PLL_OUT_100M); - else if(pstate==1) - dram_pll_init(DRAM_PLL_OUT_667M); - else - dram_pll_init(DRAM_PLL_OUT_750M); -} - -int dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void) -{ - volatile unsigned int tmp, tmp_t; - volatile unsigned int train_ok; - volatile unsigned int train_fail; - volatile unsigned int stream_msg; - int ret = 0; - - train_ok = 0; - train_fail = 0; - stream_msg = 0; - while (train_ok == 0 && train_fail == 0) { - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); - tmp_t = tmp & 0x01; - while (tmp_t){ - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); - tmp_t = tmp & 0x01; - } -#ifdef PRINT_PMU - printf("get the training message\n"); -#endif - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); -#ifdef PRINT_PMU - printf("PMU major stream =0x%x\n",tmp); -#endif - if (tmp==0x08) { - stream_msg = 1; - -#ifdef DDR_PRINT_ALL_MESSAGE - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0); - - do { - tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); - }while((tmp_t & 0x1) == 0x0); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1); - - do { - tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); - }while((tmp_t & 0x1) == 0x1); - - /* read_mbox_mssg */ - stream_nb_args = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +4 * 0xd0032); - - /* read_mbox_msb */ - stream_index = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034); - stream_index = (stream_index << 16) | stream_nb_args; -#ifdef PRINT_PMU - printf("PMU stream_index=0x%x nb_args=%d\n",stream_index, stream_nb_args); -#endif - - stream_arg_pos = 0; - while (stream_nb_args > 0) { - /* Need to complete previous handshake first... */ - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0); - /* poll_mbox_from_uc(1); */ - - do { - tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); - } while((tmp_t & 0x1) == 0x0); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1); - - /* Read the next argument... */ - do { - tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); - }while((tmp_t & 0x1) == 0x1); - - /* read_mbox_mssg */ - message = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); - /* read_mbox_msb */ - stream_arg_val = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034); - stream_arg_val = (stream_arg_val << 16) | message; -#ifdef PRINT_PMU - printf("PMU stream_arg[%d]=0x%x\n",stream_arg_pos, stream_arg_val); -#endif - stream_nb_args--; - stream_arg_pos++; - } -#endif - } else if(tmp==0x07) { - train_ok = 1; - ret = 0; - } else if(tmp==0xff) { - train_fail = 1; - printf("%c[31;40m",0x1b); - printf("------- training vt_fail\n"); - printf("%c[0m",0x1b); - - ret = -1; - } else { - train_ok = 0; - train_fail = 0; - stream_msg = 0; - } - - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0); - - if (stream_msg == 1) { - tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034); - tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034); - } - - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); - tmp_t = tmp & 0x01; - while(tmp_t==0){ - tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); - tmp_t = tmp & 0x01; - } - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1); - } - - return ret; -} - -void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned long run_2D) -{ -} - -void dwc_ddrphy_phyinit_userCustom_overrideUserInput(void) -{ -} -void dwc_ddrphy_phyinit_userCustom_A_bringupPower(void) -{ -} -void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(void) -{ -} -void dwc_ddrphy_phyinit_userCustom_customPostTrain(void) -{ -} -void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void) -{ -} diff --git a/board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_train_3000mts_fw09.c b/board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_train_3000mts_fw09.c deleted file mode 100644 index 53fede4371d..00000000000 --- a/board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_train_3000mts_fw09.c +++ /dev/null @@ -1,943 +0,0 @@ -/* - * Copyright 2018 NXP - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <errno.h> -#include <asm/io.h> -#include <asm/arch/ddr_memory_map.h> -#include <asm/arch/clock.h> -#include "lpddr4_define.h" - -struct ddr_phy_param { - u32 reg; /* reg address */ - u32 val; /* config param */ -}; - - -#define DDR_PHY_FLAG_ADDR 0x00187F00 - -static struct ddr_phy_param phy_init_cfg[] = -{ - { .reg = 0x3c000000+4*0x1005f, .val = 0x15f}, - { .reg = 0x3c000000+4*0x1015f, .val = 0x15f}, - { .reg = 0x3c000000+4*0x1105f, .val = 0x15f}, - { .reg = 0x3c000000+4*0x1115f, .val = 0x15f}, - { .reg = 0x3c000000+4*0x1205f, .val = 0x15f}, - { .reg = 0x3c000000+4*0x1215f, .val = 0x15f}, - { .reg = 0x3c000000+4*0x1305f, .val = 0x15f}, - { .reg = 0x3c000000+4*0x1315f, .val = 0x15f}, - { .reg = 0x3c000000+4*0x55, .val = 0x16f}, - { .reg = 0x3c000000+4*0x1055, .val = 0x16f}, - { .reg = 0x3c000000+4*0x2055, .val = 0x16f}, - { .reg = 0x3c000000+4*0x3055, .val = 0x16f}, - { .reg = 0x3c000000+4*0x4055, .val = 0x16f}, - { .reg = 0x3c000000+4*0x5055, .val = 0x16f}, - { .reg = 0x3c000000+4*0x6055, .val = 0x16f}, - { .reg = 0x3c000000+4*0x7055, .val = 0x16f}, - { .reg = 0x3c000000+4*0x8055, .val = 0x16f}, - { .reg = 0x3c000000+4*0x9055, .val = 0x16f}, - { .reg = 0x3c000000+4*0x200c5, .val = 0x19}, - { .reg = 0x3c000000+4*0x2002e, .val = 0x2}, - { .reg = 0x3c000000+4*0x90204, .val = 0x0}, - { .reg = 0x3c000000+4*0x20024, .val = 0xab}, - { .reg = 0x3c000000+4*0x2003a, .val = 0x0}, - { .reg = 0x3c000000+4*0x20056, .val = 0x3}, - { .reg = 0x3c000000+4*0x1004d, .val = 0xe00}, - { .reg = 0x3c000000+4*0x1014d, .val = 0xe00}, - { .reg = 0x3c000000+4*0x1104d, .val = 0xe00}, - { .reg = 0x3c000000+4*0x1114d, .val = 0xe00}, - { .reg = 0x3c000000+4*0x1204d, .val = 0xe00}, - { .reg = 0x3c000000+4*0x1214d, .val = 0xe00}, - { .reg = 0x3c000000+4*0x1304d, .val = 0xe00}, - { .reg = 0x3c000000+4*0x1314d, .val = 0xe00}, - { .reg = 0x3c000000+4*0x10049, .val = 0xfbe}, - { .reg = 0x3c000000+4*0x10149, .val = 0xfbe}, - { .reg = 0x3c000000+4*0x11049, .val = 0xfbe}, - { .reg = 0x3c000000+4*0x11149, .val = 0xfbe}, - { .reg = 0x3c000000+4*0x12049, .val = 0xfbe}, - { .reg = 0x3c000000+4*0x12149, .val = 0xfbe}, - { .reg = 0x3c000000+4*0x13049, .val = 0xfbe}, - { .reg = 0x3c000000+4*0x13149, .val = 0xfbe}, - { .reg = 0x3c000000+4*0x43, .val = 0x63}, - { .reg = 0x3c000000+4*0x1043, .val = 0x63}, - { .reg = 0x3c000000+4*0x2043, .val = 0x63}, - { .reg = 0x3c000000+4*0x3043, .val = 0x63}, - { .reg = 0x3c000000+4*0x4043, .val = 0x63}, - { .reg = 0x3c000000+4*0x5043, .val = 0x63}, - { .reg = 0x3c000000+4*0x6043, .val = 0x63}, - { .reg = 0x3c000000+4*0x7043, .val = 0x63}, - { .reg = 0x3c000000+4*0x8043, .val = 0x63}, - { .reg = 0x3c000000+4*0x9043, .val = 0x63}, - { .reg = 0x3c000000+4*0x20018, .val = 0x3}, - { .reg = 0x3c000000+4*0x20075, .val = 0x4}, - { .reg = 0x3c000000+4*0x20050, .val = 0x0}, - { .reg = 0x3c000000+4*0x20008, .val = 0x2ee}, - { .reg = 0x3c000000+4*0x20088, .val = 0x9}, - { .reg = 0x3c000000+4*0x200b2, .val = 0x1d4}, - { .reg = 0x3c000000+4*0x10043, .val = 0x5a1}, - { .reg = 0x3c000000+4*0x10143, .val = 0x5a1}, - { .reg = 0x3c000000+4*0x11043, .val = 0x5a1}, - { .reg = 0x3c000000+4*0x11143, .val = 0x5a1}, - { .reg = 0x3c000000+4*0x12043, .val = 0x5a1}, - { .reg = 0x3c000000+4*0x12143, .val = 0x5a1}, - { .reg = 0x3c000000+4*0x13043, .val = 0x5a1}, - { .reg = 0x3c000000+4*0x13143, .val = 0x5a1}, - { .reg = 0x3c000000+4*0x200fa, .val = 0x1}, - { .reg = 0x3c000000+4*0x20019, .val = 0x1}, - { .reg = 0x3c000000+4*0x200f0, .val = 0x600}, - { .reg = 0x3c000000+4*0x200f1, .val = 0x0}, - { .reg = 0x3c000000+4*0x200f2, .val = 0x4444}, - { .reg = 0x3c000000+4*0x200f3, .val = 0x8888}, - { .reg = 0x3c000000+4*0x200f4, .val = 0x5655}, - { .reg = 0x3c000000+4*0x200f5, .val = 0x0}, - { .reg = 0x3c000000+4*0x200f6, .val = 0x0}, - { .reg = 0x3c000000+4*0x200f7, .val = 0xf000}, - { .reg = 0x3c000000+4*0x20025, .val = 0x0}, - { .reg = 0x3c000000+4*0x2002d, .val = 0x0}, - { .reg = 0x3c000000+4*0x200c7, .val = 0x21}, - { .reg = 0x3c000000+4*0x200ca, .val = 0x24}, - { .reg = 0x3c000000+4*0x20060, .val = 0x2}, - { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, - { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, - - { .reg = DDR_PHY_FLAG_ADDR, .val = 0x00}, - - { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, - { .reg = DDR_PHY_FLAG_ADDR, .val = 0x01}, - { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, -#ifdef RUN_ON_SILICON - { .reg = 0x3c000000+4*0x54000, .val = 0x0}, -#else - { .reg = 0x3c000000+4*0x54000, .val = 0x600}, -#endif - { .reg = 0x3c000000+4*0x54001, .val = 0x0}, - { .reg = 0x3c000000+4*0x54002, .val = 0x0}, - { .reg = 0x3c000000+4*0x54003, .val = 0xbb8}, - { .reg = 0x3c000000+4*0x54004, .val = 0x2}, - { .reg = 0x3c000000+4*0x54005, .val = ((LPDDR4_PHY_RON<<8)|LPDDR4_PHY_RTT)}, - { .reg = 0x3c000000+4*0x54006, .val = LPDDR4_PHY_VREF_VALUE}, - { .reg = 0x3c000000+4*0x54007, .val = 0x0}, -#ifdef RUN_ON_SILICON - { .reg = 0x3c000000+4*0x54008, .val = 0x131f}, -#else - { .reg = 0x3c000000+4*0x54008, .val = 0x7}, -#endif - { .reg = 0x3c000000+4*0x54009, .val = 0xc8}, - { .reg = 0x3c000000+4*0x5400a, .val = 0x0}, - { .reg = 0x3c000000+4*0x5400b, .val = 0x2}, - { .reg = 0x3c000000+4*0x5400c, .val = 0x0}, - { .reg = 0x3c000000+4*0x5400d, .val = 0x100}, - { .reg = 0x3c000000+4*0x5400e, .val = 0x0}, - { .reg = 0x3c000000+4*0x5400f, .val = 0x0}, - { .reg = 0x3c000000+4*0x54010, .val = 0x0}, - { .reg = 0x3c000000+4*0x54011, .val = 0x0}, -#ifdef DDR_ONE_RANK - { .reg = 0x3c000000+4*0x54012, .val = 0x110}, -#else - { .reg = 0x3c000000+4*0x54012, .val = 0x310}, -#endif - { .reg = 0x3c000000+4*0x54013, .val = 0x0}, - { .reg = 0x3c000000+4*0x54014, .val = 0x0}, - { .reg = 0x3c000000+4*0x54015, .val = 0x0}, - { .reg = 0x3c000000+4*0x54016, .val = 0x0}, - { .reg = 0x3c000000+4*0x54017, .val = 0x0}, - { .reg = 0x3c000000+4*0x54018, .val = 0x0}, - - { .reg = 0x3c000000+4*0x54019, .val = 0x2dd4}, - { .reg = 0x3c000000+4*0x5401a, .val = (((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)/*0x31*/}, - { .reg = 0x3c000000+4*0x5401b, .val = ((LPDDR4_VREF_VALUE_CA<<8)|(LPDDR4_RTT_CA_BANK0<<4)|LPDDR4_RTT_DQ)/*0x4d66*/}, - { .reg = 0x3c000000+4*0x5401c, .val = ((LPDDR4_VREF_VALUE_DQ_RANK0<<8)|0x08)/*0x4d08*/}, - { .reg = 0x3c000000+4*0x5401d, .val = 0x0}, - { .reg = 0x3c000000+4*0x5401e, .val = LPDDR4_MR22_RANK0/*0x16*/}, - { .reg = 0x3c000000+4*0x5401f, .val = 0x2dd4}, - { .reg = 0x3c000000+4*0x54020, .val = (((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)/*0x31*/}, - { .reg = 0x3c000000+4*0x54021, .val = ((LPDDR4_VREF_VALUE_CA<<8)|(LPDDR4_RTT_CA_BANK1<<4)|LPDDR4_RTT_DQ)/*0x4d66*/}, - { .reg = 0x3c000000+4*0x54022, .val = ((LPDDR4_VREF_VALUE_DQ_RANK1<<8)|0x08)/*0x4d08*/}, - { .reg = 0x3c000000+4*0x54023, .val = 0x0}, - { .reg = 0x3c000000+4*0x54024, .val = LPDDR4_MR22_RANK1/*0x16*/}, - - { .reg = 0x3c000000+4*0x54025, .val = 0x0}, - { .reg = 0x3c000000+4*0x54026, .val = 0x0}, - { .reg = 0x3c000000+4*0x54027, .val = 0x0}, - { .reg = 0x3c000000+4*0x54028, .val = 0x0}, - { .reg = 0x3c000000+4*0x54029, .val = 0x0}, - { .reg = 0x3c000000+4*0x5402a, .val = 0x0}, - { .reg = 0x3c000000+4*0x5402b, .val = 0x1000}, -#ifdef DDR_ONE_RANK - { .reg = 0x3c000000+4*0x5402c, .val = 0x1}, -#else - { .reg = 0x3c000000+4*0x5402c, .val = 0x3}, -#endif - { .reg = 0x3c000000+4*0x5402d, .val = 0x0}, - { .reg = 0x3c000000+4*0x5402e, .val = 0x0}, - { .reg = 0x3c000000+4*0x5402f, .val = 0x0}, - { .reg = 0x3c000000+4*0x54030, .val = 0x0}, - { .reg = 0x3c000000+4*0x54031, .val = 0x0}, - - { .reg = 0x3c000000+4*0x54032, .val = 0xd400}, - { .reg = 0x3c000000+4*0x54033, .val = ((((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)<<8)|0x2d/*0x312d*/}, - { .reg = 0x3c000000+4*0x54034, .val = (((LPDDR4_RTT_CA_BANK0<<4)|LPDDR4_RTT_DQ)<<8)/*0x4600*/}, - { .reg = 0x3c000000+4*0x54035, .val = (0x0800|LPDDR4_VREF_VALUE_CA)/*0x084d*/}, - { .reg = 0x3c000000+4*0x54036, .val = LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/}, - { .reg = 0x3c000000+4*0x54037, .val = (LPDDR4_MR22_RANK0<<8)/*0x1600*/}, - { .reg = 0x3c000000+4*0x54038, .val = 0xd400}, - { .reg = 0x3c000000+4*0x54039, .val = ((((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)<<8)|0x2d/*0x312d*/}, - { .reg = 0x3c000000+4*0x5403a, .val = (((LPDDR4_RTT_CA_BANK1<<4)|LPDDR4_RTT_DQ)<<8)/*0x4600*/}, - { .reg = 0x3c000000+4*0x5403b, .val = (0x0800|LPDDR4_VREF_VALUE_CA)/*0x084d*/}, - { .reg = 0x3c000000+4*0x5403c, .val = LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/}, - { .reg = 0x3c000000+4*0x5403d, .val = (LPDDR4_MR22_RANK1<<8)/*0x1600*/}, - { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, - { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, - { .reg = 0x3c000000+4*0xd0099, .val = 0x9}, - { .reg = 0x3c000000+4*0xd0099, .val = 0x1}, - { .reg = 0x3c000000+4*0xd0099, .val = 0x0}, - - { .reg = DDR_PHY_FLAG_ADDR, .val = 0x02}, - - { .reg = 0x3c000000+4*0xd0099, .val = 0x1}, - { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, - - { .reg = DDR_PHY_FLAG_ADDR, .val = 0x03}, - - { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, - - { .reg = DDR_PHY_FLAG_ADDR, .val = 0x04}, - - { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, - { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, - - - - { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, - - { .reg = DDR_PHY_FLAG_ADDR, .val = 0x05}, - - - { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, -#ifdef RUN_ON_SILICON - { .reg = 0x3c000000+4*0x54000, .val = 0x0}, -#else - { .reg = 0x3c000000+4*0x54000, .val = 0x600}, -#endif - { .reg = 0x3c000000+4*0x54001, .val = 0x0}, - { .reg = 0x3c000000+4*0x54002, .val = 0x0}, - { .reg = 0x3c000000+4*0x54003, .val = 0xbb8}, - { .reg = 0x3c000000+4*0x54004, .val = 0x2}, - - { .reg = 0x3c000000+4*0x54005, .val = ((LPDDR4_PHY_RON<<8)|LPDDR4_PHY_RTT)}, - { .reg = 0x3c000000+4*0x54006, .val = LPDDR4_PHY_VREF_VALUE}, - - { .reg = 0x3c000000+4*0x54007, .val = 0x0}, -#ifdef RUN_ON_SILICON - { .reg = 0x3c000000+4*0x54008, .val = 0x61}, -#else - { .reg = 0x3c000000+4*0x54008, .val = 0x1}, -#endif - { .reg = 0x3c000000+4*0x54009, .val = 0xc8}, - { .reg = 0x3c000000+4*0x5400a, .val = 0x0}, - { .reg = 0x3c000000+4*0x5400b, .val = 0x2}, - { .reg = 0x3c000000+4*0x5400c, .val = 0x0}, - { .reg = 0x3c000000+4*0x5400d, .val = 0x100}, - { .reg = 0x3c000000+4*0x5400e, .val = 0x0}, - { .reg = 0x3c000000+4*0x5400f, .val = 0x100}, - - { .reg = 0x3c000000+4*0x54010, .val = LPDDR4_2D_WEIGHT}, - - { .reg = 0x3c000000+4*0x54011, .val = 0x0}, -#ifdef DDR_ONE_RANK - { .reg = 0x3c000000+4*0x54012, .val = 0x110}, -#else - { .reg = 0x3c000000+4*0x54012, .val = 0x310}, -#endif - { .reg = 0x3c000000+4*0x54013, .val = 0x0}, - { .reg = 0x3c000000+4*0x54014, .val = 0x0}, - { .reg = 0x3c000000+4*0x54015, .val = 0x0}, - { .reg = 0x3c000000+4*0x54016, .val = 0x0}, - { .reg = 0x3c000000+4*0x54017, .val = 0x0}, - { .reg = 0x3c000000+4*0x54018, .val = 0x0}, - - { .reg = 0x3c000000+4*0x54019, .val = 0x2dd4}, - { .reg = 0x3c000000+4*0x5401a, .val = (((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)/*0x31*/}, - { .reg = 0x3c000000+4*0x5401b, .val = ((LPDDR4_VREF_VALUE_CA<<8)|(LPDDR4_RTT_CA_BANK0<<4)|LPDDR4_RTT_DQ)/*0x4d46*/}, - { .reg = 0x3c000000+4*0x5401c, .val = ((LPDDR4_VREF_VALUE_DQ_RANK0<<8)|0x08)/*0x4d08*/}, - { .reg = 0x3c000000+4*0x5401d, .val = 0x0}, - { .reg = 0x3c000000+4*0x5401e, .val = LPDDR4_MR22_RANK0/*0x16*/}, - { .reg = 0x3c000000+4*0x5401f, .val = 0x2dd4}, - { .reg = 0x3c000000+4*0x54020, .val = (((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)/*0x31*/}, - { .reg = 0x3c000000+4*0x54021, .val = ((LPDDR4_VREF_VALUE_CA<<8)|(LPDDR4_RTT_CA_BANK1<<4)|LPDDR4_RTT_DQ)/*0x4d46*/}, - { .reg = 0x3c000000+4*0x54022, .val = ((LPDDR4_VREF_VALUE_DQ_RANK1<<8)|0x08)/*0x4d08*/}, - { .reg = 0x3c000000+4*0x54023, .val = 0x0}, - { .reg = 0x3c000000+4*0x54024, .val = LPDDR4_MR22_RANK1/*0x16*/}, - - { .reg = 0x3c000000+4*0x54025, .val = 0x0}, - { .reg = 0x3c000000+4*0x54026, .val = 0x0}, - { .reg = 0x3c000000+4*0x54027, .val = 0x0}, - { .reg = 0x3c000000+4*0x54028, .val = 0x0}, - { .reg = 0x3c000000+4*0x54029, .val = 0x0}, - { .reg = 0x3c000000+4*0x5402a, .val = 0x0}, - { .reg = 0x3c000000+4*0x5402b, .val = 0x1000}, -#ifdef DDR_ONE_RANK - { .reg = 0x3c000000+4*0x5402c, .val = 0x1}, -#else - { .reg = 0x3c000000+4*0x5402c, .val = 0x3}, -#endif - { .reg = 0x3c000000+4*0x5402d, .val = 0x0}, - { .reg = 0x3c000000+4*0x5402e, .val = 0x0}, - { .reg = 0x3c000000+4*0x5402f, .val = 0x0}, - { .reg = 0x3c000000+4*0x54030, .val = 0x0}, - { .reg = 0x3c000000+4*0x54031, .val = 0x0}, - - { .reg = 0x3c000000+4*0x54032, .val = 0xd400}, - { .reg = 0x3c000000+4*0x54033, .val = ((((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)<<8)|0x2d/*0x312d*/}, - { .reg = 0x3c000000+4*0x54034, .val = (((LPDDR4_RTT_CA_BANK0<<4)|LPDDR4_RTT_DQ)<<8)/*0x4600*/}, - { .reg = 0x3c000000+4*0x54035, .val = (0x0800|LPDDR4_VREF_VALUE_CA)/*0x084d*/}, - { .reg = 0x3c000000+4*0x54036, .val = LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/}, - { .reg = 0x3c000000+4*0x54037, .val = (LPDDR4_MR22_RANK0<<8)/*0x1600*/}, - { .reg = 0x3c000000+4*0x54038, .val = 0xd400}, - { .reg = 0x3c000000+4*0x54039, .val = ((((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)<<8)|0x2d/*0x312d*/}, - { .reg = 0x3c000000+4*0x5403a, .val = (((LPDDR4_RTT_CA_BANK1<<4)|LPDDR4_RTT_DQ)<<8)/*0x4600*/}, - { .reg = 0x3c000000+4*0x5403b, .val = (0x0800|LPDDR4_VREF_VALUE_CA)/*0x084d*/}, - { .reg = 0x3c000000+4*0x5403c, .val = LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/}, - { .reg = 0x3c000000+4*0x5403d, .val = (LPDDR4_MR22_RANK1<<8)/*0x1600*/}, - - { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, - { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, - { .reg = 0x3c000000+4*0xd0099, .val = 0x9}, - { .reg = 0x3c000000+4*0xd0099, .val = 0x1}, - { .reg = 0x3c000000+4*0xd0099, .val = 0x0}, - - { .reg = DDR_PHY_FLAG_ADDR, .val = 0x06}, - - { .reg = 0x3c000000+4*0xd0099, .val = 0x1}, - { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, - - { .reg = DDR_PHY_FLAG_ADDR, .val = 0x07}, - - { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, - - { .reg = 0x3c000000+4*0xd0000, .val = 0x0}, - - { .reg = 0x3c000000+4*0x90000, .val = 0x10}, - { .reg = 0x3c000000+4*0x90001, .val = 0x400}, - { .reg = 0x3c000000+4*0x90002, .val = 0x10e}, - { .reg = 0x3c000000+4*0x90003, .val = 0x0}, - { .reg = 0x3c000000+4*0x90004, .val = 0x0}, - { .reg = 0x3c000000+4*0x90005, .val = 0x8}, - { .reg = 0x3c000000+4*0x90029, .val = 0xb}, - { .reg = 0x3c000000+4*0x9002a, .val = 0x480}, - { .reg = 0x3c000000+4*0x9002b, .val = 0x109}, - { .reg = 0x3c000000+4*0x9002c, .val = 0x8}, - { .reg = 0x3c000000+4*0x9002d, .val = 0x448}, - { .reg = 0x3c000000+4*0x9002e, .val = 0x139}, - { .reg = 0x3c000000+4*0x9002f, .val = 0x8}, - { .reg = 0x3c000000+4*0x90030, .val = 0x478}, - { .reg = 0x3c000000+4*0x90031, .val = 0x109}, - { .reg = 0x3c000000+4*0x90032, .val = 0x0}, - { .reg = 0x3c000000+4*0x90033, .val = 0xe8}, - { .reg = 0x3c000000+4*0x90034, .val = 0x109}, - { .reg = 0x3c000000+4*0x90035, .val = 0x2}, - { .reg = 0x3c000000+4*0x90036, .val = 0x10}, - { .reg = 0x3c000000+4*0x90037, .val = 0x139}, - { .reg = 0x3c000000+4*0x90038, .val = 0xf}, - { .reg = 0x3c000000+4*0x90039, .val = 0x7c0}, - { .reg = 0x3c000000+4*0x9003a, .val = 0x139}, - { .reg = 0x3c000000+4*0x9003b, .val = 0x44}, - { .reg = 0x3c000000+4*0x9003c, .val = 0x630}, - { .reg = 0x3c000000+4*0x9003d, .val = 0x159}, - { .reg = 0x3c000000+4*0x9003e, .val = 0x14f}, - { .reg = 0x3c000000+4*0x9003f, .val = 0x630}, - { .reg = 0x3c000000+4*0x90040, .val = 0x159}, - { .reg = 0x3c000000+4*0x90041, .val = 0x47}, - { .reg = 0x3c000000+4*0x90042, .val = 0x630}, - { .reg = 0x3c000000+4*0x90043, .val = 0x149}, - { .reg = 0x3c000000+4*0x90044, .val = 0x4f}, - { .reg = 0x3c000000+4*0x90045, .val = 0x630}, - { .reg = 0x3c000000+4*0x90046, .val = 0x179}, - { .reg = 0x3c000000+4*0x90047, .val = 0x8}, - { .reg = 0x3c000000+4*0x90048, .val = 0xe0}, - { .reg = 0x3c000000+4*0x90049, .val = 0x109}, - { .reg = 0x3c000000+4*0x9004a, .val = 0x0}, - { .reg = 0x3c000000+4*0x9004b, .val = 0x7c8}, - { .reg = 0x3c000000+4*0x9004c, .val = 0x109}, - { .reg = 0x3c000000+4*0x9004d, .val = 0x0}, - { .reg = 0x3c000000+4*0x9004e, .val = 0x1}, - { .reg = 0x3c000000+4*0x9004f, .val = 0x8}, - { .reg = 0x3c000000+4*0x90050, .val = 0x0}, - { .reg = 0x3c000000+4*0x90051, .val = 0x45a}, - { .reg = 0x3c000000+4*0x90052, .val = 0x9}, - { .reg = 0x3c000000+4*0x90053, .val = 0x0}, - { .reg = 0x3c000000+4*0x90054, .val = 0x448}, - { .reg = 0x3c000000+4*0x90055, .val = 0x109}, - { .reg = 0x3c000000+4*0x90056, .val = 0x40}, - { .reg = 0x3c000000+4*0x90057, .val = 0x630}, - { .reg = 0x3c000000+4*0x90058, .val = 0x179}, - { .reg = 0x3c000000+4*0x90059, .val = 0x1}, - { .reg = 0x3c000000+4*0x9005a, .val = 0x618}, - { .reg = 0x3c000000+4*0x9005b, .val = 0x109}, - { .reg = 0x3c000000+4*0x9005c, .val = 0x40c0}, - { .reg = 0x3c000000+4*0x9005d, .val = 0x630}, - { .reg = 0x3c000000+4*0x9005e, .val = 0x149}, - { .reg = 0x3c000000+4*0x9005f, .val = 0x8}, - { .reg = 0x3c000000+4*0x90060, .val = 0x4}, - { .reg = 0x3c000000+4*0x90061, .val = 0x48}, - { .reg = 0x3c000000+4*0x90062, .val = 0x4040}, - { .reg = 0x3c000000+4*0x90063, .val = 0x630}, - { .reg = 0x3c000000+4*0x90064, .val = 0x149}, - { .reg = 0x3c000000+4*0x90065, .val = 0x0}, - { .reg = 0x3c000000+4*0x90066, .val = 0x4}, - { .reg = 0x3c000000+4*0x90067, .val = 0x48}, - { .reg = 0x3c000000+4*0x90068, .val = 0x40}, - { .reg = 0x3c000000+4*0x90069, .val = 0x630}, - { .reg = 0x3c000000+4*0x9006a, .val = 0x149}, - { .reg = 0x3c000000+4*0x9006b, .val = 0x10}, - { .reg = 0x3c000000+4*0x9006c, .val = 0x4}, - { .reg = 0x3c000000+4*0x9006d, .val = 0x18}, - { .reg = 0x3c000000+4*0x9006e, .val = 0x0}, - { .reg = 0x3c000000+4*0x9006f, .val = 0x4}, - { .reg = 0x3c000000+4*0x90070, .val = 0x78}, - { .reg = 0x3c000000+4*0x90071, .val = 0x549}, - { .reg = 0x3c000000+4*0x90072, .val = 0x630}, - { .reg = 0x3c000000+4*0x90073, .val = 0x159}, - { .reg = 0x3c000000+4*0x90074, .val = 0xd49}, - { .reg = 0x3c000000+4*0x90075, .val = 0x630}, - { .reg = 0x3c000000+4*0x90076, .val = 0x159}, - { .reg = 0x3c000000+4*0x90077, .val = 0x94a}, - { .reg = 0x3c000000+4*0x90078, .val = 0x630}, - { .reg = 0x3c000000+4*0x90079, .val = 0x159}, - { .reg = 0x3c000000+4*0x9007a, .val = 0x441}, - { .reg = 0x3c000000+4*0x9007b, .val = 0x630}, - { .reg = 0x3c000000+4*0x9007c, .val = 0x149}, - { .reg = 0x3c000000+4*0x9007d, .val = 0x42}, - { .reg = 0x3c000000+4*0x9007e, .val = 0x630}, - { .reg = 0x3c000000+4*0x9007f, .val = 0x149}, - { .reg = 0x3c000000+4*0x90080, .val = 0x1}, - { .reg = 0x3c000000+4*0x90081, .val = 0x630}, - { .reg = 0x3c000000+4*0x90082, .val = 0x149}, - { .reg = 0x3c000000+4*0x90083, .val = 0x0}, - { .reg = 0x3c000000+4*0x90084, .val = 0xe0}, - { .reg = 0x3c000000+4*0x90085, .val = 0x109}, - { .reg = 0x3c000000+4*0x90086, .val = 0xa}, - { .reg = 0x3c000000+4*0x90087, .val = 0x10}, - { .reg = 0x3c000000+4*0x90088, .val = 0x109}, - { .reg = 0x3c000000+4*0x90089, .val = 0x9}, - { .reg = 0x3c000000+4*0x9008a, .val = 0x3c0}, - { .reg = 0x3c000000+4*0x9008b, .val = 0x149}, - { .reg = 0x3c000000+4*0x9008c, .val = 0x9}, - { .reg = 0x3c000000+4*0x9008d, .val = 0x3c0}, - { .reg = 0x3c000000+4*0x9008e, .val = 0x159}, - { .reg = 0x3c000000+4*0x9008f, .val = 0x18}, - { .reg = 0x3c000000+4*0x90090, .val = 0x10}, - { .reg = 0x3c000000+4*0x90091, .val = 0x109}, - { .reg = 0x3c000000+4*0x90092, .val = 0x0}, - { .reg = 0x3c000000+4*0x90093, .val = 0x3c0}, - { .reg = 0x3c000000+4*0x90094, .val = 0x109}, - { .reg = 0x3c000000+4*0x90095, .val = 0x18}, - { .reg = 0x3c000000+4*0x90096, .val = 0x4}, - { .reg = 0x3c000000+4*0x90097, .val = 0x48}, - { .reg = 0x3c000000+4*0x90098, .val = 0x18}, - { .reg = 0x3c000000+4*0x90099, .val = 0x4}, - { .reg = 0x3c000000+4*0x9009a, .val = 0x58}, - { .reg = 0x3c000000+4*0x9009b, .val = 0xa}, - { .reg = 0x3c000000+4*0x9009c, .val = 0x10}, - { .reg = 0x3c000000+4*0x9009d, .val = 0x109}, - { .reg = 0x3c000000+4*0x9009e, .val = 0x2}, - { .reg = 0x3c000000+4*0x9009f, .val = 0x10}, - { .reg = 0x3c000000+4*0x900a0, .val = 0x109}, - { .reg = 0x3c000000+4*0x900a1, .val = 0x5}, - { .reg = 0x3c000000+4*0x900a2, .val = 0x7c0}, - { .reg = 0x3c000000+4*0x900a3, .val = 0x109}, - { .reg = 0x3c000000+4*0x900a4, .val = 0x10}, - { .reg = 0x3c000000+4*0x900a5, .val = 0x10}, - { .reg = 0x3c000000+4*0x900a6, .val = 0x109}, - { .reg = 0x3c000000+4*0x40000, .val = 0x811}, - { .reg = 0x3c000000+4*0x40020, .val = 0x880}, - { .reg = 0x3c000000+4*0x40040, .val = 0x0}, - { .reg = 0x3c000000+4*0x40060, .val = 0x0}, - { .reg = 0x3c000000+4*0x40001, .val = 0x4008}, - { .reg = 0x3c000000+4*0x40021, .val = 0x83}, - { .reg = 0x3c000000+4*0x40041, .val = 0x4f}, - { .reg = 0x3c000000+4*0x40061, .val = 0x0}, - { .reg = 0x3c000000+4*0x40002, .val = 0x4040}, - { .reg = 0x3c000000+4*0x40022, .val = 0x83}, - { .reg = 0x3c000000+4*0x40042, .val = 0x51}, - { .reg = 0x3c000000+4*0x40062, .val = 0x0}, - { .reg = 0x3c000000+4*0x40003, .val = 0x811}, - { .reg = 0x3c000000+4*0x40023, .val = 0x880}, - { .reg = 0x3c000000+4*0x40043, .val = 0x0}, - { .reg = 0x3c000000+4*0x40063, .val = 0x0}, - { .reg = 0x3c000000+4*0x40004, .val = 0x720}, - { .reg = 0x3c000000+4*0x40024, .val = 0xf}, - { .reg = 0x3c000000+4*0x40044, .val = 0x1740}, - { .reg = 0x3c000000+4*0x40064, .val = 0x0}, - { .reg = 0x3c000000+4*0x40005, .val = 0x16}, - { .reg = 0x3c000000+4*0x40025, .val = 0x83}, - { .reg = 0x3c000000+4*0x40045, .val = 0x4b}, - { .reg = 0x3c000000+4*0x40065, .val = 0x0}, - { .reg = 0x3c000000+4*0x40006, .val = 0x716}, - { .reg = 0x3c000000+4*0x40026, .val = 0xf}, - { .reg = 0x3c000000+4*0x40046, .val = 0x2001}, - { .reg = 0x3c000000+4*0x40066, .val = 0x0}, - { .reg = 0x3c000000+4*0x40007, .val = 0x716}, - { .reg = 0x3c000000+4*0x40027, .val = 0xf}, - { .reg = 0x3c000000+4*0x40047, .val = 0x2800}, - { .reg = 0x3c000000+4*0x40067, .val = 0x0}, - { .reg = 0x3c000000+4*0x40008, .val = 0x716}, - { .reg = 0x3c000000+4*0x40028, .val = 0xf}, - { .reg = 0x3c000000+4*0x40048, .val = 0xf00}, - { .reg = 0x3c000000+4*0x40068, .val = 0x0}, - { .reg = 0x3c000000+4*0x40009, .val = 0x720}, - { .reg = 0x3c000000+4*0x40029, .val = 0xf}, - { .reg = 0x3c000000+4*0x40049, .val = 0x1400}, - { .reg = 0x3c000000+4*0x40069, .val = 0x0}, - { .reg = 0x3c000000+4*0x4000a, .val = 0xe08}, - { .reg = 0x3c000000+4*0x4002a, .val = 0xc15}, - { .reg = 0x3c000000+4*0x4004a, .val = 0x0}, - { .reg = 0x3c000000+4*0x4006a, .val = 0x0}, - { .reg = 0x3c000000+4*0x4000b, .val = 0x623}, - { .reg = 0x3c000000+4*0x4002b, .val = 0x15}, - { .reg = 0x3c000000+4*0x4004b, .val = 0x0}, - { .reg = 0x3c000000+4*0x4006b, .val = 0x0}, - { .reg = 0x3c000000+4*0x4000c, .val = 0x4028}, - { .reg = 0x3c000000+4*0x4002c, .val = 0x80}, - { .reg = 0x3c000000+4*0x4004c, .val = 0x0}, - { .reg = 0x3c000000+4*0x4006c, .val = 0x0}, - { .reg = 0x3c000000+4*0x4000d, .val = 0xe08}, - { .reg = 0x3c000000+4*0x4002d, .val = 0xc1a}, - { .reg = 0x3c000000+4*0x4004d, .val = 0x0}, - { .reg = 0x3c000000+4*0x4006d, .val = 0x0}, - { .reg = 0x3c000000+4*0x4000e, .val = 0x623}, - { .reg = 0x3c000000+4*0x4002e, .val = 0x1a}, - { .reg = 0x3c000000+4*0x4004e, .val = 0x0}, - { .reg = 0x3c000000+4*0x4006e, .val = 0x0}, - { .reg = 0x3c000000+4*0x4000f, .val = 0x4040}, - { .reg = 0x3c000000+4*0x4002f, .val = 0x80}, - { .reg = 0x3c000000+4*0x4004f, .val = 0x0}, - { .reg = 0x3c000000+4*0x4006f, .val = 0x0}, - { .reg = 0x3c000000+4*0x40010, .val = 0x2604}, - { .reg = 0x3c000000+4*0x40030, .val = 0x15}, - { .reg = 0x3c000000+4*0x40050, .val = 0x0}, - { .reg = 0x3c000000+4*0x40070, .val = 0x0}, - { .reg = 0x3c000000+4*0x40011, .val = 0x708}, - { .reg = 0x3c000000+4*0x40031, .val = 0x5}, - { .reg = 0x3c000000+4*0x40051, .val = 0x0}, - { .reg = 0x3c000000+4*0x40071, .val = 0x2002}, - { .reg = 0x3c000000+4*0x40012, .val = 0x8}, - { .reg = 0x3c000000+4*0x40032, .val = 0x80}, - { .reg = 0x3c000000+4*0x40052, .val = 0x0}, - { .reg = 0x3c000000+4*0x40072, .val = 0x0}, - { .reg = 0x3c000000+4*0x40013, .val = 0x2604}, - { .reg = 0x3c000000+4*0x40033, .val = 0x1a}, - { .reg = 0x3c000000+4*0x40053, .val = 0x0}, - { .reg = 0x3c000000+4*0x40073, .val = 0x0}, - { .reg = 0x3c000000+4*0x40014, .val = 0x708}, - { .reg = 0x3c000000+4*0x40034, .val = 0xa}, - { .reg = 0x3c000000+4*0x40054, .val = 0x0}, - { .reg = 0x3c000000+4*0x40074, .val = 0x2002}, - { .reg = 0x3c000000+4*0x40015, .val = 0x4040}, - { .reg = 0x3c000000+4*0x40035, .val = 0x80}, - { .reg = 0x3c000000+4*0x40055, .val = 0x0}, - { .reg = 0x3c000000+4*0x40075, .val = 0x0}, - { .reg = 0x3c000000+4*0x40016, .val = 0x60a}, - { .reg = 0x3c000000+4*0x40036, .val = 0x15}, - { .reg = 0x3c000000+4*0x40056, .val = 0x1200}, - { .reg = 0x3c000000+4*0x40076, .val = 0x0}, - { .reg = 0x3c000000+4*0x40017, .val = 0x61a}, - { .reg = 0x3c000000+4*0x40037, .val = 0x15}, - { .reg = 0x3c000000+4*0x40057, .val = 0x1300}, - { .reg = 0x3c000000+4*0x40077, .val = 0x0}, - { .reg = 0x3c000000+4*0x40018, .val = 0x60a}, - { .reg = 0x3c000000+4*0x40038, .val = 0x1a}, - { .reg = 0x3c000000+4*0x40058, .val = 0x1200}, - { .reg = 0x3c000000+4*0x40078, .val = 0x0}, - { .reg = 0x3c000000+4*0x40019, .val = 0x642}, - { .reg = 0x3c000000+4*0x40039, .val = 0x1a}, - { .reg = 0x3c000000+4*0x40059, .val = 0x1300}, - { .reg = 0x3c000000+4*0x40079, .val = 0x0}, - { .reg = 0x3c000000+4*0x4001a, .val = 0x4808}, - { .reg = 0x3c000000+4*0x4003a, .val = 0x880}, - { .reg = 0x3c000000+4*0x4005a, .val = 0x0}, - { .reg = 0x3c000000+4*0x4007a, .val = 0x0}, - { .reg = 0x3c000000+4*0x900a7, .val = 0x0}, - { .reg = 0x3c000000+4*0x900a8, .val = 0x790}, - { .reg = 0x3c000000+4*0x900a9, .val = 0x11a}, - { .reg = 0x3c000000+4*0x900aa, .val = 0x8}, - { .reg = 0x3c000000+4*0x900ab, .val = 0x7aa}, - { .reg = 0x3c000000+4*0x900ac, .val = 0x2a}, - { .reg = 0x3c000000+4*0x900ad, .val = 0x10}, - { .reg = 0x3c000000+4*0x900ae, .val = 0x7b2}, - { .reg = 0x3c000000+4*0x900af, .val = 0x2a}, - { .reg = 0x3c000000+4*0x900b0, .val = 0x0}, - { .reg = 0x3c000000+4*0x900b1, .val = 0x7c8}, - { .reg = 0x3c000000+4*0x900b2, .val = 0x109}, - { .reg = 0x3c000000+4*0x900b3, .val = 0x10}, - { .reg = 0x3c000000+4*0x900b4, .val = 0x2a8}, - { .reg = 0x3c000000+4*0x900b5, .val = 0x129}, - { .reg = 0x3c000000+4*0x900b6, .val = 0x8}, - { .reg = 0x3c000000+4*0x900b7, .val = 0x370}, - { .reg = 0x3c000000+4*0x900b8, .val = 0x129}, - { .reg = 0x3c000000+4*0x900b9, .val = 0xa}, - { .reg = 0x3c000000+4*0x900ba, .val = 0x3c8}, - { .reg = 0x3c000000+4*0x900bb, .val = 0x1a9}, - { .reg = 0x3c000000+4*0x900bc, .val = 0xc}, - { .reg = 0x3c000000+4*0x900bd, .val = 0x408}, - { .reg = 0x3c000000+4*0x900be, .val = 0x199}, - { .reg = 0x3c000000+4*0x900bf, .val = 0x14}, - { .reg = 0x3c000000+4*0x900c0, .val = 0x790}, - { .reg = 0x3c000000+4*0x900c1, .val = 0x11a}, - { .reg = 0x3c000000+4*0x900c2, .val = 0x8}, - { .reg = 0x3c000000+4*0x900c3, .val = 0x4}, - { .reg = 0x3c000000+4*0x900c4, .val = 0x18}, - { .reg = 0x3c000000+4*0x900c5, .val = 0xe}, - { .reg = 0x3c000000+4*0x900c6, .val = 0x408}, - { .reg = 0x3c000000+4*0x900c7, .val = 0x199}, - { .reg = 0x3c000000+4*0x900c8, .val = 0x8}, - { .reg = 0x3c000000+4*0x900c9, .val = 0x8568}, - { .reg = 0x3c000000+4*0x900ca, .val = 0x108}, - { .reg = 0x3c000000+4*0x900cb, .val = 0x18}, - { .reg = 0x3c000000+4*0x900cc, .val = 0x790}, - { .reg = 0x3c000000+4*0x900cd, .val = 0x16a}, - { .reg = 0x3c000000+4*0x900ce, .val = 0x8}, - { .reg = 0x3c000000+4*0x900cf, .val = 0x1d8}, - { .reg = 0x3c000000+4*0x900d0, .val = 0x169}, - { .reg = 0x3c000000+4*0x900d1, .val = 0x10}, - { .reg = 0x3c000000+4*0x900d2, .val = 0x8558}, - { .reg = 0x3c000000+4*0x900d3, .val = 0x168}, - { .reg = 0x3c000000+4*0x900d4, .val = 0x70}, - { .reg = 0x3c000000+4*0x900d5, .val = 0x788}, - { .reg = 0x3c000000+4*0x900d6, .val = 0x16a}, - { .reg = 0x3c000000+4*0x900d7, .val = 0x1ff8}, - { .reg = 0x3c000000+4*0x900d8, .val = 0x85a8}, - { .reg = 0x3c000000+4*0x900d9, .val = 0x1e8}, - { .reg = 0x3c000000+4*0x900da, .val = 0x50}, - { .reg = 0x3c000000+4*0x900db, .val = 0x798}, - { .reg = 0x3c000000+4*0x900dc, .val = 0x16a}, - { .reg = 0x3c000000+4*0x900dd, .val = 0x60}, - { .reg = 0x3c000000+4*0x900de, .val = 0x7a0}, - { .reg = 0x3c000000+4*0x900df, .val = 0x16a}, - { .reg = 0x3c000000+4*0x900e0, .val = 0x8}, - { .reg = 0x3c000000+4*0x900e1, .val = 0x8310}, - { .reg = 0x3c000000+4*0x900e2, .val = 0x168}, - { .reg = 0x3c000000+4*0x900e3, .val = 0x8}, - { .reg = 0x3c000000+4*0x900e4, .val = 0xa310}, - { .reg = 0x3c000000+4*0x900e5, .val = 0x168}, - { .reg = 0x3c000000+4*0x900e6, .val = 0xa}, - { .reg = 0x3c000000+4*0x900e7, .val = 0x408}, - { .reg = 0x3c000000+4*0x900e8, .val = 0x169}, - { .reg = 0x3c000000+4*0x900e9, .val = 0x6e}, - { .reg = 0x3c000000+4*0x900ea, .val = 0x0}, - { .reg = 0x3c000000+4*0x900eb, .val = 0x68}, - { .reg = 0x3c000000+4*0x900ec, .val = 0x0}, - { .reg = 0x3c000000+4*0x900ed, .val = 0x408}, - { .reg = 0x3c000000+4*0x900ee, .val = 0x169}, - { .reg = 0x3c000000+4*0x900ef, .val = 0x0}, - { .reg = 0x3c000000+4*0x900f0, .val = 0x8310}, - { .reg = 0x3c000000+4*0x900f1, .val = 0x168}, - { .reg = 0x3c000000+4*0x900f2, .val = 0x0}, - { .reg = 0x3c000000+4*0x900f3, .val = 0xa310}, - { .reg = 0x3c000000+4*0x900f4, .val = 0x168}, - { .reg = 0x3c000000+4*0x900f5, .val = 0x1ff8}, - { .reg = 0x3c000000+4*0x900f6, .val = 0x85a8}, - { .reg = 0x3c000000+4*0x900f7, .val = 0x1e8}, - { .reg = 0x3c000000+4*0x900f8, .val = 0x68}, - { .reg = 0x3c000000+4*0x900f9, .val = 0x798}, - { .reg = 0x3c000000+4*0x900fa, .val = 0x16a}, - { .reg = 0x3c000000+4*0x900fb, .val = 0x78}, - { .reg = 0x3c000000+4*0x900fc, .val = 0x7a0}, - { .reg = 0x3c000000+4*0x900fd, .val = 0x16a}, - { .reg = 0x3c000000+4*0x900fe, .val = 0x68}, - { .reg = 0x3c000000+4*0x900ff, .val = 0x790}, - { .reg = 0x3c000000+4*0x90100, .val = 0x16a}, - { .reg = 0x3c000000+4*0x90101, .val = 0x8}, - { .reg = 0x3c000000+4*0x90102, .val = 0x8b10}, - { .reg = 0x3c000000+4*0x90103, .val = 0x168}, - { .reg = 0x3c000000+4*0x90104, .val = 0x8}, - { .reg = 0x3c000000+4*0x90105, .val = 0xab10}, - { .reg = 0x3c000000+4*0x90106, .val = 0x168}, - { .reg = 0x3c000000+4*0x90107, .val = 0xa}, - { .reg = 0x3c000000+4*0x90108, .val = 0x408}, - { .reg = 0x3c000000+4*0x90109, .val = 0x169}, - { .reg = 0x3c000000+4*0x9010a, .val = 0x58}, - { .reg = 0x3c000000+4*0x9010b, .val = 0x0}, - { .reg = 0x3c000000+4*0x9010c, .val = 0x68}, - { .reg = 0x3c000000+4*0x9010d, .val = 0x0}, - { .reg = 0x3c000000+4*0x9010e, .val = 0x408}, - { .reg = 0x3c000000+4*0x9010f, .val = 0x169}, - { .reg = 0x3c000000+4*0x90110, .val = 0x0}, - { .reg = 0x3c000000+4*0x90111, .val = 0x8b10}, - { .reg = 0x3c000000+4*0x90112, .val = 0x168}, - { .reg = 0x3c000000+4*0x90113, .val = 0x0}, - { .reg = 0x3c000000+4*0x90114, .val = 0xab10}, - { .reg = 0x3c000000+4*0x90115, .val = 0x168}, - { .reg = 0x3c000000+4*0x90116, .val = 0x0}, - { .reg = 0x3c000000+4*0x90117, .val = 0x1d8}, - { .reg = 0x3c000000+4*0x90118, .val = 0x169}, - { .reg = 0x3c000000+4*0x90119, .val = 0x80}, - { .reg = 0x3c000000+4*0x9011a, .val = 0x790}, - { .reg = 0x3c000000+4*0x9011b, .val = 0x16a}, - { .reg = 0x3c000000+4*0x9011c, .val = 0x18}, - { .reg = 0x3c000000+4*0x9011d, .val = 0x7aa}, - { .reg = 0x3c000000+4*0x9011e, .val = 0x6a}, - { .reg = 0x3c000000+4*0x9011f, .val = 0xa}, - { .reg = 0x3c000000+4*0x90120, .val = 0x0}, - { .reg = 0x3c000000+4*0x90121, .val = 0x1e9}, - { .reg = 0x3c000000+4*0x90122, .val = 0x8}, - { .reg = 0x3c000000+4*0x90123, .val = 0x8080}, - { .reg = 0x3c000000+4*0x90124, .val = 0x108}, - { .reg = 0x3c000000+4*0x90125, .val = 0xf}, - { .reg = 0x3c000000+4*0x90126, .val = 0x408}, - { .reg = 0x3c000000+4*0x90127, .val = 0x169}, - { .reg = 0x3c000000+4*0x90128, .val = 0xc}, - { .reg = 0x3c000000+4*0x90129, .val = 0x0}, - { .reg = 0x3c000000+4*0x9012a, .val = 0x68}, - { .reg = 0x3c000000+4*0x9012b, .val = 0x9}, - { .reg = 0x3c000000+4*0x9012c, .val = 0x0}, - { .reg = 0x3c000000+4*0x9012d, .val = 0x1a9}, - { .reg = 0x3c000000+4*0x9012e, .val = 0x0}, - { .reg = 0x3c000000+4*0x9012f, .val = 0x408}, - { .reg = 0x3c000000+4*0x90130, .val = 0x169}, - { .reg = 0x3c000000+4*0x90131, .val = 0x0}, - { .reg = 0x3c000000+4*0x90132, .val = 0x8080}, - { .reg = 0x3c000000+4*0x90133, .val = 0x108}, - { .reg = 0x3c000000+4*0x90134, .val = 0x8}, - { .reg = 0x3c000000+4*0x90135, .val = 0x7aa}, - { .reg = 0x3c000000+4*0x90136, .val = 0x6a}, - { .reg = 0x3c000000+4*0x90137, .val = 0x0}, - { .reg = 0x3c000000+4*0x90138, .val = 0x8568}, - { .reg = 0x3c000000+4*0x90139, .val = 0x108}, - { .reg = 0x3c000000+4*0x9013a, .val = 0xb7}, - { .reg = 0x3c000000+4*0x9013b, .val = 0x790}, - { .reg = 0x3c000000+4*0x9013c, .val = 0x16a}, - { .reg = 0x3c000000+4*0x9013d, .val = 0x1f}, - { .reg = 0x3c000000+4*0x9013e, .val = 0x0}, - { .reg = 0x3c000000+4*0x9013f, .val = 0x68}, - { .reg = 0x3c000000+4*0x90140, .val = 0x8}, - { .reg = 0x3c000000+4*0x90141, .val = 0x8558}, - { .reg = 0x3c000000+4*0x90142, .val = 0x168}, - { .reg = 0x3c000000+4*0x90143, .val = 0xf}, - { .reg = 0x3c000000+4*0x90144, .val = 0x408}, - { .reg = 0x3c000000+4*0x90145, .val = 0x169}, - { .reg = 0x3c000000+4*0x90146, .val = 0xc}, - { .reg = 0x3c000000+4*0x90147, .val = 0x0}, - { .reg = 0x3c000000+4*0x90148, .val = 0x68}, - { .reg = 0x3c000000+4*0x90149, .val = 0x0}, - { .reg = 0x3c000000+4*0x9014a, .val = 0x408}, - { .reg = 0x3c000000+4*0x9014b, .val = 0x169}, - { .reg = 0x3c000000+4*0x9014c, .val = 0x0}, - { .reg = 0x3c000000+4*0x9014d, .val = 0x8558}, - { .reg = 0x3c000000+4*0x9014e, .val = 0x168}, - { .reg = 0x3c000000+4*0x9014f, .val = 0x8}, - { .reg = 0x3c000000+4*0x90150, .val = 0x3c8}, - { .reg = 0x3c000000+4*0x90151, .val = 0x1a9}, - { .reg = 0x3c000000+4*0x90152, .val = 0x3}, - { .reg = 0x3c000000+4*0x90153, .val = 0x370}, - { .reg = 0x3c000000+4*0x90154, .val = 0x129}, - { .reg = 0x3c000000+4*0x90155, .val = 0x20}, - { .reg = 0x3c000000+4*0x90156, .val = 0x2aa}, - { .reg = 0x3c000000+4*0x90157, .val = 0x9}, - { .reg = 0x3c000000+4*0x90158, .val = 0x0}, - { .reg = 0x3c000000+4*0x90159, .val = 0x400}, - { .reg = 0x3c000000+4*0x9015a, .val = 0x10e}, - { .reg = 0x3c000000+4*0x9015b, .val = 0x8}, - { .reg = 0x3c000000+4*0x9015c, .val = 0xe8}, - { .reg = 0x3c000000+4*0x9015d, .val = 0x109}, - { .reg = 0x3c000000+4*0x9015e, .val = 0x0}, - { .reg = 0x3c000000+4*0x9015f, .val = 0x8140}, - { .reg = 0x3c000000+4*0x90160, .val = 0x10c}, - { .reg = 0x3c000000+4*0x90161, .val = 0x10}, - { .reg = 0x3c000000+4*0x90162, .val = 0x8138}, - { .reg = 0x3c000000+4*0x90163, .val = 0x10c}, - { .reg = 0x3c000000+4*0x90164, .val = 0x8}, - { .reg = 0x3c000000+4*0x90165, .val = 0x7c8}, - { .reg = 0x3c000000+4*0x90166, .val = 0x101}, - { .reg = 0x3c000000+4*0x90167, .val = 0x8}, - { .reg = 0x3c000000+4*0x90168, .val = 0x0}, - { .reg = 0x3c000000+4*0x90169, .val = 0x8}, - { .reg = 0x3c000000+4*0x9016a, .val = 0x8}, - { .reg = 0x3c000000+4*0x9016b, .val = 0x448}, - { .reg = 0x3c000000+4*0x9016c, .val = 0x109}, - { .reg = 0x3c000000+4*0x9016d, .val = 0xf}, - { .reg = 0x3c000000+4*0x9016e, .val = 0x7c0}, - { .reg = 0x3c000000+4*0x9016f, .val = 0x109}, - { .reg = 0x3c000000+4*0x90170, .val = 0x0}, - { .reg = 0x3c000000+4*0x90171, .val = 0xe8}, - { .reg = 0x3c000000+4*0x90172, .val = 0x109}, - { .reg = 0x3c000000+4*0x90173, .val = 0x47}, - { .reg = 0x3c000000+4*0x90174, .val = 0x630}, - { .reg = 0x3c000000+4*0x90175, .val = 0x109}, - { .reg = 0x3c000000+4*0x90176, .val = 0x8}, - { .reg = 0x3c000000+4*0x90177, .val = 0x618}, - { .reg = 0x3c000000+4*0x90178, .val = 0x109}, - { .reg = 0x3c000000+4*0x90179, .val = 0x8}, - { .reg = 0x3c000000+4*0x9017a, .val = 0xe0}, - { .reg = 0x3c000000+4*0x9017b, .val = 0x109}, - { .reg = 0x3c000000+4*0x9017c, .val = 0x0}, - { .reg = 0x3c000000+4*0x9017d, .val = 0x7c8}, - { .reg = 0x3c000000+4*0x9017e, .val = 0x109}, - { .reg = 0x3c000000+4*0x9017f, .val = 0x8}, - { .reg = 0x3c000000+4*0x90180, .val = 0x8140}, - { .reg = 0x3c000000+4*0x90181, .val = 0x10c}, - { .reg = 0x3c000000+4*0x90182, .val = 0x0}, - { .reg = 0x3c000000+4*0x90183, .val = 0x1}, - { .reg = 0x3c000000+4*0x90184, .val = 0x8}, - { .reg = 0x3c000000+4*0x90185, .val = 0x8}, - { .reg = 0x3c000000+4*0x90186, .val = 0x4}, - { .reg = 0x3c000000+4*0x90187, .val = 0x8}, - { .reg = 0x3c000000+4*0x90188, .val = 0x8}, - { .reg = 0x3c000000+4*0x90189, .val = 0x7c8}, - { .reg = 0x3c000000+4*0x9018a, .val = 0x101}, - { .reg = 0x3c000000+4*0x90006, .val = 0x0}, - { .reg = 0x3c000000+4*0x90007, .val = 0x0}, - { .reg = 0x3c000000+4*0x90008, .val = 0x8}, - { .reg = 0x3c000000+4*0x90009, .val = 0x0}, - { .reg = 0x3c000000+4*0x9000a, .val = 0x0}, - { .reg = 0x3c000000+4*0x9000b, .val = 0x0}, - { .reg = 0x3c000000+4*0xd00e7, .val = 0x400}, - { .reg = 0x3c000000+4*0x90017, .val = 0x0}, - { .reg = 0x3c000000+4*0x9001f, .val = 0x2a}, - { .reg = 0x3c000000+4*0x90026, .val = 0x6a}, - { .reg = 0x3c000000+4*0x400d0, .val = 0x0}, - { .reg = 0x3c000000+4*0x400d1, .val = 0x101}, - { .reg = 0x3c000000+4*0x400d2, .val = 0x105}, - { .reg = 0x3c000000+4*0x400d3, .val = 0x107}, - { .reg = 0x3c000000+4*0x400d4, .val = 0x10f}, - { .reg = 0x3c000000+4*0x400d5, .val = 0x202}, - { .reg = 0x3c000000+4*0x400d6, .val = 0x20a}, - { .reg = 0x3c000000+4*0x400d7, .val = 0x20b}, - { .reg = 0x3c000000+4*0x2003a, .val = 0x2}, - { .reg = 0x3c000000+4*0x2000b, .val = 0x5d}, - { .reg = 0x3c000000+4*0x2000c, .val = 0xbb}, - { .reg = 0x3c000000+4*0x2000d, .val = 0x753}, - { .reg = 0x3c000000+4*0x2000e, .val = 0x2c}, - { .reg = 0x3c000000+4*0x9000c, .val = 0x0}, - { .reg = 0x3c000000+4*0x9000d, .val = 0x173}, - { .reg = 0x3c000000+4*0x9000e, .val = 0x60}, - { .reg = 0x3c000000+4*0x9000f, .val = 0x6110}, - { .reg = 0x3c000000+4*0x90010, .val = 0x2152}, - { .reg = 0x3c000000+4*0x90011, .val = 0xdfbd}, - { .reg = 0x3c000000+4*0x90012, .val = 0x60}, - { .reg = 0x3c000000+4*0x90013, .val = 0x6152}, - { .reg = 0x3c000000+4*0x20010, .val = 0x5a}, - { .reg = 0x3c000000+4*0x20011, .val = 0x3}, - { .reg = 0x3c000000+4*0x40080, .val = 0xe0}, - { .reg = 0x3c000000+4*0x40081, .val = 0x12}, - { .reg = 0x3c000000+4*0x40082, .val = 0xe0}, - { .reg = 0x3c000000+4*0x40083, .val = 0x12}, - { .reg = 0x3c000000+4*0x40084, .val = 0xe0}, - { .reg = 0x3c000000+4*0x40085, .val = 0x12}, - { .reg = 0x3c000000+4*0x400fd, .val = 0xf}, - { .reg = 0x3c000000+4*0x10011, .val = 0x1}, - { .reg = 0x3c000000+4*0x10012, .val = 0x1}, - { .reg = 0x3c000000+4*0x10013, .val = 0x180}, - { .reg = 0x3c000000+4*0x10018, .val = 0x1}, - { .reg = 0x3c000000+4*0x10002, .val = 0x6209}, - { .reg = 0x3c000000+4*0x100b2, .val = 0x1}, - { .reg = 0x3c000000+4*0x101b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x102b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x103b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x104b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x105b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x106b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x107b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x108b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x11011, .val = 0x1}, - { .reg = 0x3c000000+4*0x11012, .val = 0x1}, - { .reg = 0x3c000000+4*0x11013, .val = 0x180}, - { .reg = 0x3c000000+4*0x11018, .val = 0x1}, - { .reg = 0x3c000000+4*0x11002, .val = 0x6209}, - { .reg = 0x3c000000+4*0x110b2, .val = 0x1}, - { .reg = 0x3c000000+4*0x111b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x112b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x113b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x114b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x115b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x116b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x117b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x118b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x12011, .val = 0x1}, - { .reg = 0x3c000000+4*0x12012, .val = 0x1}, - { .reg = 0x3c000000+4*0x12013, .val = 0x180}, - { .reg = 0x3c000000+4*0x12018, .val = 0x1}, - { .reg = 0x3c000000+4*0x12002, .val = 0x6209}, - { .reg = 0x3c000000+4*0x120b2, .val = 0x1}, - { .reg = 0x3c000000+4*0x121b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x122b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x123b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x124b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x125b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x126b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x127b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x128b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x13011, .val = 0x1}, - { .reg = 0x3c000000+4*0x13012, .val = 0x1}, - { .reg = 0x3c000000+4*0x13013, .val = 0x180}, - { .reg = 0x3c000000+4*0x13018, .val = 0x1}, - { .reg = 0x3c000000+4*0x13002, .val = 0x6209}, - { .reg = 0x3c000000+4*0x130b2, .val = 0x1}, - { .reg = 0x3c000000+4*0x131b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x132b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x133b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x134b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x135b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x136b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x137b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x138b4, .val = 0x1}, - { .reg = 0x3c000000+4*0x2003a, .val = 0x2}, - { .reg = 0x3c000000+4*0xc0080, .val = 0x2}, - { .reg = 0x3c000000+4*0xd0000, .val = 0x1}, - { .reg = DDR_PHY_FLAG_ADDR, .val = 0x08}, -}; - - - -void lpddr4_750M_cfg_phy(void) -{ - uint32_t index, reg, val, num; - - num = sizeof(phy_init_cfg)/sizeof(struct ddr_phy_param); - - dwc_ddrphy_phyinit_userCustom_overrideUserInput(); - dwc_ddrphy_phyinit_userCustom_A_bringupPower(); - dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(); - - for (index = 0; index < num; index++) { - val = phy_init_cfg[index].val; - reg = phy_init_cfg[index].reg; - writel(val,(void __iomem *)(u64)reg); - if(reg == DDR_PHY_FLAG_ADDR) { - switch(val) { - case 0x00: - dwc_ddrphy_phyinit_userCustom_E_setDfiClk(0); - break; - case 0x01: - ddr_load_train_code(FW_1D_IMAGE); - break; - case 0x02: - dwc_ddrphy_phyinit_userCustom_G_waitFwDone(); - break; - case 0x03: - dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(0); - break; - case 0x04: - dwc_ddrphy_phyinit_userCustom_E_setDfiClk(0); - break; - case 0x05: - ddr_load_train_code(FW_2D_IMAGE); - break; - case 0x06: - dwc_ddrphy_phyinit_userCustom_G_waitFwDone(); - break; - case 0x07: - dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(1); - break; - case 0x08: - dwc_ddrphy_phyinit_userCustom_customPostTrain(); - dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(); - break; - default: - break; - } - } - } -} diff --git a/board/freescale/imx8mm_evk/ddr/lpddr4_pmu_training_3000mts_fw09.c b/board/freescale/imx8mm_evk/ddr/lpddr4_pmu_training_3000mts_fw09.c deleted file mode 100644 index 33fc6725308..00000000000 --- a/board/freescale/imx8mm_evk/ddr/lpddr4_pmu_training_3000mts_fw09.c +++ /dev/null @@ -1,167 +0,0 @@ -/* -* Copyright 2018 NXP -* -* SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <common.h> -#include <errno.h> -#include <asm/io.h> -#include <asm/arch/ddr_memory_map.h> -#include <asm/arch/clock.h> -#include "lpddr4_define.h" -#include "ddr.h" - -void ddr_init(void) -{ - volatile unsigned int tmp; - - /* - * Desc: assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, - * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, - * [4]src_system_rst_b! - */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); - - /* Desc: deassert [4]src_system_rst_b! */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); - - /* - * Desc: change the clock source of dram_apb_clk_root - * to source 4 --800MHz/4 - */ - clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); - - /* Desc: disable iso PGC_CPU_MAPPING,PU_PGC_SW_PUP_REQ */ - reg32_write(0x303A00EC,0x0000ffff); - reg32setbit(0x303A00F8,5); - - /* - * Desc: configure dram pll to 750M - */ - dram_pll_init(DRAM_PLL_OUT_750M); - - - /* - * Desc: release [0]ddr1_preset_n, [1]ddr1_core_reset_n, - * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n - */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); - - /* Desc: Configure uMCTL2's registers */ - lpddr4_3000mts_cfg_umctl2(); - - /* Desc: diable ctlupd */ - reg32_write(DDRC_DFIUPD0(0), 0xE0300018); - - /* - * Desc: release [1]ddr1_core_reset_n, [2]ddr1_phy_reset, - * [3]ddr1_phy_pwrokin_n - */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); - - /* - * Desc: release [1]ddr1_core_reset_n, [2]ddr1_phy_reset, - * [3]ddr1_phy_pwrokin_n - */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); - - /* - * Desc: ('b00000000_00000000_00000000_00000000) ('d0) - */ - reg32_write(DDRC_DBG1(0), 0x00000000); - - /* - * Desc: [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR - */ - reg32_write(DDRC_PWRCTL(0), 0x000000a8); - - tmp=0; - while(tmp != 0x223) { - tmp = 0x33f & (reg32_read(DDRC_STAT(0))); - ddr_dbg("C: waiting for STAT selfref_type= Self Refresh\n"); - } - - /* - * Desc: ('b00000000_00000000_00000000_00000000) ('d0) - */ - reg32_write(DDRC_SWCTL(0), 0x00000000); - - /* - * Desc: LPDDR4 mode - */ - reg32_write(DDRC_DDR_SS_GPR0, 0x01); - - /* - * Desc: [12:8]dfi_freq, [5]dfi_init_start, [4]ctl_idle_en - */ - reg32_write(DDRC_DFIMISC(0), 0x00000010); - - /* - * Desc: Configure LPDDR4 PHY's registers - */ - lpddr4_750M_cfg_phy(); - - reg32_write(DDRC_RFSHCTL3(0), 0x00000000); - reg32_write(DDRC_SWCTL(0), 0x0000); - - /* - * Desc: Set DFIMISC.dfi_init_start to 1 - * [5]--1: dfi_init_start, [4] ctl_idle_en - */ - reg32_write(DDRC_DFIMISC(0), 0x00000030); - reg32_write(DDRC_SWCTL(0), 0x0001); - - /* - * Desc: wait DFISTAT.dfi_init_complete to 1 - */ - while(!(0x1 & (reg32_read(DDRC_DFISTAT(0))))); - - reg32_write(DDRC_SWCTL(0), 0x0000); - - /* - * Desc: clear DFIMISC.dfi_init_complete_en - * ('b00000000_00000000_00000000_00010000) ('d16) - */ - reg32_write(DDRC_DFIMISC(0), 0x00000010); - - /* - * Desc: set DFIMISC.dfi_init_complete_en again - * ('b00000000_00000000_00000000_00010001) ('d17) - */ - reg32_write(DDRC_DFIMISC(0), 0x00000011); - - /* - * Desc: ('b00000000_00000000_00000000_10001000) ('d136) - */ - reg32_write(DDRC_PWRCTL(0), 0x00000088); - - /* - * Desc: set SWCTL.sw_done to enable quasi-dynamic - * register programming outside reset. - * ('b00000000_00000000_00000000_00000001) ('d1) - */ - reg32_write(DDRC_SWCTL(0), 0x00000001); - - /* - * Desc: wait SWSTAT.sw_done_ack to 1 - */ - while(!(0x1 & (reg32_read(DDRC_SWSTAT(0))))); - - /* - * Desc: wait STAT.operating_mode([2:0] for lpddr4) to normal state - */ - while(0x1 != (0x7 & (reg32_read(DDRC_STAT(0))))); - - /* - * Desc: ('b00000000_00000000_00000000_10001000) ('d136) - */ - reg32_write(DDRC_PWRCTL(0), 0x00000088); - - - /* - * Desc: enable port 0 - * ('b00000000_00000000_00000000_00000001) ('d1) - */ - reg32_write(DDRC_PCTRL_0(0), 0x00000001); -} diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c new file mode 100644 index 00000000000..72ba6ee81b6 --- /dev/null +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c @@ -0,0 +1,1980 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <linux/kernel.h> +#include <asm/arch/ddr_memory_map.h> +#include <asm/arch/lpddr4_define.h> +#include <asm/arch/imx8m_ddr.h> + +struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa1080020 }, + { DDRC_RFSHTMG(0), 0x005b00d2 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG2(0), 0x0000170A }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + { DDRC_DBICTL(0), 0x00000001 }, + + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + + { DDRC_DFIPHYMSTR(0), 0x00000000 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x0000001f }, + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP2(0), 0x00000000 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001f1f }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x07070707 }, + { DDRC_ADDRMAP7(0), 0x00000f0f }, + + /* performance setting */ + { DDRC_SCHED(0), 0x29001701 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x04000030 }, + { DDRC_PERFLPR1(0), 0x900093e7 }, + { DDRC_PERFWR1(0), 0x20005574 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCFGQOS0_0(0), 0x02100e07 }, + { DDRC_PCFGQOS1_0(0), 0x00620096 }, + { DDRC_PCFGWQOS0_0(0), 0x01100e07 }, + { DDRC_PCFGWQOS1_0(0), 0x00c8012c }, + + /* frequency P1&P2 */ + /* Frequency 1: 400mbps */ + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, + { DDRC_FREQ1_INIT3(0), 0x00840000 }, + { DDRC_FREQ1_INIT4(0), 0x00310000 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + + /* Frequency 2: 100mbps */ + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ2_RFSHTMG(0), 0x0003800c }, + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, + { DDRC_FREQ2_INIT3(0), 0x00840000 }, + { DDRC_FREQ2_INIT4(0), 0x00310008 }, + { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, + { DDRC_FREQ2_INIT6(0), 0x0066004a }, + { DDRC_FREQ2_INIT7(0), 0x0006004a }, + + /* boot start point */ + { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + + { 0x20024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x120024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x220024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + + { 0x200b2, 0x1d4 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + + { 0x20025, 0x0 }, + { 0x2002d, LPDDR4_PHY_DMIPinPresent }, + { 0x12002d, LPDDR4_PHY_DMIPinPresent }, + { 0x22002d, LPDDR4_PHY_DMIPinPresent }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x2200c7, 0x21 }, + { 0x2200ca, 0x24 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0xd400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0x8400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100&0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0x8400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0xd400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P1 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info lpddr4_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), +}; diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index 608ab917d19..e827484419f 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -19,14 +19,14 @@ #include <asm/imx-common/mxc_i2c.h> #include <fsl_esdhc.h> #include <mmc.h> -#include "ddr/ddr.h" +#include <asm/arch/imx8m_ddr.h> DECLARE_GLOBAL_DATA_PTR; void spl_dram_init(void) { /* ddr train */ - ddr_init(); + ddr_init(&lpddr4_timing); } #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) |