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| author | Simon Glass <sjg@chromium.org> | 2019-01-21 14:53:27 -0700 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2019-02-01 16:59:12 +0100 |
| commit | 6cecc2b556a7b9cddf7c95155f51208f7bea66b1 (patch) | |
| tree | a5e1ab71349eff84389ae95294253d0e6b0ccebd | |
| parent | 60853a9b5c1f87e70d282de8bdb66bcc5c855b7f (diff) | |
rockchip: Clarify docs on SPI writing
We use every second block when creating a SPI image, so update the text to
say this explicitly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| -rw-r--r-- | doc/README.rockchip | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/doc/README.rockchip b/doc/README.rockchip index 9542265a830..db5724e0730 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -262,7 +262,7 @@ To write an image that boots from SPI flash (e.g. for the Haier Chromebook): dd if=out.bin of=out.bin.pad bs=4M conv=sync This converts the SPL image to the required SPI format by adding the Rockchip -header and skipping every 2KB block. Then the U-Boot image is written at +header and skipping every second 2KB block. Then the U-Boot image is written at offset 128KB and the whole image is padded to 4MB which is the SPI flash size. The position of U-Boot is controlled with this setting in U-Boot: |