diff options
| author | Vitor Soares <vitor.soares@toradex.com> | 2024-02-16 12:41:37 +0000 |
|---|---|---|
| committer | Vitor Soares <vitor.soares@toradex.com> | 2024-02-19 14:55:59 +0000 |
| commit | 626d73cf84b0d6251bc348ec6fc80d24be480512 (patch) | |
| tree | e1b240ab8d88c33daac20143bca17f18bba9958c | |
| parent | a8177718dd3569cc0de63e4c907f9b35b10a64e7 (diff) | |
arm: dts: k3-am625-verdin-r5: Change CPU frequency to 1000MHz
The same U-Boot binary is compatible with multiple Verdin AM62 board
variants. However, some of the SoC models can only operate at a maximum
speed of 1 GHz.
Previously, the boards with lower-speed grades were running at
overclocked speeds, leading to kernel complaints about unsupported
configurations.
To resolve this issue, the operating speed has been decreased to the
maximum allowable value across all Verdin AM62 board variants. As a
result, there is a regression in overall boot time, increasing by around
200 milliseconds for the faster SoC variant.
Upstream-Status: Submitted [https://lore.kernel.org/all/20240219123408.22054-1-ivitro@gmail.com]
Related-to: ELB-5325
Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
| -rw-r--r-- | arch/arm/dts/k3-am625-verdin-r5.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts index 4fda412129..f68c951100 100644 --- a/arch/arm/dts/k3-am625-verdin-r5.dts +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -24,7 +24,7 @@ */ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>; assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>; - assigned-clock-rates = <200000000>, <1200000000>, <25000000>; + assigned-clock-rates = <200000000>, <1000000000>, <25000000>; clocks = <&k3_clks 61 0>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, |