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| author | Hari Nagalla <hnagalla@ti.com> | 2022-08-24 06:53:09 -0500 |
|---|---|---|
| committer | Anand Gadiyar <gadiyar@ti.com> | 2022-09-08 14:59:59 -0500 |
| commit | 5a9068c5f80b238b202905c9fed590e167ed0e67 (patch) | |
| tree | f3ad1488806eaddd748ceaf1082c340fd037e486 | |
| parent | 94ab4d6f8f80a687d050fabc2f5670c9d11bb255 (diff) | |
ram: k3-ddrss: Add support for J784S4 SoC
Add support for DDR subsystem in J784S4 SoC.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
| -rw-r--r-- | drivers/ram/Kconfig | 10 | ||||
| -rw-r--r-- | drivers/ram/k3-ddrss/Makefile | 4 |
2 files changed, 14 insertions, 0 deletions
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index c57a571c31d..40e664db21d 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -64,6 +64,7 @@ choice default K3_J721E_DDRSS if SOC_K3_J721E default K3_J721S2_DDRSS if SOC_K3_J721S2 + default K3_J784S4_DDRSS if SOC_K3_J784S4 default K3_AM64_DDRSS if SOC_K3_AM642 default K3_AM64_DDRSS if SOC_K3_AM625 @@ -87,6 +88,15 @@ config K3_J721S2_DDRSS Enabling this config adds support for the DDR memory controller on J721S2 family of SoCs. +config K3_J784S4_DDRSS + bool "Enable J784S4 DRSS support" + help + The J784S4 DDR subsystem comprises DDR controller, DDR PHY and + wrapper logic to integrate these blocks in the device. The DDR + subsystem is used to provide an interface to external SDRAM + devices which can be utilized for storing program or data. + Enabling this config adds support for the DDR memory controller + on J784S4 family of SoCs. config K3_AM64_DDRSS bool "Enable AM64 DDRSS support" diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile index 2f6df0b7ad0..2ac34914e01 100644 --- a/drivers/ram/k3-ddrss/Makefile +++ b/drivers/ram/k3-ddrss/Makefile @@ -20,3 +20,7 @@ ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/ obj-$(CONFIG_K3_J721S2_DDRSS) += lpddr4_32bit.o obj-$(CONFIG_K3_J721S2_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o ccflags-$(CONFIG_K3_J721S2_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/ + +obj-$(CONFIG_K3_J784S4_DDRSS) += lpddr4_32bit.o +obj-$(CONFIG_K3_J784S4_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o +ccflags-$(CONFIG_K3_J784S4_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/ |