MLK-23574-52 mx6sll_val: Add iMX6SLL validation boards support

Porting the iMX6SLL LPDDR3/LPDDR2 validation board support from
v2019.04 u-boot.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit fabe5a0e397fdc89862c706ae502b5cc7afd16f5)
(cherry picked from commit cb2cc57c9d2166db88b4428d35196d415fd33ef0)
(cherry picked from commit 32e608b96bf3873bd55239d9029c7a676b407dd8)

17 files changed, 2709 insertions, 1 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7397ef28e8..2bb3f05392 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -827,7 +827,10 @@ endif
 
 dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
 
-dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb
+dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb \
+	imx6sll-lpddr2-val.dtb \
+	imx6sll-lpddr3-val.dtb \
+	imx6sll-lpddr3-val-ecspi.dtb
 
 dtb-$(CONFIG_MX6SX) += \
 	imx6sx-14x14-val.dtb \
diff --git a/arch/arm/dts/imx6sll-lpddr2-val.dts b/arch/arm/dts/imx6sll-lpddr2-val.dts
new file mode 100644
index 0000000000..66111b85fb
--- /dev/null
+++ b/arch/arm/dts/imx6sll-lpddr2-val.dts
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sll-lpddr3-val.dts"
+
diff --git a/arch/arm/dts/imx6sll-lpddr3-val-ecspi.dts b/arch/arm/dts/imx6sll-lpddr3-val-ecspi.dts
new file mode 100644
index 0000000000..60b90bd023
--- /dev/null
+++ b/arch/arm/dts/imx6sll-lpddr3-val-ecspi.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sll-lpddr3-val.dts"
+
+&ecspi1 {
+	status = "okay";
+};
+
+&lcdif {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/imx6sll-lpddr3-val.dts b/arch/arm/dts/imx6sll-lpddr3-val.dts
new file mode 100644
index 0000000000..458789a394
--- /dev/null
+++ b/arch/arm/dts/imx6sll-lpddr3-val.dts
@@ -0,0 +1,857 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6sll.dtsi"
+
+/ {
+	model = "i.MX6SLL Validation Board";
+	compatible = "fsl,imx6sll-lpddr3-val", "fsl,imx6sll";
+
+	memory {
+		reg = <0x80000000 0x80000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_led>;
+
+		users {
+			label = "debug";
+			gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		status = "okay";
+	};
+
+	pxp_v4l2_out {
+		compatible = "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&swbst_reg>;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&swbst_reg>;
+		};
+
+		reg_aud3v: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "wm8962-supply-3v15";
+			regulator-min-microvolt = <3150000>;
+			regulator-max-microvolt = <3150000>;
+			regulator-boot-on;
+		};
+
+		reg_aud4v: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "wm8962-supply-4v2";
+			regulator-min-microvolt = <4325000>;
+			regulator-max-microvolt = <4325000>;
+			regulator-boot-on;
+		};
+
+		reg_lcd: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "lcd-pwr";
+			gpio = <&gpio4 8 0>;
+			enable-active-high;
+		};
+
+		reg_sd1_vmmc: sd1_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD1_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <20000>;
+			startup-delay-us = <2000>;
+			enable-active-high;
+		};
+
+		reg_sd2_vmmc: sd2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "eMMC-VCCQ";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-boot-on;
+		};
+
+		reg_sd3_vmmc: sd3_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD3_WIFI";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <20000>;
+			startup-delay-us = <2000>;
+			enable-active-high;
+		};
+
+	};
+
+	sound {
+		compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
+		model = "wm8962-audio";
+		cpu-dai = <&ssi2>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"Ext Spk", "SPKOUTL",
+			"Ext Spk", "SPKOUTR",
+			"AMIC", "MICBIAS",
+			"IN3R", "AMIC";
+		mux-int-port = <2>;
+		mux-ext-port = <3>;
+		codec-master;
+		hp-det-gpios = <&gpio4 24 1>;
+	};
+};
+
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux3>;
+	status = "okay";
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <393216000>;
+};
+
+&cpu0 {
+	arm-supply = <&sw1a_reg>;
+	soc-supply = <&sw1c_reg>;
+};
+
+&csi {
+	status = "disabled";
+
+	port {
+		csi1_ep: endpoint {
+			remote-endpoint = <&ov5640_ep>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	max17135: max17135@48 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_max17135>;
+		compatible = "maxim,max17135";
+		reg = <0x48>;
+		status = "okay";
+
+		vneg_pwrup = <1>;
+		gvee_pwrup = <2>;
+		vpos_pwrup = <10>;
+		gvdd_pwrup = <12>;
+		gvdd_pwrdn = <1>;
+		vpos_pwrdn = <2>;
+		gvee_pwrdn = <8>;
+		vneg_pwrdn = <10>;
+		gpio_pmic_pwrgood = <&gpio2 13 0>;
+		gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
+		gpio_pmic_wakeup = <&gpio2 14 0>;
+		gpio_pmic_v3p3 = <&gpio2 7 0>;
+		gpio_pmic_intr = <&gpio2 12 0>;
+
+		regulators {
+			DISPLAY_reg: DISPLAY {
+				regulator-name = "DISPLAY";
+			};
+
+			GVDD_reg: GVDD {
+				/* 20v */
+				regulator-name = "GVDD";
+			};
+
+			GVEE_reg: GVEE {
+				/* -22v */
+				regulator-name = "GVEE";
+			};
+
+			HVINN_reg: HVINN {
+				/* -22v */
+				regulator-name = "HVINN";
+			};
+
+			HVINP_reg: HVINP {
+				/* 20v */
+				regulator-name = "HVINP";
+			};
+
+			VCOM_reg: VCOM {
+				regulator-name = "VCOM";
+				/* Real max value: -500000 */
+				regulator-max-microvolt = <4325000>;
+				/* Real min value: -4325000 */
+				regulator-min-microvolt = <500000>;
+			};
+
+			VNEG_reg: VNEG {
+				/* -15v */
+				regulator-name = "VNEG";
+			};
+
+			VPOS_reg: VPOS {
+				/* 15v */
+				regulator-name = "VPOS";
+			};
+
+			V3P3_reg: V3P3 {
+				regulator-name = "V3P3";
+			};
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+        scl-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+        sda-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	codec: wm8962@1a {
+		compatible = "wlf,wm8962";
+		reg = <0x1a>;
+		clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
+		DCVDD-supply = <&vgen3_reg>;
+		DBVDD-supply = <&reg_aud3v>;
+		AVDD-supply = <&vgen3_reg>;
+		CPVDD-supply = <&vgen3_reg>;
+		MICVDD-supply = <&reg_aud3v>;
+		PLLVDD-supply = <&vgen3_reg>;
+		SPKVDD1-supply = <&reg_aud4v>;
+		SPKVDD2-supply = <&reg_aud4v>;
+		amic-mono;
+	};
+
+	ov5640: ov5640@3c {
+		compatible = "ovti,ov5640";
+		reg = <0x3c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_csi1>;
+		clocks = <&clks IMX6SLL_CLK_CSI>;
+		clock-names = "csi_mclk";
+		AVDD-supply = <&vgen6_reg>;  /* 2.8v */
+		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
+		pwn-gpios = <&gpio1 25 1>;
+		rst-gpios = <&gpio1 26 0>;
+		csi_id = <0>;
+		mclk = <24000000>;
+		mclk_source = <0>;
+		status = "disabled";
+		port {
+			ov5640_ep: endpoint {
+				remote-endpoint = <&csi1_ep>;
+			};
+		};
+	};
+};
+
+&gpc {
+	fsl,ldo-bypass = <1>;
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog &pinctrl_hog_sd2_reset>;
+
+	imx6sll-lpddr3-val {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
+				MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059
+				MX6SLL_PAD_KEY_COL3__GPIO3_IO30	0x17059
+				MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
+				MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */
+				MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */
+				MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
+				MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
+			>;
+		};
+
+		pinctrl_hog_sd2_reset: hoggrp-1 {
+			fsl,pins = <
+				MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059
+			>;
+		};
+
+		pinctrl_audmux3: audmux3grp {
+			fsl,pins = <
+				MX6SLL_PAD_AUD_TXC__AUD3_TXC		0x4130b0
+				MX6SLL_PAD_AUD_TXFS__AUD3_TXFS		0x4130b0
+				MX6SLL_PAD_AUD_TXD__AUD3_TXD		0x4110b0
+				MX6SLL_PAD_AUD_RXD__AUD3_RXD		0x4130b0
+				MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT	0x4130b0
+			>;
+		};
+
+		pinctrl_csi1: csi1grp {
+			fsl,pins = <
+				MX6SLL_PAD_EPDC_GDRL__CSI_MCLK		0x1b088
+				MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK	0x1b088
+				MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC		0x1b088
+				MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC		0x1b088
+				MX6SLL_PAD_EPDC_DATA02__CSI_DATA02	0x1b088
+				MX6SLL_PAD_EPDC_DATA03__CSI_DATA03	0x1b088
+				MX6SLL_PAD_EPDC_DATA04__CSI_DATA04	0x1b088
+				MX6SLL_PAD_EPDC_DATA05__CSI_DATA05	0x1b088
+				MX6SLL_PAD_EPDC_DATA06__CSI_DATA06	0x1b088
+				MX6SLL_PAD_EPDC_DATA07__CSI_DATA07	0x1b088
+				MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08	0x1b088
+				MX6SLL_PAD_EPDC_SDLE__CSI_DATA09	0x1b088
+				MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26	0x80000000
+				MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25	0x80000000
+			>;
+		};
+
+		pinctrl_led: ledgrp {
+			fsl,pins = <
+				MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059
+			>;
+		};
+
+                pinctrl_epdc0: epdcgrp0 {
+                        fsl,pins = <
+				MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00	0x100b1
+				MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01	0x100b1
+				MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02	0x100b1
+				MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03	0x100b1
+				MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04	0x100b1
+				MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05	0x100b1
+				MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06	0x100b1
+				MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07	0x100b1
+				MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08	0x100b1
+				MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09	0x100b1
+				MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10	0x100b1
+				MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11	0x100b1
+				MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12	0x100b1
+				MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13	0x100b1
+				MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14	0x100b1
+				MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15	0x100b1
+				MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P	0x100b1
+				MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE		0x100b1
+				MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE		0x100b1
+				MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR	0x100b1
+				MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0	0x100b1
+				MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK	0x100b1
+				MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE		0x100b1
+				MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL		0x100b1
+				MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP		0x100b1
+                       >;
+                };
+
+		pinctrl_lcdif_dat: lcdifdatgrp {
+			fsl,pins = <
+				MX6SLL_PAD_LCD_DATA00__LCD_DATA00	0x79
+				MX6SLL_PAD_LCD_DATA01__LCD_DATA01	0x79
+				MX6SLL_PAD_LCD_DATA02__LCD_DATA02	0x79
+				MX6SLL_PAD_LCD_DATA03__LCD_DATA03	0x79
+				MX6SLL_PAD_LCD_DATA04__LCD_DATA04	0x79
+				MX6SLL_PAD_LCD_DATA05__LCD_DATA05	0x79
+				MX6SLL_PAD_LCD_DATA06__LCD_DATA06	0x79
+				MX6SLL_PAD_LCD_DATA07__LCD_DATA07	0x79
+				MX6SLL_PAD_LCD_DATA08__LCD_DATA08	0x79
+				MX6SLL_PAD_LCD_DATA09__LCD_DATA09	0x79
+				MX6SLL_PAD_LCD_DATA10__LCD_DATA10	0x79
+				MX6SLL_PAD_LCD_DATA11__LCD_DATA11	0x79
+				MX6SLL_PAD_LCD_DATA12__LCD_DATA12	0x79
+				MX6SLL_PAD_LCD_DATA13__LCD_DATA13	0x79
+				MX6SLL_PAD_LCD_DATA14__LCD_DATA14	0x79
+				MX6SLL_PAD_LCD_DATA15__LCD_DATA15	0x79
+				MX6SLL_PAD_LCD_DATA16__LCD_DATA16	0x79
+				MX6SLL_PAD_LCD_DATA17__LCD_DATA17	0x79
+				MX6SLL_PAD_LCD_DATA18__LCD_DATA18	0x79
+				MX6SLL_PAD_LCD_DATA19__LCD_DATA19	0x79
+				MX6SLL_PAD_LCD_DATA20__LCD_DATA20	0x79
+				MX6SLL_PAD_LCD_DATA21__LCD_DATA21	0x79
+				MX6SLL_PAD_LCD_DATA22__LCD_DATA22	0x79
+				MX6SLL_PAD_LCD_DATA23__LCD_DATA23	0x79
+			>;
+		};
+
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
+				MX6SLL_PAD_LCD_CLK__LCD_CLK		0x79
+				MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE	0x79
+				MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC		0x79
+				MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC		0x79
+				MX6SLL_PAD_LCD_RESET__LCD_RESET		0x79
+				MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08	0x79
+			>;
+		};
+
+		pinctrl_max17135: max17135grp-1 {
+			fsl,pins = <
+				MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13	0x80000000  /* pwrgood */
+				MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03	0x80000000  /* vcom_ctrl */
+				MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14	0x80000000  /* wakeup */
+				MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07	0x80000000  /* v3p3 */
+				MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12	0x80000000  /* pwr int */
+			>;
+		};
+
+		pinctrl_spdif: spdifgrp {
+			fsl,pins = <
+				MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x4130b0
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
+				MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x17059
+				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x17059
+				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x17059
+				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x17059
+				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x17059
+				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x17059
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170b9
+				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x170b9
+				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170b9
+				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170b9
+				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170b9
+				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170b9
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170f9
+				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x170f9
+				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170f9
+				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170f9
+				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170f9
+				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170f9
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6SLL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6SLL_PAD_SD2_CLK__SD2_CLK		0x13059
+				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 	0x17059
+				MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x17059
+				MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x17059
+				MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x17059
+				MX6SLL_PAD_SD2_DATA4__SD2_DATA4		0x17059
+				MX6SLL_PAD_SD2_DATA5__SD2_DATA5		0x17059
+				MX6SLL_PAD_SD2_DATA6__SD2_DATA6		0x17059
+				MX6SLL_PAD_SD2_DATA7__SD2_DATA7		0x17059
+				MX6SLL_PAD_GPIO4_IO21__SD2_STROBE	0x413059
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170b9
+				MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130b9
+				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 	0x170b9
+				MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170b9
+				MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170b9
+				MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170b9
+				MX6SLL_PAD_SD2_DATA4__SD2_DATA4		0x170b9
+				MX6SLL_PAD_SD2_DATA5__SD2_DATA5		0x170b9
+				MX6SLL_PAD_SD2_DATA6__SD2_DATA6		0x170b9
+				MX6SLL_PAD_SD2_DATA7__SD2_DATA7		0x170b9
+				MX6SLL_PAD_GPIO4_IO21__SD2_STROBE	0x4130b9
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170f9
+				MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130f9
+				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 	0x170f9
+				MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170f9
+				MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170f9
+				MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170f9
+				MX6SLL_PAD_SD2_DATA4__SD2_DATA4		0x170f9
+				MX6SLL_PAD_SD2_DATA5__SD2_DATA5		0x170f9
+				MX6SLL_PAD_SD2_DATA6__SD2_DATA6		0x170f9
+				MX6SLL_PAD_SD2_DATA7__SD2_DATA7		0x170f9
+				MX6SLL_PAD_GPIO4_IO21__SD2_STROBE	0x4130f9
+			>;
+		};
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x17059
+				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x17059
+				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x17059
+				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x17059
+				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x17059
+				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x17059
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170b9
+				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170b9
+				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170b9
+				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170b9
+				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170b9
+				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170b9
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170f9
+				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170f9
+				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170f9
+				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170f9
+				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170f9
+				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170f9
+			>;
+		};
+
+		pinctrl_usbotg1: usbotg1grp {
+			fsl,pins = <
+				MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6SLL_PAD_I2C1_SCL__I2C1_SCL	 0x4001b8b1
+				MX6SLL_PAD_I2C1_SDA__I2C1_SDA	 0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c1_gpio: i2c1grp_gpio {
+			fsl,pins = <
+				MX6SLL_PAD_I2C1_SCL__GPIO3_IO12    0x1b8b1
+				MX6SLL_PAD_I2C1_SDA__GPIO3_IO13    0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL  0x4041b8b1
+				MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA  0x4041b8b1
+			>;
+		};
+
+		pinctrl_i2c3_gpio: i2c3grp_gpio {
+			fsl,pins = <
+				MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29  0x41b8b1
+				MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30  0x41b8b1
+			>;
+		};
+
+		pinctrl_pwm1: pmw1grp {
+			fsl,pins = <
+				MX6SLL_PAD_PWM1__PWM1_OUT   0x110b0
+			>;
+		};
+
+		pinctrl_ecspi1: ecspi1grp {
+			fsl,pins = <
+				MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO	 0x100b1
+				MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI	 0x100b1
+				MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK	 0x100b1
+				MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11	 0x100b1
+			>;
+		};
+	};
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+	lcd-supply = <&reg_lcd>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display@0 {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <33500000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <89>;
+				hfront-porch = <164>;
+				vback-porch = <23>;
+				vfront-porch = <10>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&pxp {
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	vqmmc-supply = <&reg_sd2_vmmc>;
+	bus-width = <8>;
+	no-removable;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd3_vmmc>;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1>;
+	disable-over-current;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio4 11 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	status = "disabled";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	flash: m25p80@0 {
+		compatible = "st,m25p32", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&epdc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_epdc0>;
+	V3P3-supply = <&V3P3_reg>;
+	VCOM-supply = <&VCOM_reg>;
+	DISPLAY-supply = <&DISPLAY_reg>;
+	status = "okay";
+};
+
+&ssi2 {
+	status = "okay";
+};
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index fddbf709ee..9918440430 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -465,6 +465,14 @@ config TARGET_MX6SLLEVK
 	select DM_THERMAL
 	imply CMD_DM
 
+config TARGET_MX6SLL_VAL
+	bool "mx6sll val"
+	depends on MX6SLL
+	select BOARD_LATE_INIT
+	select DM
+	select DM_THERMAL
+	imply CMD_DM
+
 config TARGET_MX6SXSABRESD
 	bool "mx6sxsabresd"
 	depends on MX6SX
@@ -805,6 +813,7 @@ source "board/freescale/mx6memcal/Kconfig"
 source "board/freescale/mx6sabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
 source "board/freescale/mx6slevk/Kconfig"
+source "board/freescale/mx6sll_val/Kconfig"
 source "board/freescale/mx6sllevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/mx6sxsabreauto/Kconfig"
diff --git a/board/freescale/mx6sll_val/Kconfig b/board/freescale/mx6sll_val/Kconfig
new file mode 100644
index 0000000000..9964eccf89
--- /dev/null
+++ b/board/freescale/mx6sll_val/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_MX6SLL_VAL
+
+config SYS_BOARD
+	default "mx6sll_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6sll_val"
+
+config LPDDR2_BOARD
+	bool "set if the board uses the LPDDR2 not default LPDDR3" 
+
+config SYS_TEXT_BASE
+	default 0x87800000
+
+endif
diff --git a/board/freescale/mx6sll_val/Makefile b/board/freescale/mx6sll_val/Makefile
new file mode 100644
index 0000000000..f3d2f83728
--- /dev/null
+++ b/board/freescale/mx6sll_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6sll_val.o
diff --git a/board/freescale/mx6sll_val/imximage.cfg b/board/freescale/mx6sll_val/imximage.cfg
new file mode 100644
index 0000000000..733aedd3b0
--- /dev/null
+++ b/board/freescale/mx6sll_val/imximage.cfg
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sll_val/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E0550 0x00080000
+DATA 4 0x020E0534 0x00000000
+DATA 4 0x020E02AC 0x00000030
+DATA 4 0x020E0548 0x00000030
+DATA 4 0x020E052C 0x00000030
+DATA 4 0x020E0530 0x00020000
+DATA 4 0x020E02B0 0x00003030
+DATA 4 0x020E02B4 0x00003030
+DATA 4 0x020E02B8 0x00003030
+DATA 4 0x020E02BC 0x00003030
+DATA 4 0x020E0540 0x00020000
+DATA 4 0x020E0544 0x00000030
+DATA 4 0x020E054C 0x00000030
+DATA 4 0x020E0554 0x00000030
+DATA 4 0x020E0558 0x00000030
+DATA 4 0x020E0294 0x00000030
+DATA 4 0x020E0298 0x00000030
+DATA 4 0x020E029C 0x00000030
+DATA 4 0x020E02A0 0x00000030
+DATA 4 0x020E02C0 0x00082030
+
+DATA 4 0x021B001C 0x00008000
+
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B085c 0x084700C7
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B0848 0x3C3A3C3C
+DATA 4 0x021B0850 0x24293625
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B0824 0x33333333
+DATA 4 0x021B0828 0x33333333
+
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B0834 0xf3333333
+DATA 4 0x021B0838 0xf3333333
+DATA 4 0x021B08C0 0x24922492
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B000C 0x53574333
+DATA 4 0x021B0010 0x00100B22
+DATA 4 0x021B0038 0x00170778
+DATA 4 0x021B0014 0x00C700DB
+DATA 4 0x021B0018 0x00201718
+DATA 4 0x021B002C 0x0F9F26D2
+DATA 4 0x021B0030 0x009F0E10
+DATA 4 0x021B0040 0x0000005F
+DATA 4 0x021B0000 0xC4190000
+
+DATA 4 0x021B001C 0x00008050
+DATA 4 0x021B001C 0x00008058
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0x003F8038
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0xFF0A8038
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x04028038
+DATA 4 0x021B001C 0x83018030
+DATA 4 0x021B001C 0x83018038
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B001C 0x01038038
+
+DATA 4 0x021B083C 0x20000000
+
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6sll_val/imximage_lpddr2.cfg b/board/freescale/mx6sll_val/imximage_lpddr2.cfg
new file mode 100644
index 0000000000..e6c52b73a5
--- /dev/null
+++ b/board/freescale/mx6sll_val/imximage_lpddr2.cfg
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sll_val/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E0550 0x00080000
+DATA 4 0x020E0534 0x00000000
+DATA 4 0x020E02AC 0x00000030
+DATA 4 0x020E0548 0x00000030
+DATA 4 0x020E052C 0x00000030
+DATA 4 0x020E0530 0x00020000
+DATA 4 0x020E02B0 0x00003030
+DATA 4 0x020E02B4 0x00003030
+DATA 4 0x020E02B8 0x00003030
+DATA 4 0x020E02BC 0x00003030
+DATA 4 0x020E0540 0x00020000
+DATA 4 0x020E0544 0x00000030
+DATA 4 0x020E054C 0x00000030
+DATA 4 0x020E0554 0x00000030
+DATA 4 0x020E0558 0x00000030
+DATA 4 0x020E0294 0x00000030
+DATA 4 0x020E0298 0x00000030
+DATA 4 0x020E029C 0x00000030
+DATA 4 0x020E02A0 0x00000030
+DATA 4 0x020E02C0 0x00082030
+
+DATA 4 0x021B001C 0x00008000
+
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B085c 0x084700C7
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B0848 0x3A383C40
+DATA 4 0x021B0850 0x242C3020
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B0824 0x33333333
+DATA 4 0x021B0828 0x33333333
+
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B0834 0xf3333333
+DATA 4 0x021B0838 0xf3333333
+DATA 4 0x021B08C0 0x24922492
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B000C 0x53574333
+DATA 4 0x021B0010 0x00100A82
+DATA 4 0x021B0038 0x00170777
+DATA 4 0x021B0014 0x00C70093
+DATA 4 0x021B0018 0x00201708
+DATA 4 0x021B002C 0x0F9F26D2
+DATA 4 0x021B0030 0x009F0E10
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0xC3110000
+
+DATA 4 0x021B001C 0x00008050
+DATA 4 0x021B001C 0x00008058
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0x003F8038
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0xFF0A8038
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x04028038
+DATA 4 0x021B001C 0x82018030
+DATA 4 0x021B001C 0x82018038
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B001C 0x01038038
+
+DATA 4 0x021B083C 0x20000000
+
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6sll_val/mx6sll_val.c b/board/freescale/mx6sll_val/mx6sll_val.c
new file mode 100644
index 0000000000..6acd73cec6
--- /dev/null
+++ b/board/freescale/mx6sll_val/mx6sll_val.c
@@ -0,0 +1,751 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch-mx6/clock.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <mxsfb.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#if defined(CONFIG_MXC_EPDC)
+#include <lcd.h>
+#include <mxc_epdc_fb.h>
+#endif
+#include <asm/mach-imx/video.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define EPDC_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC and EPD */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		/* conflict with usb_otg2_pwr */
+		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO3_IO12 | PC,
+		.gp = IMX_GPIO_NR(3, 12),
+	},
+	.sda = {
+		/* conflict with usb_otg2_oc */
+		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO3_IO13 | PC,
+		.gp = IMX_GPIO_NR(3, 13),
+	},
+};
+
+/* I2C2 for LCD and ADV */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_I2C2_SCL__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_I2C2_SCL__GPIO3_IO14 | PC,
+		.gp = IMX_GPIO_NR(3, 14),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_I2C2_SDA__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_I2C2_SDA__GPIO3_IO15 | PC,
+		.gp = IMX_GPIO_NR(3, 15),
+	},
+};
+
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const led_pads[] = {
+	MX6_PAD_EPDC_VCOM1__GPIO2_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+/* 8bit SD1 */
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA4__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA5__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA6__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA7__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* CD */
+	MX6_PAD_KEY_ROW7__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* WP */
+	MX6_PAD_GPIO4_IO22__SD1_WP   | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* EMMC */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* DQS */
+	MX6_PAD_GPIO4_IO21__SD2_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* RST_B */
+	MX6_PAD_SD2_RESET__GPIO4_IO27 | MUX_PAD_CTRL(USDHC_PAD_CTRL | PAD_CTL_LVE),
+};
+
+/* Wifi SD */
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* CD */
+	MX6_PAD_REF_CLK_32K__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+
+	SETUP_IOMUX_PADS(led_pads);
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC1_BASE_ADDR, 0, 8, 1},
+	{USDHC2_BASE_ADDR, 0, 8, 0, 1}, /* fixed 1.8v IO voltage for eMMC chip */
+	{USDHC3_BASE_ADDR, 0, 4},
+};
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
+#define USDHC2_PWR_GPIO	IMX_GPIO_NR(4, 27)
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(3, 22)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 * mmc2                    USDHC3
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
+			gpio_direction_input(USDHC1_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		case 2:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
+			gpio_direction_input(USDHC3_CD_GPIO);
+			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
+			return 0;
+		}
+
+		if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_POWER_LEGACY
+#define I2C_PMIC	0
+static struct pmic *pfuze;
+int power_init_board(void)
+{
+	int ret;
+	u32 rev_id, value;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	pfuze = pmic_get("PFUZE100");
+	if (!pfuze)
+		return -ENODEV;
+
+	ret = pmic_probe(pfuze);
+	if (ret)
+		return ret;
+
+	ret = pfuze_mode_init(pfuze, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value);
+	pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id);
+	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id);
+
+	/* set SW1AB standby volatage 0.975V */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
+	value &= ~0x3f;
+	value |= PFUZE100_SW1ABC_SETP(9750);
+	pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
+	value &= ~0xc0;
+	value |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
+
+	/* set SW1C staby volatage 0.975V */
+	pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
+	value &= ~0x3f;
+	value |= 0x1b;
+	pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
+	value &= ~0xc0;
+	value |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
+
+	return 0;
+}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	dev = pfuze_common_init();
+	if (!dev)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+
+	/* CS0 */
+	MX6_PAD_ECSPI1_SS0__GPIO4_IO11   | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_spinor(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+	gpio_request(IMX_GPIO_NR(4, 11), "escpi cs");
+	gpio_direction_output(IMX_GPIO_NR(4, 11), 0);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
+}
+#endif
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX6_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA00__LCD_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA01__LCD_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA02__LCD_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA03__LCD_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA04__LCD_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA05__LCD_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA06__LCD_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA07__LCD_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA08__LCD_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA09__LCD_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_ECSPI1_SCLK__GPIO4_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_LCD_RESET__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* Use GPIO for Brightness adjustment, duty cycle = period */
+	MX6_PAD_PWM1__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void do_enable_parallel_lcd(struct display_info_t const *dev)
+
+{
+	int ret;
+
+	ret = enable_lcdif_clock(dev->bus, 1);
+	if (ret) {
+		printf("Enable LCDIF clock failed, %d\n", ret);
+		return;
+	}
+
+	SETUP_IOMUX_PADS(lcd_pads);
+
+	/* Reset the LCD */
+	gpio_request(IMX_GPIO_NR(2, 19), "lcd reset");
+	gpio_direction_output(IMX_GPIO_NR(2, 19) , 0);
+	udelay(500);
+	gpio_direction_output(IMX_GPIO_NR(2, 19) , 1);
+
+	gpio_request(IMX_GPIO_NR(4, 8), "lcd pwr en");
+	gpio_direction_output(IMX_GPIO_NR(4, 8) , 1);
+
+	/* Set Brightness to high */
+	gpio_request(IMX_GPIO_NR(3, 23), "backlight");
+	gpio_direction_output(IMX_GPIO_NR(3, 23) , 1);
+}
+
+struct display_info_t const displays[] = {{
+	.bus = MX6SLL_LCDIF_BASE_ADDR,
+	.addr = 0,
+	.pixfmt = 24,
+	.detect = NULL,
+	.enable	= do_enable_parallel_lcd,
+	.mode	= {
+		.name			= "MCIMX28LCD",
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 29850,
+		.left_margin    = 89,
+		.right_margin   = 164,
+		.upper_margin   = 23,
+		.lower_margin   = 10,
+		.hsync_len      = 10,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+#endif
+
+#ifdef CONFIG_MXC_EPDC
+static iomux_v3_cfg_t const epdc_enable_pads[] = {
+	MX6_PAD_EPDC_DATA00__EPDC_DATA00	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA01__EPDC_DATA01	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA02__EPDC_DATA02	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA03__EPDC_DATA03	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA04__EPDC_DATA04	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA05__EPDC_DATA05	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA06__EPDC_DATA06	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA07__EPDC_DATA07	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA08__EPDC_DATA08	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA09__EPDC_DATA09	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA10__EPDC_DATA10	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA11__EPDC_DATA11	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA12__EPDC_DATA12	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA13__EPDC_DATA13	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA14__EPDC_DATA14	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA15__EPDC_DATA15	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDLE__EPDC_SDLE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDOE__EPDC_SDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDSHR__EPDC_SDSHR		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDCE0__EPDC_SDCE0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDCLK__EPDC_GDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDOE__EPDC_GDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDRL__EPDC_GDRL		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDSP__EPDC_GDSP		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const epdc_disable_pads[] = {
+	MX6_PAD_EPDC_DATA01__GPIO1_IO08,
+	MX6_PAD_EPDC_DATA02__GPIO1_IO09,
+	MX6_PAD_EPDC_DATA03__GPIO1_IO10,
+	MX6_PAD_EPDC_DATA04__GPIO1_IO11,
+	MX6_PAD_EPDC_DATA05__GPIO1_IO12,
+	MX6_PAD_EPDC_DATA06__GPIO1_IO13,
+	MX6_PAD_EPDC_DATA07__GPIO1_IO14,
+	MX6_PAD_EPDC_DATA08__GPIO1_IO15,
+	MX6_PAD_EPDC_DATA09__GPIO1_IO16,
+	MX6_PAD_EPDC_DATA10__GPIO1_IO17,
+	MX6_PAD_EPDC_DATA11__GPIO1_IO18,
+	MX6_PAD_EPDC_DATA12__GPIO1_IO19,
+	MX6_PAD_EPDC_DATA13__GPIO1_IO20,
+	MX6_PAD_EPDC_DATA14__GPIO1_IO21,
+	MX6_PAD_EPDC_DATA15__GPIO1_IO22,
+	MX6_PAD_EPDC_SDCLK__GPIO1_IO23,
+	MX6_PAD_EPDC_SDLE__GPIO1_IO24,
+	MX6_PAD_EPDC_SDOE__GPIO1_IO25,
+	MX6_PAD_EPDC_SDSHR__GPIO1_IO26,
+	MX6_PAD_EPDC_SDCE0__GPIO1_IO27,
+	MX6_PAD_EPDC_GDCLK__GPIO1_IO31,
+	MX6_PAD_EPDC_GDOE__GPIO2_IO00,
+	MX6_PAD_EPDC_GDRL__GPIO2_IO01,
+	MX6_PAD_EPDC_GDSP__GPIO2_IO02,
+};
+
+vidinfo_t panel_info = {
+	.vl_refresh = 85,
+	.vl_col = 1024,
+	.vl_row = 758,
+	.vl_pixclock = 40000000,
+	.vl_left_margin = 12,
+	.vl_right_margin = 76,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 5,
+	.vl_hsync = 12,
+	.vl_vsync = 2,
+	.vl_sync = 0,
+	.vl_mode = 0,
+	.vl_flag = 0,
+	.vl_bpix = 3,
+	.cmap = 0,
+};
+
+struct epdc_timing_params panel_timings = {
+	.vscan_holdoff = 4,
+	.sdoed_width = 10,
+	.sdoed_delay = 20,
+	.sdoez_width = 10,
+	.sdoez_delay = 20,
+	.gdclk_hp_offs = 524,
+	.gdsp_offs = 327,
+	.gdoe_offs = 0,
+	.gdclk_offs = 19,
+	.num_ce = 1,
+};
+
+static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = {
+	IOMUX_PADS(PAD_EPDC_PWR_STAT__GPIO2_IO13	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EPDC_VCOM0__GPIO2_IO03		| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EPDC_PWR_WAKE__GPIO2_IO14	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EPDC_PWR_CTRL0__GPIO2_IO07	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+};
+
+static void setup_epdc_power(void)
+{
+	SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads);
+	/* Setup epdc voltage */
+
+	/* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */
+	gpio_request(IMX_GPIO_NR(2, 13), "EPDC_PWRSTAT");
+	gpio_direction_input(IMX_GPIO_NR(2, 13));
+
+	/* EPDC_VCOM0 - GPIO2[03] for VCOM control */
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(2, 3), "EPDC_VCOM0");
+	gpio_direction_output(IMX_GPIO_NR(2, 3), 1);
+
+	/* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(2, 14), "EPDC_PWRWAKEUP");
+	gpio_direction_output(IMX_GPIO_NR(2, 14), 1);
+
+	/* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(2, 7), "EPDC_PWRCTRL0");
+	gpio_direction_output(IMX_GPIO_NR(2, 7), 1);
+}
+
+static void epdc_enable_pins(void)
+{
+	/* epdc iomux settings */
+	SETUP_IOMUX_PADS(epdc_enable_pads);
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO  and drive to 0 */
+	SETUP_IOMUX_PADS(epdc_disable_pads);
+}
+
+static void setup_epdc(void)
+{
+	/* Set pixel clock rates for EPDC in clock.c */
+
+	panel_info.epdc_data.wv_modes.mode_init = 0;
+	panel_info.epdc_data.wv_modes.mode_du = 1;
+	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
+	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
+
+	panel_info.epdc_data.epdc_timings = panel_timings;
+
+	setup_epdc_power();
+}
+
+void epdc_power_on(void)
+{
+	unsigned int reg;
+	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(2, 7), 1);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	gpio_set_value(IMX_GPIO_NR(2, 14), 1);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(&gpio_regs->gpio_psr);
+		if (!(reg & (1 << 13)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	gpio_set_value(IMX_GPIO_NR(2, 3), 1);
+
+	udelay(500);
+}
+
+void epdc_power_off(void)
+{
+	/* Set PMIC Wakeup to low - disable Display power */
+	gpio_set_value(IMX_GPIO_NR(2, 14), 0);
+
+	/* Disable VCOM */
+	gpio_set_value(IMX_GPIO_NR(2, 3), 0);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(2, 7), 0);
+}
+#endif
+
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+	MX6_PAD_KEY_COL4__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW4__USB_OTG1_OC  | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EPDC_PWR_COM__USB_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+	MX6_PAD_KEY_COL5__USB_OTG2_PWR   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_ECSPI2_SCLK__USB_OTG2_OC | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EPDC_PWR_IRQ__USB_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+int board_usb_phy_mode(int port)
+{
+	return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	switch (port) {
+	case 0:
+		SETUP_IOMUX_PADS(usb_otg1_pads);
+		break;
+	case 1:
+		SETUP_IOMUX_PADS(usb_otg2_pads);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return 1;
+	}
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	enable_uart_clk(true);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+	setup_spinor();
+#endif
+#endif
+
+#ifdef	CONFIG_MXC_EPDC
+	enable_epdc_clock();
+	setup_epdc();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	SETUP_IOMUX_PADS(wdog_pads);
+
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_LPDDR2_BOARD
+	puts("Board: MX6SLL LPDDR2 VAL\n");
+#else
+	puts("Board: MX6SLL LPDDR3 VAL\n");
+#endif
+
+	return 0;
+}
diff --git a/board/freescale/mx6sll_val/plugin.S b/board/freescale/mx6sll_val/plugin.S
new file mode 100644
index 0000000000..61bc34e5c7
--- /dev/null
+++ b/board/freescale/mx6sll_val/plugin.S
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6sll_lpddr3_val_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x550]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x534]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x2AC]
+	str r1, [r0, #0x548]
+	str r1, [r0, #0x52C]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x530]
+	ldr r1, =0x00003030
+	str r1, [r0, #0x2B0]
+	str r1, [r0, #0x2B4]
+	str r1, [r0, #0x2B8]
+	str r1, [r0, #0x2BC]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x540]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x544]
+	str r1, [r0, #0x54C]
+	str r1, [r0, #0x554]
+	str r1, [r0, #0x558]
+	str r1, [r0, #0x294]
+	str r1, [r0, #0x298]
+	str r1, [r0, #0x29C]
+	str r1, [r0, #0x2A0]
+
+	ldr r1, =0x00082030
+	str r1, [r0, #0x2C0]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x084700C7
+	str r1, [r0, #0x85C]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x3C3A3C3C
+	str r1, [r0, #0x848]
+	ldr r1, =0x24293625
+	str r1, [r0, #0x850]
+
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	str r1, [r0, #0x824]
+	str r1, [r0, #0x828]
+
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	str r1, [r0, #0x834]
+	str r1, [r0, #0x838]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x53574333
+	str r1, [r0, #0x00C]
+	ldr r1, =0x00100B22
+	str r1, [r0, #0x010]
+	ldr r1, =0x00170778
+	str r1, [r0, #0x038]
+	ldr r1, =0x00C700DB
+	str r1, [r0, #0x014]
+	ldr r1, =0x00201718
+	str r1, [r0, #0x018]
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000005F
+	str r1, [r0, #0x040]
+	ldr r1, =0xC4190000
+	str r1, [r0, #0x000]
+
+	ldr r1, =0x00008050
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008058
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x83018030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x83018038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038038
+	str r1, [r0, #0x01C]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83C]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x020]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6sll_lpddr2_val_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x550]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x534]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x2AC]
+	str r1, [r0, #0x548]
+	str r1, [r0, #0x52C]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x530]
+	ldr r1, =0x00003030
+	str r1, [r0, #0x2B0]
+	str r1, [r0, #0x2B4]
+	str r1, [r0, #0x2B8]
+	str r1, [r0, #0x2BC]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x540]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x544]
+	str r1, [r0, #0x54C]
+	str r1, [r0, #0x554]
+	str r1, [r0, #0x558]
+	str r1, [r0, #0x294]
+	str r1, [r0, #0x298]
+	str r1, [r0, #0x29C]
+	str r1, [r0, #0x2A0]
+
+	ldr r1, =0x00082030
+	str r1, [r0, #0x2C0]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x084700C7
+	str r1, [r0, #0x85C]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x3A383C40
+	str r1, [r0, #0x848]
+	ldr r1, =0x242C3020
+	str r1, [r0, #0x850]
+
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	str r1, [r0, #0x824]
+	str r1, [r0, #0x828]
+
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	str r1, [r0, #0x834]
+	str r1, [r0, #0x838]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x53574333
+	str r1, [r0, #0x00C]
+	ldr r1, =0x00100A82
+	str r1, [r0, #0x010]
+	ldr r1, =0x00170777
+	str r1, [r0, #0x038]
+	ldr r1, =0x00C70093
+	str r1, [r0, #0x014]
+	ldr r1, =0x00201708
+	str r1, [r0, #0x018]
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000004F
+	str r1, [r0, #0x040]
+	ldr r1, =0xC3110000
+	str r1, [r0, #0x000]
+
+	ldr r1, =0x00008050
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008058
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x82018030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x82018038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038038
+	str r1, [r0, #0x01C]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83C]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x020]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	str r1, [r0, #0x06c]
+	str r1, [r0, #0x070]
+	str r1, [r0, #0x074]
+	str r1, [r0, #0x078]
+	str r1, [r0, #0x07c]
+	str r1, [r0, #0x080]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+#if defined (CONFIG_LPDDR2_BOARD)
+	imx6sll_lpddr2_val_setting
+#else
+	imx6sll_lpddr3_val_setting
+#endif
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/configs/mx6sll_lpddr2_val_defconfig b/configs/mx6sll_lpddr2_val_defconfig
new file mode 100644
index 0000000000..2b1f0434b7
--- /dev/null
+++ b/configs/mx6sll_lpddr2_val_defconfig
@@ -0,0 +1,65 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6sll_val/imximage_lpddr2.cfg"
+CONFIG_LPDDR2_BOARD=y
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6SLL_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SLL=y
+CONFIG_DM_GPIO=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr2-val"
+CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr2-val.dtb"
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
diff --git a/configs/mx6sll_lpddr3_val_defconfig b/configs/mx6sll_lpddr3_val_defconfig
new file mode 100644
index 0000000000..5cad2d7775
--- /dev/null
+++ b/configs/mx6sll_lpddr3_val_defconfig
@@ -0,0 +1,64 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6sll_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6SLL_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SLL=y
+CONFIG_DM_GPIO=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
diff --git a/configs/mx6sll_lpddr3_val_epdc_defconfig b/configs/mx6sll_lpddr3_val_epdc_defconfig
new file mode 100644
index 0000000000..497480d9e9
--- /dev/null
+++ b/configs/mx6sll_lpddr3_val_epdc_defconfig
@@ -0,0 +1,69 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6sll_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6SLL_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SLL=y
+CONFIG_DM_GPIO=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_LCD=y
+CONFIG_MXC_EPDC=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
diff --git a/configs/mx6sll_lpddr3_val_plugin_defconfig b/configs/mx6sll_lpddr3_val_plugin_defconfig
new file mode 100644
index 0000000000..a88e1e403e
--- /dev/null
+++ b/configs/mx6sll_lpddr3_val_plugin_defconfig
@@ -0,0 +1,65 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6sll_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6SLL_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SLL=y
+CONFIG_DM_GPIO=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-val.dtb"
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
diff --git a/configs/mx6sll_lpddr3_val_spinor_defconfig b/configs/mx6sll_lpddr3_val_spinor_defconfig
new file mode 100644
index 0000000000..4590d781eb
--- /dev/null
+++ b/configs/mx6sll_lpddr3_val_spinor_defconfig
@@ -0,0 +1,77 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6sll_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6SLL_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SLL=y
+CONFIG_DM_GPIO=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SPI_BOOT=y
+CONFIG_MXC_SPI=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-val-ecspi"
+CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
diff --git a/include/configs/mx6sll_val.h b/include/configs/mx6sll_val.h
new file mode 100644
index 0000000000..2939dedfe7
--- /dev/null
+++ b/include/configs/mx6sll_val.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SL EVK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+
+/* PMIC */
+#ifndef CONFIG_DM_PMIC
+#define CONFIG_POWER_LEGACY
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		"rdinit=/linuxrc " \
+		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+		"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
+		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+		"g_mass_storage.iSerialNumber=\"\" "\
+		"\0" \
+	"initrd_addr=0x86800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"epdc_waveform=epdc_splash.bin\0" \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"usb start; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+
+/* Miscellaneous configurable options */
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#ifdef CONFIG_LPDDR2_BOARD
+#define PHYS_SDRAM_SIZE			SZ_1G
+#else
+#define PHYS_SDRAM_SIZE			SZ_2G
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+
+
+#define CONFIG_IOMUX_LPSR
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+#endif
+
+
+/*#define CONFIG_MXC_EPDC  1*/
+
+/*
+ * EPDC SPLASH SCREEN Configs
+ */
+#ifdef CONFIG_MXC_EPDC
+	/*
+	 * Framebuffer and LCD
+	 */
+	#undef LCD_TEST_PATTERN
+	#define LCD_BPP					LCD_MONOCHROME
+
+	#define CONFIG_WAVEFORM_BUF_SIZE		0x400000
+#endif /* CONFIG_MXC_EPDC */
+
+#endif				/* __CONFIG_H */