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authorMarkus Klotzbuecher <mk@creamnet.de>2007-01-09 14:57:10 +0100
committerMarkus Klotzbuecher <mk@pollux.denx.de>2007-01-09 14:57:10 +0100
commitd8d9de1a02fbd880b613d607143d1f57342affc7 (patch)
treea2a120e49e0c3099f5c51a8ddbd460bb069cf69c
parent3f34f869162750e5e999fd140f884f5de952bcfe (diff)
Update the SPC1920 CMB PLD driver
-rw-r--r--board/spc1920/pld.h2
-rw-r--r--include/configs/spc1920.h16
2 files changed, 8 insertions, 10 deletions
diff --git a/board/spc1920/pld.h b/board/spc1920/pld.h
index 3254f820c1e..5beb71b5cca 100644
--- a/board/spc1920/pld.h
+++ b/board/spc1920/pld.h
@@ -5,8 +5,8 @@ typedef struct spc1920_pld {
uchar com1_en;
uchar dsp_reset;
uchar dsp_hpi_on;
+ uchar superv_mode;
uchar codec_dsp_power_en;
- uchar clk2_en;
uchar clk3_select;
uchar clk4_select;
} spc1920_pld_t;
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index 6db0d1a1c83..f8909b1d1d4 100644
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -89,7 +89,7 @@
| CFG_CMD_PING \
| CFG_CMD_DHCP \
| CFG_CMD_IMMAP \
- | CFG_CMD_I2C \
+ | CFG_CMD_I2C \
| CFG_CMD_MII)
/* & ~( CFG_CMD_NET)) */
@@ -217,9 +217,9 @@
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
+ else immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
+ else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
#endif /* CONFIG_SOFT_I2C */
#endif
@@ -386,9 +386,11 @@
#define HPI_HPID_NOINC_2 HPI_REG(0x3000000 + 2)
#endif /* CONFIG_SPC1920_HPI_TEST */
-/* PLD CS5 */
+/*
+ * PLD CS5
+ */
#define CFG_SPC1920_PLD_BASE 0x80000000
-#define CFG_PRELIM_OR5_AM 0xffff8000
+#define CFG_PRELIM_OR5_AM 0xfff00000
#define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \
OR_CSNT_SAM | \
@@ -399,10 +401,6 @@
#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
-/* #define CFG_PLD_BASE 0x30000000 */
-/* #define CFG_OR5_PRELIM 0xffff1110 */
-/* #define CFG_BR5_PRELIM 0x30000401 */
-
/*
* Internal Definitions
*