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authorAndy Fleming <afleming@freescale.com>2007-02-23 17:11:16 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2007-04-23 19:58:28 -0500
commit45cef612cc601d2d1c890fbbd7cdc9609a189a46 (patch)
tree0703d0cd9aa4c9ab200553f9f646e908b270d716
parent1f9a318cea14272edd10d63739e2d326c90f430e (diff)
Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nG
The other pagesz constants use one letter to specify order of magnitude. Also change the one reference to it in mpc8548cds/init.S Signed-off-by: Andy Fleming <afleming@freescale.com>
-rw-r--r--board/cds/mpc8548cds/init.S2
-rw-r--r--include/asm-ppc/mmu.h4
2 files changed, 3 insertions, 3 deletions
diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S
index 2c15debd488..34ca711bde4 100644
--- a/board/cds/mpc8548cds/init.S
+++ b/board/cds/mpc8548cds/init.S
@@ -161,7 +161,7 @@ tlb1_entry:
* 0xd0000000 256M Rapid IO MEM Second half
*/
.long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1GB)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 67c2c571ed8..48fd9829506 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -396,8 +396,8 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define BOOKE_PAGESZ_16M 7
#define BOOKE_PAGESZ_64M 8
#define BOOKE_PAGESZ_256M 9
-#define BOOKE_PAGESZ_1GB 10
-#define BOOKE_PAGESZ_4GB 11
+#define BOOKE_PAGESZ_1G 10
+#define BOOKE_PAGESZ_4G 11
#if defined(CONFIG_MPC86xx)
#define LAWBAR_BASE_ADDR 0x00FFFFFF