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authorYe Li <ye.li@nxp.com>2018-06-12 19:33:13 -0700
committerYe Li <ye.li@nxp.com>2018-06-13 03:06:48 -0700
commit399ed6fe78099c6895bd164179091e4be6e80393 (patch)
treee995fddcf60aa540ba42562a6bc828f1a7ead934
parentcec9f65bee49dbb8e827efee650cc1a4af106a19 (diff)
MLK-18591-14 android: iot: Add imx8m-phanbell support
Porting the imx8m-phanbell android things board support from v2017.03 Signed-off-by: Haoran.Wang <elven.wang@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat
-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/fsl-imx8mq-phanbell.dts746
-rw-r--r--arch/arm/mach-imx/imx8m/Kconfig6
-rw-r--r--board/freescale/imx8mq_phanbell/Kconfig14
-rw-r--r--board/freescale/imx8mq_phanbell/Makefile12
-rw-r--r--board/freescale/imx8mq_phanbell/ddr/ddr.h34
-rw-r--r--board/freescale/imx8mq_phanbell/ddr/ddr_init.c271
-rw-r--r--board/freescale/imx8mq_phanbell/ddr/ddrphy_train.c1144
-rw-r--r--board/freescale/imx8mq_phanbell/ddr/helper.c104
-rw-r--r--board/freescale/imx8mq_phanbell/ddr/lpddr4_dvfs.h78
-rw-r--r--board/freescale/imx8mq_phanbell/ddr/wait_ddrphy_training_complete.c96
-rw-r--r--board/freescale/imx8mq_phanbell/imx8m_phanbell.c269
-rw-r--r--board/freescale/imx8mq_phanbell/spl.c222
-rw-r--r--configs/imx8mq_phanbell_androidthings_defconfig46
-rw-r--r--include/configs/imx8mq_phanbell.h285
15 files changed, 3328 insertions, 0 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cf54ede5d67..d1e37b67560 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -461,6 +461,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
fsl-imx8mq-ddr3l-arm2.dtb \
fsl-imx8mq-ddr4-arm2.dtb \
+ fsl-imx8mq-phanbell.dtb \
fsl-imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-ddr4-arm2.dtb \
diff --git a/arch/arm/dts/fsl-imx8mq-phanbell.dts b/arch/arm/dts/fsl-imx8mq-phanbell.dts
new file mode 100644
index 00000000000..c40931f7bd7
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mq-phanbell.dts
@@ -0,0 +1,746 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x40000000 0x00020000;
+
+#include "fsl-imx8mq.dtsi"
+
+/ {
+ model = "Freescale i.MX8MQ Phanbell";
+ compatible = "fsl,imx8mq-phanbell", "fsl,imx8mq";
+
+ bcmdhd_wlan_0: bcmdhd_wlan@0 {
+ compatible = "android,bcmdhd_wlan";
+ bcmdhd_fw = "/lib/firmware/bcm/1CX_BCM4356/fw_bcmdhd.bin";
+ bcmdhd_nv = "/lib/firmware/bcm/1CX_BCM4356/bcmdhd.cal";
+ };
+
+ chosen {
+ bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
+ stdout-path = &uart1;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+ modem_reset: modem-reset {
+ compatible = "gpio-reset";
+ reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+ reset-post-delay-ms = <40>;
+ #reset-cells = <0>;
+ };
+
+ wm8524: wm8524 {
+ compatible = "wlf,wm8524";
+ clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
+ clock-names = "mclk";
+ wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ };
+
+ sound-wm8524 {
+ compatible = "fsl,imx-audio-wm8524";
+ model = "wm8524-audio";
+ audio-cpu = <&sai2>;
+ audio-codec = <&wm8524>;
+ audio-routing =
+ "Line Out Jack", "LINEVOUTL",
+ "Line Out Jack", "LINEVOUTR";
+ };
+
+ pwmleds {
+ compatible = "pwm-leds";
+
+ ledpwm2 {
+ label = "PWM2";
+ pwms = <&pwm2 0 50000>;
+ max-brightness = <255>;
+ };
+ };
+ regulator-virtuals {
+ compatible = "simple-bus";
+
+ virt-buck1 {
+ compatible = "regulator-virtual";
+ virtual-supply = "buck1";
+ };
+ virt-buck2 {
+ compatible = "regulator-virtual";
+ virtual-supply = "buck2";
+ };
+ virt-buck3 {
+ compatible = "regulator-virtual";
+ virtual-supply = "buck3";
+ };
+ virt-buck4 {
+ compatible = "regulator-virtual";
+ virtual-supply = "buck4";
+ };
+ virt-buck5 {
+ compatible = "regulator-virtual";
+ virtual-supply = "buck5";
+ };
+ virt-buck6 {
+ compatible = "regulator-virtual";
+ virtual-supply = "buck6";
+ };
+ virt-buck7 {
+ compatible = "regulator-virtual";
+ virtual-supply = "buck7";
+ };
+ virt-buck8 {
+ compatible = "regulator-virtual";
+ virtual-supply = "buck8";
+ };
+ virt-ldo1 {
+ compatible = "regulator-virtual";
+ virtual-supply = "ldo1";
+ };
+ virt-ldo2 {
+ compatible = "regulator-virtual";
+ virtual-supply = "ldo2";
+ };
+ virt-ldo3 {
+ compatible = "regulator-virtual";
+ virtual-supply = "ldo3";
+ };
+ virt-ldo4 {
+ compatible = "regulator-virtual";
+ virtual-supply = "ldo4";
+ };
+ virt-ldo5 {
+ compatible = "regulator-virtual";
+ virtual-supply = "ldo5";
+ };
+ virt-ldo6 {
+ compatible = "regulator-virtual";
+ virtual-supply = "ldo6";
+ };
+ virt-ldo7 {
+ compatible = "regulator-virtual";
+ virtual-supply = "ldo7";
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ imx8mq-evk {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
+ >;
+ };
+
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x16
+ MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
+ MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
+ >;
+ };
+
+ pinctrl_pcie1: pcie1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x16
+ MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
+ MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
+ >;
+ };
+
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
+ MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
+ MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
+ MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
+ MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
+ MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
+
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79
+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79
+ MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79
+ MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x79
+ MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x79
+ MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
+ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
+ MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
+ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 /*0x17059*/
+ >;
+ };
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ at803x,led-act-blind-workaround;
+ at803x,eee-disabled;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic: bd71837@4b {
+ reg = <0x4b>;
+ compatible = "rohm,bd71837";
+ /* PMIC BD71837 PMIC_nINT GPIO1_IO12 */
+ pinctrl-0 = <&pinctrl_pmic>;
+ gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
+
+ bd71837,pmic-buck1-uses-i2c-dvs;
+ bd71837,pmic-buck1-dvs-voltage = <900000>, <850000>, <800000>; /* VDD_SOC: Run-Idle-Suspend */
+ bd71837,pmic-buck2-uses-i2c-dvs;
+ bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
+ bd71837,pmic-buck3-uses-i2c-dvs;
+ bd71837,pmic-buck3-dvs-voltage = <1000000>, <0>, <0>; /* VDD_GPU: Run */
+ bd71837,pmic-buck4-uses-i2c-dvs;
+ bd71837,pmic-buck4-dvs-voltage = <1000000>, <0>, <0>; /* VDD_VPU: Run */
+
+ gpo {
+ rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
+ };
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ buck1_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: regulator@1 {
+ reg = <1>;
+ regulator-compatible = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck3_reg: regulator@2 {
+ reg = <2>;
+ regulator-compatible = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "buck4";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: regulator@4 {
+ reg = <4>;
+ regulator-compatible = "buck5";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: regulator@5 {
+ reg = <5>;
+ regulator-compatible = "buck6";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck7_reg: regulator@6 {
+ reg = <6>;
+ regulator-compatible = "buck7";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck8_reg: regulator@7 {
+ reg = <7>;
+ regulator-compatible = "buck8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+
+ ldo1_reg: regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: regulator@10 {
+ reg = <10>;
+ regulator-compatible = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: regulator@11 {
+ reg = <11>;
+ regulator-compatible = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: regulator@12 {
+ reg = <12>;
+ regulator-compatible = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo6_reg: regulator@13 {
+ reg = <13>;
+ regulator-compatible = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo7_reg: regulator@14 {
+ reg = <14>;
+ regulator-compatible = "ldo7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ adv7535: adv7535@3d {
+ compatible = "adi,adv7535";
+ reg = <0x3d>; /* PD pin is low */
+ /* TODO: pin config & irq */
+ video-mode = <34>; /* 1920x1080@30HZ */
+ dsi-traffic-mode = <0>;
+ bpp = <24>;
+ status = "okay";
+ port {
+ dsi_to_hdmi: endpoint {
+ remote-endpoint = <&mipi_dsi_ep>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "disabled";
+};
+
+&pcie0{
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>;
+ disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie1{
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie1>;
+ clkreq-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
+ disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>;
+ reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&uart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+ disp-dev = "mipi_dsi_northwest";
+ display = <&display0>;
+
+ display0: display@0 {
+ bits-per-pixel = <24>;
+ bus-width = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <9200000>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <8>;
+ hback-porch = <4>;
+ hsync-len = <41>;
+ vback-porch = <2>;
+ vfront-porch = <4>;
+ vsync-len = <10>;
+
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ flash0: n25q256a@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a";
+ spi-max-frequency = <29000000>;
+ spi-nor,ddr-quad-read-dummy = <6>;
+ };
+};
+
+&mipi_dsi {
+ reset = <&src>;
+ mux-sel = <&gpr>; /* lcdif or dcss */
+ status = "okay";
+ port {
+ mipi_dsi_ep: endpoint {
+ remote-endpoint = <&dsi_to_hdmi>;
+ };
+ };
+};
+
+&uart3 { /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+ fsl,uart-has-rtscts;
+ resets = <&modem_reset>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&reg_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ status = "okay";
+ dr_mode = "peripheral";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&sai2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>,
+ <&clk IMX8MQ_AUDIO_PLL1>,
+ <&clk IMX8MQ_CLK_SAI2_PRE_DIV>,
+ <&clk IMX8MQ_CLK_SAI2_DIV>;
+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>;
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&vpu {
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index a3256e76be1..1b2ea4e9e60 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -32,6 +32,11 @@ config TARGET_IMX8MQ_DDR4_ARM2
select IMX8MQ
select SUPPORT_SPL
+config TARGET_IMX8MQ_PHANBELL
+ bool "imx8mq_phanbell"
+ select IMX8MQ
+ select SUPPORT_SPL
+
config TARGET_IMX8MM_EVK
bool "imx8mm evk"
select IMX8MM
@@ -44,6 +49,7 @@ config SYS_SOC
source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mq_arm2/Kconfig"
+source "board/freescale/imx8mq_phanbell/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
endif
diff --git a/board/freescale/imx8mq_phanbell/Kconfig b/board/freescale/imx8mq_phanbell/Kconfig
new file mode 100644
index 00000000000..442d982e5f5
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_IMX8MQ_PHANBELL
+
+config SYS_BOARD
+ default "imx8mq_phanbell"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "imx8mq_phanbell"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/imx8mq_phanbell/Makefile b/board/freescale/imx8mq_phanbell/Makefile
new file mode 100644
index 00000000000..fc4b9f8ef0a
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2016 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8m_phanbell.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o
+endif
diff --git a/board/freescale/imx8mq_phanbell/ddr/ddr.h b/board/freescale/imx8mq_phanbell/ddr/ddr.h
new file mode 100644
index 00000000000..9acb29c7a5f
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/ddr/ddr.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+enum fw_type {
+ FW_1D_IMAGE,
+ FW_2D_IMAGE,
+};
+
+void ddr_init(void);
+void ddr_load_train_code(enum fw_type type);
+void lpddr4_800M_cfg_phy(void);
+
+static inline void reg32_write(unsigned long addr, u32 val)
+{
+ writel(val, addr);
+}
+
+static inline uint32_t reg32_read(unsigned long addr)
+{
+ return readl(addr);
+}
+
+static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val)
+{
+ writel(val, addr);
+}
+
+static inline void reg32setbit(unsigned long addr, u32 bit)
+{
+ setbits_le32(addr, (1 << bit));
+}
diff --git a/board/freescale/imx8mq_phanbell/ddr/ddr_init.c b/board/freescale/imx8mq_phanbell/ddr/ddr_init.c
new file mode 100644
index 00000000000..5b6a60d2346
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/ddr/ddr_init.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include "ddr.h"
+
+#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
+#define ddr_printf(args...) printf(args)
+#else
+#define ddr_printf(args...)
+#endif
+
+#include "wait_ddrphy_training_complete.c"
+#ifndef SRC_DDRC_RCR_ADDR
+#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
+#endif
+#ifndef DDR_CSD1_BASE_ADDR
+#define DDR_CSD1_BASE_ADDR 0x40000000
+#endif
+#define SILICON_TRAIN
+#define DDR_BOOT_P1 /* default DDR boot frequency point */
+#define WR_POST_EXT_3200
+
+volatile unsigned int tmp, tmp_t, i;
+void lpddr4_800MHz_cfg_umctl2(void)
+{
+ /* Start to config, default 3200mbps */
+ /* dis_dq=1, indicates no reads or writes are issued to SDRAM */
+ reg32_write(DDRC_DBG1(0), 0x00000001);
+ /* selfref_en=1, SDRAM enter self-refresh state */
+ reg32_write(DDRC_PWRCTL(0), 0x00000001);
+ reg32_write(DDRC_MSTR(0), 0xa3080020);
+ reg32_write(DDRC_MSTR2(0), 0x00000000);
+ reg32_write(DDRC_RFSHTMG(0), 0x006100E0);
+ reg32_write(DDRC_INIT0(0), 0xC003061B);
+ reg32_write(DDRC_INIT1(0), 0x009D0000);
+ reg32_write(DDRC_INIT3(0), 0x00D4002D);
+#ifdef WR_POST_EXT_3200 // recommened to define
+ reg32_write(DDRC_INIT4(0), 0x00330008);
+#else
+ reg32_write(DDRC_INIT4(0), 0x00310008);
+#endif
+ reg32_write(DDRC_INIT6(0), 0x0066004a);
+ reg32_write(DDRC_INIT7(0), 0x0006004a);
+
+ reg32_write(DDRC_DRAMTMG0(0), 0x1A201B22);
+ reg32_write(DDRC_DRAMTMG1(0), 0x00060633);
+ reg32_write(DDRC_DRAMTMG3(0), 0x00C0C000);
+ reg32_write(DDRC_DRAMTMG4(0), 0x0F04080F);
+ reg32_write(DDRC_DRAMTMG5(0), 0x02040C0C);
+ reg32_write(DDRC_DRAMTMG6(0), 0x01010007);
+ reg32_write(DDRC_DRAMTMG7(0), 0x00000401);
+ reg32_write(DDRC_DRAMTMG12(0), 0x00020600);
+ reg32_write(DDRC_DRAMTMG13(0), 0x0C100002);
+ reg32_write(DDRC_DRAMTMG14(0), 0x000000E6);
+ reg32_write(DDRC_DRAMTMG17(0), 0x00A00050);
+
+ reg32_write(DDRC_ZQCTL0(0), 0x03200018);
+ reg32_write(DDRC_ZQCTL1(0), 0x028061A8);
+ reg32_write(DDRC_ZQCTL2(0), 0x00000000);
+
+ reg32_write(DDRC_DFITMG0(0), 0x0497820A);
+ reg32_write(DDRC_DFITMG1(0), 0x00080303);
+ reg32_write(DDRC_DFIUPD0(0), 0xE0400018);
+ reg32_write(DDRC_DFIUPD1(0), 0x00DF00E4);
+ reg32_write(DDRC_DFIUPD2(0), 0x80000000);
+ reg32_write(DDRC_DFIMISC(0), 0x00000011);
+ reg32_write(DDRC_DFITMG2(0), 0x0000170A);
+
+ reg32_write(DDRC_DBICTL(0), 0x00000001);
+ reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001);
+
+ /* need be refined by ddrphy trained value */
+ reg32_write(DDRC_RANKCTL(0), 0x00000c99);
+ reg32_write(DDRC_DRAMTMG2(0), 0x070E171a);
+
+ /* address mapping */
+ /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+ reg32_write(DDRC_ADDRMAP0(0), 0x00000015);
+ reg32_write(DDRC_ADDRMAP3(0), 0x00000000);
+ /* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
+ reg32_write(DDRC_ADDRMAP4(0), 0x00001F1F);
+ /* bank interleave */
+ /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
+ reg32_write(DDRC_ADDRMAP1(0), 0x00080808);
+ /* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
+ reg32_write(DDRC_ADDRMAP5(0), 0x07070707);
+ /* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
+ reg32_write(DDRC_ADDRMAP6(0), 0x08080707);
+
+ /* 667mts frequency setting */
+ reg32_write(DDRC_FREQ1_DERATEEN(0), 0x0000000);
+ reg32_write(DDRC_FREQ1_DERATEINT(0), 0x0800000);
+ reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0210000);
+ reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x014001E);
+ reg32_write(DDRC_FREQ1_INIT3(0), 0x0140009);
+ reg32_write(DDRC_FREQ1_INIT4(0), 0x00310008);
+ reg32_write(DDRC_FREQ1_INIT6(0), 0x0066004a);
+ reg32_write(DDRC_FREQ1_INIT7(0), 0x0006004a);
+ reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0xB070A07);
+ reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x003040A);
+ reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x305080C);
+ reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x0505000);
+ reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x3040203);
+ reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x2030303);
+ reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x2020004);
+ reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000302);
+ reg32_write(DDRC_FREQ1_DRAMTMG12(0), 0x0020310);
+ reg32_write(DDRC_FREQ1_DRAMTMG13(0), 0xA100002);
+ reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x0000020);
+ reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0220011);
+ reg32_write(DDRC_FREQ1_ZQCTL0(0), 0x0A70005);
+ reg32_write(DDRC_FREQ1_DFITMG0(0), 0x3858202);
+ reg32_write(DDRC_FREQ1_DFITMG1(0), 0x0000404);
+ reg32_write(DDRC_FREQ1_DFITMG2(0), 0x0000502);
+
+ /* performance setting */
+ dwc_ddrphy_apb_wr(DDRC_ODTCFG(0), 0x0b060908);
+ dwc_ddrphy_apb_wr(DDRC_ODTMAP(0), 0x00000000);
+ dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505);
+ dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c);
+ dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b);
+ dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x00000009);
+ dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574);
+ dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016);
+ dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000);
+ dwc_ddrphy_apb_wr(DDRC_DBGCMD(0), 0x00000000);
+ dwc_ddrphy_apb_wr(DDRC_SWCTL(0), 0x00000001);
+ dwc_ddrphy_apb_wr(DDRC_POISONCFG(0), 0x00000011);
+ dwc_ddrphy_apb_wr(DDRC_PCCFG(0), 0x00000111);
+ dwc_ddrphy_apb_wr(DDRC_PCFGR_0(0), 0x000010f3);
+ dwc_ddrphy_apb_wr(DDRC_PCFGW_0(0), 0x000072ff);
+ dwc_ddrphy_apb_wr(DDRC_PCTRL_0(0), 0x00000001);
+ dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x01110d00);
+ dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x00620790);
+ dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00100001);
+ dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000041f);
+ dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEEN(0), 0x00000202);
+ dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5);
+ dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHCTL0(0), 0x00618040);
+ dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHTMG(0), 0x00610090);
+}
+
+void ddr_init(void)
+{
+ reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
+ mdelay(100);
+ reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
+
+ /* change the clock source of dram_apb_clk_root */
+ reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7<<24)|(0x7<<16));
+ reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4<<24)|(0x3<<16));
+
+ /* disable iso */
+ reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
+ reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
+
+ dram_pll_init(SSCG_PLL_OUT_800M);
+
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
+
+ /* Configure uMCTL2's registers */
+ lpddr4_800MHz_cfg_umctl2();
+
+#ifdef DDR_BOOT_P2
+ reg32_write(DDRC_MSTR2(0), 0x2);
+#else
+#ifdef DDR_BOOT_P1
+ reg32_write(DDRC_MSTR2(0), 0x1);
+#endif
+#endif
+ /* release [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n */
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
+
+ /* release [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n */
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
+
+ reg32_write(DDRC_DBG1(0), 0x00000000);
+ tmp = reg32_read(DDRC_PWRCTL(0));
+ reg32_write(DDRC_PWRCTL(0), 0x000000a8);
+
+ while ((reg32_read(DDRC_STAT(0)) & 0x33f) != 0x223)
+ ;
+
+ reg32_write(DDRC_SWCTL(0), 0x00000000);
+
+ /* LPDDR4 mode */
+ reg32_write(DDRC_DDR_SS_GPR0, 0x01);
+
+#ifdef DDR_BOOT_P1
+ reg32_write(DDRC_DFIMISC(0), 0x00000110);
+#else
+ reg32_write(DDRC_DFIMISC(0), 0x00000010);
+#endif
+ /* LPDDR4 PHY config and training */
+ lpddr4_800M_cfg_phy();
+
+ reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+
+ reg32_write(DDRC_SWCTL(0), 0x0000);
+
+ /* Set DFIMISC.dfi_init_start to 1 */
+#ifdef DDR_BOOT_P2
+ reg32_write(DDRC_DFIMISC(0), 0x00000230);
+#else
+#ifdef DDR_BOOT_P1
+ reg32_write(DDRC_DFIMISC(0), 0x00000130);
+#else
+ reg32_write(DDRC_DFIMISC(0), 0x00000030);
+#endif
+#endif
+ reg32_write(DDRC_SWCTL(0), 0x0001);
+
+ /* wait DFISTAT.dfi_init_complete to 1 */
+ while ((reg32_read(DDRC_DFISTAT(0)) & 0x1) == 0x0)
+ ;
+
+ reg32_write(DDRC_SWCTL(0), 0x0000);
+
+#ifdef DDR_BOOT_P2
+ reg32_write(DDRC_DFIMISC(0), 0x00000210);
+ /* set DFIMISC.dfi_init_complete_en again */
+ reg32_write(DDRC_DFIMISC(0), 0x00000211);
+#else
+#ifdef DDR_BOOT_P1
+ reg32_write(DDRC_DFIMISC(0), 0x00000110);
+ /* set DFIMISC.dfi_init_complete_en again */
+ reg32_write(DDRC_DFIMISC(0), 0x00000111);
+#else
+ /* clear DFIMISC.dfi_init_complete_en */
+ reg32_write(DDRC_DFIMISC(0), 0x00000010);
+ /* set DFIMISC.dfi_init_complete_en again */
+ reg32_write(DDRC_DFIMISC(0), 0x00000011);
+#endif
+#endif
+
+ reg32_write(DDRC_PWRCTL(0), 0x00000088);
+
+ tmp = reg32_read(DDRC_CRCPARSTAT(0));
+
+ /*
+ * set SWCTL.sw_done to enable quasi-dynamic register
+ * programming outside reset.
+ */
+ reg32_write(DDRC_SWCTL(0), 0x00000001);
+
+ /* wait SWSTAT.sw_done_ack to 1 */
+ while ((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0x0)
+ ;
+
+ /* wait STAT.operating_mode([1:0] for ddr3) to normal state */
+ while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
+ ;
+
+ reg32_write(DDRC_PWRCTL(0), 0x00000088);
+
+ tmp = reg32_read(DDRC_CRCPARSTAT(0));
+
+ reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+
+ tmp = reg32_read(DDRC_CRCPARSTAT(0));
+ reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+}
diff --git a/board/freescale/imx8mq_phanbell/ddr/ddrphy_train.c b/board/freescale/imx8mq_phanbell/ddr/ddrphy_train.c
new file mode 100644
index 00000000000..71776b44057
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/ddr/ddrphy_train.c
@@ -0,0 +1,1144 @@
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include "ddr.h"
+#include "lpddr4_dvfs.h"
+
+extern void wait_ddrphy_training_complete(void);
+
+void sscgpll_bypass_enable(unsigned int reg_addr)
+{
+ unsigned int read_data;
+ read_data = reg32_read(reg_addr);
+ reg32_write(reg_addr, read_data | 0x00000010);
+ read_data = reg32_read(reg_addr);
+ reg32_write(reg_addr, read_data | 0x00000020);
+}
+
+void sscgpll_bypass_disable(unsigned int reg_addr)
+{
+ unsigned int read_data;
+ read_data = reg32_read(reg_addr);
+ reg32_write(reg_addr, read_data & 0xffffffdf);
+ read_data = reg32_read(reg_addr);
+ reg32_write(reg_addr, read_data & 0xffffffef);
+}
+
+unsigned int wait_pll_lock(unsigned int reg_addr)
+{
+ unsigned int pll_lock;
+ pll_lock = reg32_read(reg_addr) >> 31;
+ return pll_lock;
+}
+
+void ddr_pll_config_freq(unsigned int freq)
+{
+ unsigned int ddr_pll_lock = 0x0;
+ sscgpll_bypass_enable(HW_DRAM_PLL_CFG0_ADDR);
+ switch (freq) {
+ case 800:
+ reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ece580);
+ break;
+ case 700:
+ reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ec4580);
+ break;
+ case 667:
+ reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ece480);
+ break;
+ case 400:
+ reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ec6984);
+ break;
+ case 167:
+ reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00f5a406);
+ break;
+ case 100:
+ reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x015dea96);
+ break;
+ default:
+ printf("Input freq=%d error.\n",freq);
+ }
+
+ sscgpll_bypass_disable(HW_DRAM_PLL_CFG0_ADDR);
+ while (ddr_pll_lock != 0x1) {
+ ddr_pll_lock = wait_pll_lock(HW_DRAM_PLL_CFG0_ADDR);
+ }
+}
+
+void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate)
+{
+ if (pstate == 0x1) {
+ reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7<<24)|(0x7<<16));
+ reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4<<24)|(0x4<<16)); /* to source 4 --800MHz/5 */
+ ddr_pll_config_freq(167);
+ } else {
+ ddr_pll_config_freq(800);
+ reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7<<24)|(0x7<<16));
+ reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4<<24)|(0x3<<16)); /* to source 4 --800MHz/4 */
+ }
+}
+
+void lpddr4_800M_cfg_phy(void)
+{
+ printf("start to config phy: p0=3200mts, p1=667mts with 1D2D training\n");
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20110, 0x02); /* MapCAB0toDFI */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20111, 0x03); /* MapCAB1toDFI */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20112, 0x04); /* MapCAB2toDFI */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20113, 0x05); /* MapCAB3toDFI */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20114, 0x00); /* MapCAB4toDFI */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20115, 0x01); /* MapCAB5toDFI */
+
+ /* Initialize PHY Configuration */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1005f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1015f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1105f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1115f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1205f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1215f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1305f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1315f, 0x1ff);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11005f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11015f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11105f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11115f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11205f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11215f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11305f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11315f, 0x1ff);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21005f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21015f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21105f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21115f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21205f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21215f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21305f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21315f, 0x1ff);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x55, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200c5, 0x19);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200c5, 0x7);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200c5, 0x7);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002e, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002e, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002e, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90204, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x190204, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x290204, 0x0);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20024, 0xe3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120024, 0xa3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220024, 0xa3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20056, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120056, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220056, 0xa);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1004d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1014d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1104d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1114d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1204d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1214d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1304d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1314d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11004d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11014d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11104d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11114d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11204d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11214d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11304d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11314d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21004d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21014d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21104d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21114d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21204d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21214d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21304d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21314d, 0xe00);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13149, 0xfbe);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113149, 0xfbe);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213149, 0xfbe);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x43, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9043, 0x63);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20018, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20075, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20050, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20008, 0x320);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120008, 0xa7);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220008, 0x19);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200b2, 0x104);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200b2, 0x104);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200b2, 0x104);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200fa, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200fa, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200fa, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20019, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120019, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220019, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f0, 0x600);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f1, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f2, 0x4444);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f3, 0x8888);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f4, 0x5655);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f5, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f6, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f7, 0xf000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002d, 0x0);
+
+ /* Load the 1D IMEM image */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ ddr_load_train_code(FW_1D_IMAGE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* Set the PHY input clocks for pstate 0 */
+ dwc_ddrphy_phyinit_userCustom_E_setDfiClk (0);
+ /* Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ printf("config to do 3200 1d training.\n");
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, ((LPDDR4_PHY_RON<<8) | LPDDR4_PHY_RTT));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, LPDDR4_PHY_VREF_VALUE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x131f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, LPDDR4_HDT_CTL_3200_1D);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x3));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, LPDDR4_MR22_RANK0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, (((LPDDR4_RON) << 3) | 0x3));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, LPDDR4_MR22_RANK1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, (LPDDR4_MR22_RANK0 << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54040, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54041, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54042, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54043, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54044, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+
+ /* wait for train complete */
+ wait_ddrphy_training_complete();
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* Load the 2D IMEM image */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ ddr_load_train_code(FW_2D_IMAGE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* 3200 mts 2D training */
+ printf("config to do 3200 2d training.\n");
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, LPDDR4_PHY_VREF_VALUE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x61);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, LPDDR4_HDT_CTL_2D);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, LPDDR4_2D_WEIGHT);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x3));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, LPDDR4_MR22_RANK0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, (((LPDDR4_RON) << 3) | 0x3));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, LPDDR4_MR22_RANK1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, (LPDDR4_MR22_RANK0 << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54040, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54041, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54042, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54043, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54044, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+
+ /* wait for train complete */
+ wait_ddrphy_training_complete();
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* Step (E) Set the PHY input clocks for pstate 1 */
+ dwc_ddrphy_phyinit_userCustom_E_setDfiClk (1);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ ddr_load_train_code(FW_1D_IMAGE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ printf("pstate=1: set dfi clk done done\n");
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0x29c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, LPDDR4_PHY_VREF_VALUE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x121f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0xc8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x914);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x1));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x6);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x914);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, (((LPDDR4_RON) << 3) | 0x1));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, LPDDR4_MR22_RANK1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0x1400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x600);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0x1400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54040, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54041, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54042, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54043, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+
+ /* wait for train complete */
+ wait_ddrphy_training_complete();
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* (I) Load PHY Init Engine Image */
+ printf("Load 201711 PIE\n");
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90000, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90001, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90002, 0x10e);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90003, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90004, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90005, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90029, 0xb);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002a, 0x480);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002b, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002c, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002d, 0x448);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002e, 0x139);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90030, 0x478);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90031, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90032, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90033, 0xe8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90034, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90035, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90036, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90037, 0x139);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90038, 0xb);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90039, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003a, 0x139);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003b, 0x44);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003c, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003d, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003e, 0x14f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003f, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90040, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90041, 0x47);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90042, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90043, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90044, 0x4f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90045, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90046, 0x179);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90047, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90048, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90049, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004b, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004c, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004e, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90050, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90051, 0x45a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90052, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90053, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90054, 0x448);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90055, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90056, 0x40);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90057, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90058, 0x179);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90059, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005a, 0x618);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005b, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005c, 0x40c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005d, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005e, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90060, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90061, 0x48);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90062, 0x4040);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90063, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90064, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90065, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90066, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90067, 0x48);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90068, 0x40);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90069, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006a, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006b, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006c, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006d, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006f, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90070, 0x78);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90071, 0x549);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90072, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90073, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90074, 0xd49);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90075, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90076, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90077, 0x94a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90078, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90079, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007a, 0x441);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007b, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007c, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007d, 0x42);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007e, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007f, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90080, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90081, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90082, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90083, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90084, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90085, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90086, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90087, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90088, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90089, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008a, 0x3c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008b, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008c, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008d, 0x3c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008e, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008f, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90090, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90091, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90092, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90093, 0x3c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90094, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90095, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90096, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90097, 0x48);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90098, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90099, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009a, 0x58);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009b, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009c, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009d, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009e, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009f, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a0, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a1, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a2, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a3, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a4, 0xd);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a5, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a6, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a7, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a8, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a9, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40000, 0x811);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40020, 0x880);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40040, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40060, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40001, 0x4008);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40021, 0x83);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40041, 0x4f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40061, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40002, 0x4040);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40022, 0x83);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40042, 0x51);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40062, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40003, 0x811);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40023, 0x880);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40043, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40063, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40004, 0x720);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40024, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40044, 0x1740);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40064, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40005, 0x16);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40025, 0x83);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40045, 0x4b);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40065, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40006, 0x716);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40026, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40046, 0x2001);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40066, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40007, 0x716);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40027, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40047, 0x2800);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40067, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40008, 0x716);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40028, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40048, 0xf00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40068, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40009, 0x720);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40029, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40049, 0x1400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40069, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000a, 0xe08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002a, 0xc15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000b, 0x623);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002b, 0x15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004b, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006b, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000c, 0x4028);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002c, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000d, 0xe08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002d, 0xc1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000e, 0x623);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002e, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000f, 0x4040);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002f, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40010, 0x2604);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40030, 0x15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40050, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40070, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40011, 0x708);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40031, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40051, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40071, 0x2002);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40012, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40032, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40052, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40072, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40013, 0x2604);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40033, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40053, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40073, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40014, 0x708);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40034, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40054, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40074, 0x2002);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40015, 0x4040);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40035, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40055, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40075, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40016, 0x60a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40036, 0x15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40056, 0x1200);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40076, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40017, 0x61a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40037, 0x15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40057, 0x1300);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40077, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40018, 0x60a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40038, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40058, 0x1200);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40078, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40019, 0x642);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40039, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40059, 0x1300);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40079, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4001a, 0x4808);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4003a, 0x880);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4005a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4007a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900aa, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ab, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ac, 0x11a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ad, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ae, 0x7aa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900af, 0x2a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b0, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b1, 0x7b2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b2, 0x2a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b3, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b4, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b5, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b6, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b7, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b8, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b9, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ba, 0x2a8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bb, 0x129);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bc, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bd, 0x370);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900be, 0x129);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bf, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c0, 0x3c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c1, 0x1a9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c2, 0xc);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c3, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c4, 0x199);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c5, 0x14);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c6, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c7, 0x11a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c8, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c9, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ca, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cb, 0xe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cc, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cd, 0x199);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ce, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cf, 0x8568);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d0, 0x108);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d1, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d2, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d3, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d4, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d5, 0x1d8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d6, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d7, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d8, 0x8558);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d9, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900da, 0x70);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900db, 0x788);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dc, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dd, 0x1ff8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900de, 0x85a8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900df, 0x1e8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e0, 0x50);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e1, 0x798);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e2, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e3, 0x60);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e4, 0x7a0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e5, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e6, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e7, 0x8310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e8, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e9, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ea, 0xa310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900eb, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ec, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ed, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ee, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ef, 0x6e);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f0, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f1, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f2, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f3, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f4, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f5, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f6, 0x8310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f7, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f8, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f9, 0xa310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fa, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fb, 0x1ff8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fc, 0x85a8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fd, 0x1e8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fe, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ff, 0x798);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90100, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90101, 0x78);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90102, 0x7a0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90103, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90104, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90105, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90106, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90107, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90108, 0x8b10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90109, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010a, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010b, 0xab10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010c, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010d, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010e, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010f, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90110, 0x58);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90111, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90112, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90113, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90114, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90115, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90116, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90117, 0x8b10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90118, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90119, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011a, 0xab10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011b, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011d, 0x1d8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011e, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011f, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90120, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90121, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90122, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90123, 0x7aa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90124, 0x6a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90125, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90126, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90127, 0x1e9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90128, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90129, 0x8080);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012a, 0x108);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012b, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012c, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012d, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012e, 0xc);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90130, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90131, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90132, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90133, 0x1a9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90134, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90135, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90136, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90137, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90138, 0x8080);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90139, 0x108);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013a, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013b, 0x7aa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013c, 0x6a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013e, 0x8568);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013f, 0x108);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90140, 0xb7);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90141, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90142, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90143, 0x1f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90144, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90145, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90146, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90147, 0x8558);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90148, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90149, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014a, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014b, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014c, 0xc);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014e, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90150, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90151, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90152, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90153, 0x8558);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90154, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90155, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90156, 0x3c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90157, 0x1a9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90158, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90159, 0x370);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015a, 0x129);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015b, 0x20);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015c, 0x2aa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015d, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015f, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90160, 0x10e);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90161, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90162, 0xe8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90163, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90164, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90165, 0x8140);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90166, 0x10c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90167, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90168, 0x8138);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90169, 0x10c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016a, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016b, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016c, 0x101);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016d, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90170, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90171, 0x448);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90172, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90173, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90174, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90175, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90176, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90177, 0xe8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90178, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90179, 0x47);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017a, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017b, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017c, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017d, 0x618);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017e, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90180, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90181, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90182, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90183, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90184, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90185, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90186, 0x8140);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90187, 0x10c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90188, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90189, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018a, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018b, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018c, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018d, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018e, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018f, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90190, 0x101);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90006, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90008, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90009, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000b, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd00e7, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9001f, 0x2b);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90026, 0x6c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d0, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d1, 0x101);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d2, 0x105);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d3, 0x107);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d4, 0x10f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d5, 0x202);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d6, 0x20a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d7, 0x20b);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000b, 0x64);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000c, 0xc8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000d, 0x7d0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000e, 0x2c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000b, 0x14);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000c, 0x29);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000d, 0x1a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000e, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000b, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000c, 0x6);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000d, 0x3e);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000e, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000d, 0x173);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000e, 0x60);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000f, 0x6110);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90010, 0x2152);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90011, 0xdfbd);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90012, 0x60);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90013, 0x6152);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20010, 0x5a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20011, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40080, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40081, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40082, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40083, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40084, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40085, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140080, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140081, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140082, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140083, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140084, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140085, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240080, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240081, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240082, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240083, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240084, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240085, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400fd, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10011, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10012, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10013, 0x180);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10018, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10002, 0x6209);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x100b2, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x101b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x102b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x103b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x104b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x105b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x106b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x107b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x108b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11011, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11012, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11013, 0x180);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11018, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11002, 0x6209);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110b2, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x114b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x115b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x116b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x117b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x118b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12011, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12012, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12013, 0x180);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12018, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002, 0x6209);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120b2, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x121b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x122b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x123b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x124b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x125b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x126b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x127b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x128b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13011, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13012, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13013, 0x180);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13018, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13002, 0x6209);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x130b2, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x131b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x132b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x133b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x134b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x135b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x136b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x137b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x138b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20089, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x19);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xc0080, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+}
diff --git a/board/freescale/imx8mq_phanbell/ddr/helper.c b/board/freescale/imx8mq_phanbell/ddr/helper.c
new file mode 100644
index 00000000000..3cd44e8bfdf
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/ddr/helper.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/sections.h>
+
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMEM_LEN 32768//23400 //byte
+#define DMEM_LEN 16384//1720 //byte
+#define IMEM_2D_OFFSET 49152
+
+#define IMEM_OFFSET_ADDR 0x00050000
+#define DMEM_OFFSET_ADDR 0x00054000
+#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+
+/* We need PHY iMEM PHY is 32KB padded */
+void ddr_load_train_code(enum fw_type type)
+{
+ u32 tmp32, i;
+ u32 error = 0;
+ unsigned long pr_to32, pr_from32;
+ unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
+ unsigned long imem_start = (unsigned long)&_end + fw_offset;
+ unsigned long dmem_start = imem_start + IMEM_LEN;
+
+ pr_from32 = imem_start;
+ pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+ for(i = 0x0; i < IMEM_LEN; ){
+ tmp32 = readl(pr_from32);
+ writew(tmp32 & 0x0000ffff, pr_to32);
+ pr_to32 += 4;
+ writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+ pr_to32 += 4;
+ pr_from32 += 4;
+ i += 4;
+ }
+
+ pr_from32 = dmem_start;
+ pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+ for(i = 0x0; i < DMEM_LEN;){
+ tmp32 = readl(pr_from32);
+ writew(tmp32 & 0x0000ffff, pr_to32);
+ pr_to32 += 4;
+ writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+ pr_to32 += 4;
+ pr_from32 += 4;
+ i += 4;
+ }
+
+ printf("check ddr4_pmu_train_imem code\n");
+ pr_from32 = imem_start;
+ pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+ for(i = 0x0; i < IMEM_LEN;){
+ tmp32 = (readw(pr_to32) & 0x0000ffff);
+ pr_to32 += 4;
+ tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+
+ if(tmp32 != readl(pr_from32)){
+ printf("%lx %lx\n", pr_from32, pr_to32);
+ error++;
+ }
+ pr_from32 += 4;
+ pr_to32 += 4;
+ i += 4;
+ }
+ if(error){
+ printf("check ddr4_pmu_train_imem code fail=%d\n",error);
+ }else{
+ printf("check ddr4_pmu_train_imem code pass\n");
+ }
+
+ printf("check ddr4_pmu_train_dmem code\n");
+ pr_from32 = dmem_start;
+ pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+ for(i = 0x0; i < DMEM_LEN;){
+ tmp32 = (readw(pr_to32) & 0x0000ffff);
+ pr_to32 += 4;
+ tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+ if(tmp32 != readl(pr_from32)){
+ printf("%lx %lx\n", pr_from32, pr_to32);
+ error++;
+ }
+ pr_from32 += 4;
+ pr_to32 += 4;
+ i += 4;
+ }
+
+ if(error){
+ printf("check ddr4_pmu_train_dmem code fail=%d",error);
+ }else{
+ printf("check ddr4_pmu_train_dmem code pass\n");
+ }
+}
diff --git a/board/freescale/imx8mq_phanbell/ddr/lpddr4_dvfs.h b/board/freescale/imx8mq_phanbell/ddr/lpddr4_dvfs.h
new file mode 100644
index 00000000000..60d5dd4438f
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/ddr/lpddr4_dvfs.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LPDDR4_DVFS_H__
+#define __LPDDR4_DVFS_H__
+#include <asm/arch/ddr.h>
+
+#define DFILP_SPT
+
+#define ANAMIX_PLL_BASE_ADDR 0x30360000
+#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
+#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
+#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
+
+#define LPDDR4_HDT_CTL_2D 0xC8 /* stage completion */
+#define LPDDR4_HDT_CTL_3200_1D 0xC8 /* stage completion */
+#define LPDDR4_HDT_CTL_400_1D 0xC8 /* stage completion */
+#define LPDDR4_HDT_CTL_100_1D 0xC8 /* stage completion */
+
+/* 2D share & weight */
+#define LPDDR4_2D_WEIGHT 0x1f7f
+#define LPDDR4_2D_SHARE 1
+#define LPDDR4_CATRAIN_3200_1d 0
+#define LPDDR4_CATRAIN_400 0
+#define LPDDR4_CATRAIN_100 0
+#define LPDDR4_CATRAIN_3200_2d 0
+
+#define WR_POST_EXT_3200 /* recommened to define */
+
+/* lpddr4 phy training config */
+/* for LPDDR4 Rtt */
+#define LPDDR4_RTT40 6
+#define LPDDR4_RTT48 5
+#define LPDDR4_RTT60 4
+#define LPDDR4_RTT80 3
+#define LPDDR4_RTT120 2
+#define LPDDR4_RTT240 1
+#define LPDDR4_RTT_DIS 0
+
+/* for LPDDR4 Ron */
+#define LPDDR4_RON34 7
+#define LPDDR4_RON40 6
+#define LPDDR4_RON48 5
+#define LPDDR4_RON60 4
+#define LPDDR4_RON80 3
+
+#define LPDDR4_PHY_ADDR_RON60 0x1
+#define LPDDR4_PHY_ADDR_RON40 0x3
+#define LPDDR4_PHY_ADDR_RON30 0x7
+#define LPDDR4_PHY_ADDR_RON24 0xf
+#define LPDDR4_PHY_ADDR_RON20 0x1f
+
+/* for read channel */
+#define LPDDR4_RON LPDDR4_RON40 /* MR3[5:3] */
+#define LPDDR4_PHY_RTT 30
+#define LPDDR4_PHY_VREF_VALUE 17
+
+/* for write channel */
+#define LPDDR4_PHY_RON 30
+#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40
+#define LPDDR4_RTT_DQ LPDDR4_RTT40 /* MR11[2:0] */
+#define LPDDR4_RTT_CA LPDDR4_RTT40 /* MR11[6:4] */
+#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 /* MR11[6:4] */
+#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 /* LPDDR4_RTT_DIS//MR11[6:4] */
+#define LPDDR4_VREF_VALUE_CA ((1<<6)|(0xd)) /*((0<<6)|(0xe)) MR12 */
+#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1<<6)|(0xd)) /* MR14 */
+#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1<<6)|(0xd)) /* MR14 */
+#define LPDDR4_MR22_RANK0 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
+#define LPDDR4_MR22_RANK1 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
+#define LPDDR4_MR3_PU_CAL 1 /* MR3[0] */
+
+#define LPDDR4_2D_WEIGHT 0x1f7f
+#define LPDDR4_2D_SHARE 1
+
+#endif /*__LPDDR4_DVFS_H__ */
diff --git a/board/freescale/imx8mq_phanbell/ddr/wait_ddrphy_training_complete.c b/board/freescale/imx8mq_phanbell/ddr/wait_ddrphy_training_complete.c
new file mode 100644
index 00000000000..0b42e58bd1d
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/ddr/wait_ddrphy_training_complete.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+static inline void poll_pmu_message_ready(void)
+{
+ unsigned int reg;
+
+ do {
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
+ } while (reg & 0x1);
+}
+
+static inline void ack_pmu_message_recieve(void)
+{
+ unsigned int reg;
+
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0);
+
+ do {
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
+ } while (!(reg & 0x1));
+
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1);
+}
+
+static inline unsigned int get_mail(void)
+{
+ unsigned int reg;
+
+ poll_pmu_message_ready();
+
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
+
+ ack_pmu_message_recieve();
+
+ return reg;
+}
+
+static inline unsigned int get_stream_message(void)
+{
+ unsigned int reg, reg2;
+
+ poll_pmu_message_ready();
+
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
+
+ reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
+
+ reg2 = (reg2 << 16) | reg;
+
+ ack_pmu_message_recieve();
+
+ return reg2;
+}
+
+static inline void decode_major_message(unsigned int mail)
+{
+ ddr_printf("[PMU Major message = 0x%08x]\n", mail);
+}
+
+static inline void decode_streaming_message(void)
+{
+ unsigned int string_index, arg __maybe_unused;
+ int i = 0;
+
+ string_index = get_stream_message();
+ ddr_printf(" PMU String index = 0x%08x\n", string_index);
+ while (i < (string_index & 0xffff)){
+ arg = get_stream_message();
+ ddr_printf(" arg[%d] = 0x%08x\n", i, arg);
+ i++;
+ }
+
+ ddr_printf("\n");
+}
+
+void wait_ddrphy_training_complete(void)
+{
+ unsigned int mail;
+ while (1) {
+ mail = get_mail();
+ decode_major_message(mail);
+ if (mail == 0x08) {
+ decode_streaming_message();
+ } else if (mail == 0x07) {
+ printf("Training PASS\n");
+ break;
+ } else if (mail == 0xff) {
+ printf("Training FAILED\n");
+ break;
+ }
+ }
+}
diff --git a/board/freescale/imx8mq_phanbell/imx8m_phanbell.c b/board/freescale/imx8mq_phanbell/imx8m_phanbell.c
new file mode 100644
index 00000000000..d672255e123
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/imx8m_phanbell.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <power/pmic.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_QSPI
+static iomux_v3_cfg_t const qspi_pads[] = {
+ IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+ IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+ IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+ IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+ IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+ IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+};
+
+int board_qspi_init(void)
+{
+ imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
+
+ set_clk_qspi();
+
+ return 0;
+}
+#endif
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
+{
+ /* TODO */
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ /* rom_pointer[1] contains the size of TEE occupies */
+ if (rom_pointer[1])
+ gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+ else
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
+static iomux_v3_cfg_t const fec1_rst_pads[] = {
+ IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
+ ARRAY_SIZE(fec1_rst_pads));
+
+ gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
+ gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
+ udelay(500);
+ gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+ = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+
+ setup_iomux_fec();
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
+ return set_clk_enet(ENET_125MHZ);
+}
+
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_DWC3
+
+#define USB_PHY_CTRL0 0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN BIT(2)
+
+#define USB_PHY_CTRL1 0xF0044
+#define USB_PHY_CTRL1_RESET BIT(0)
+#define USB_PHY_CTRL1_COMMONONN BIT(1)
+#define USB_PHY_CTRL1_ATERESET BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0 BIT(20)
+
+#define USB_PHY_CTRL2 0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0 BIT(8)
+
+static struct dwc3_device dwc3_device_data = {
+ .maximum_speed = USB_SPEED_SUPER,
+ .base = USB1_BASE_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+ .power_down_scale = 2,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+ dwc3_uboot_handle_interrupt(0);
+ return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+ u32 RegData;
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL1);
+ RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+ USB_PHY_CTRL1_COMMONONN);
+ RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+ writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL0);
+ RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+ writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL2);
+ RegData |= USB_PHY_CTRL2_TXENABLEN0;
+ writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL1);
+ RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+ writel(RegData, dwc3->base + USB_PHY_CTRL1);
+}
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+int board_usb_init(int index, enum usb_init_type init)
+{
+ imx8m_usb_power(index, true);
+
+ if (index == 0 && init == USB_INIT_DEVICE) {
+ dwc3_nxp_usb_phy_init(&dwc3_device_data);
+ return dwc3_uboot_init(&dwc3_device_data);
+ }
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ if (index == 0 && init == USB_INIT_DEVICE) {
+ dwc3_uboot_exit(index);
+ }
+
+ imx8m_usb_power(index, false);
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ board_qspi_init();
+
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+ init_usb_clk();
+#endif
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", "Phanbell");
+ setenv("board_rev", "iMX8MQ");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_env_init();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+ return 0; /*TODO*/
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
diff --git a/board/freescale/imx8mq_phanbell/spl.c b/board/freescale/imx8mq_phanbell/spl.c
new file mode 100644
index 00000000000..9223bb8ab2d
--- /dev/null
+++ b/board/freescale/imx8mq_phanbell/spl.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <power/pmic.h>
+#include <power/bd71837.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include "ddr/ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_dram_init(void)
+{
+ /* ddr init */
+ ddr_init();
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+ .gp = IMX_GPIO_NR(5, 14),
+ },
+ .sda = {
+ .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+ .gp = IMX_GPIO_NR(5, 15),
+ },
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = 1;
+ break;
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ return ret;
+ }
+
+ return 1;
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+ PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+ IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+ IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+ IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR, 0, 8},
+ {USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+ gpio_direction_output(USDHC1_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC1_PWR_GPIO, 1);
+ break;
+ case 1:
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg;
+
+ ret = power_bd71837_init(I2C_PMIC);
+ if (ret)
+ printf("power init failed");
+
+ p = pmic_get("BD71837");
+ pmic_probe(p);
+
+ /* unlock the PMIC regs */
+ pmic_reg_write(p, BD71837_REGLOCK, 0x1);
+
+ /* Set BUCK5 output for DRAM to 1.0V */
+ pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x3);
+
+ /* lock the PMIC regs */
+ pmic_reg_write(p, BD71837_REGLOCK, 0x11);
+ return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+ enable_tzc380();
+
+ /* Adjust pmic voltage to 1.0V for 800M */
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Serial download mode */
+ if (is_usb_boot()) {
+ puts("Back to ROM, SDP\n");
+ restore_boot_params();
+ }
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ arch_cpu_init();
+
+ init_uart_clk(0); /* Init UART0 clock */
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
diff --git a/configs/imx8mq_phanbell_androidthings_defconfig b/configs/imx8mq_phanbell_androidthings_defconfig
new file mode 100644
index 00000000000..c42c377be84
--- /dev/null
+++ b/configs/imx8mq_phanbell_androidthings_defconfig
@@ -0,0 +1,46 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_IMX8MQ_PHANBELL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_THINGS_SUPPORT"
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_LIBFDT=y
+CONFIG_BOOTDELAY=3
+CONFIG_FS_FAT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-phanbell"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_PMIC=y
+CONFIG_NXP_TMU=y
+CONFIG_DM_THERMAL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_ANDROID_BOOT_IMAGE=y
diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h
new file mode 100644
index 00000000000..6ea9986d347
--- /dev/null
+++ b/include/configs/imx8mq_phanbell.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX8M_PHANBELL_
+#define __IMX8M_PHANBELL_
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
+#endif
+
+#define CONFIG_SPL_TEXT_BASE 0x7E1000
+#define CONFIG_SPL_MAX_SIZE (124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x187FF0
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_BSS_START_ADDR 0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x00182000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_BD71837
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_BOARD_LATE_INIT
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_PHY_GIGE
+#define IMX_FEC_BASE 0x30BE0000
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+ "rdinit=/linuxrc " \
+ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+ "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+ "g_mass_storage.iSerialNumber=\"\" "\
+ "clk_ignore_unused "\
+ "\0" \
+ "initrd_addr=0x43800000\0" \
+ "initrd_high=0xffffffff\0" \
+ "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_MFG_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=Image\0" \
+ "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
+ "fdt_addr=0x43000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "boot_fdt=try\0" \
+ "fdt_file=fsl-imx8mq-phanbell.dtb\0" \
+ "initrd_addr=0x43800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "echo wait for boot; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "booti; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (64 * SZ_64K)
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+
+/* Monitor Command Prompt */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT "u-boot=> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_FSL_QSPI /* enable the QUADSPI driver */
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 40000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+
+#define FSL_QSPI_FLASH_SIZE (SZ_32M)
+#define FSL_QSPI_FLASH_NUM 1
+#endif
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_OCOTP
+#define CONFIG_CMD_FUSE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USB_XHCI_IMX8M
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI_HCD
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_USB_DWC3
+#define CONFIG_USB_DWC3_GADGET
+#define CONFIG_USBD_HS
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+
+#define CONFIG_USB_GADGET_VENDOR_NUM 0x18d1
+#define CONFIG_USB_GADGET_PRODUCT_NUM 0x0d02
+#define CONFIG_USB_GADGET_MANUFACTURER "FSL"
+
+#endif
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+#if defined (CONFIG_ANDROID_THINGS_SUPPORT)
+#include "imx8mq_evk_androidthings.h"
+#endif
+#endif
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-16 05:34:53 +0000