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authorPuneet Saxena <puneets@nvidia.com>2012-01-24 12:47:28 +0530
committerPuneet Saxena <puneets@nvidia.com>2012-02-07 02:01:10 -0800
commit64cd650224e8f66ef3d9965ada17a95a643a65f7 (patch)
tree2654759602acbf73f37d059d094770a825f2f0a6
parent5fbb64cdebd43d7f39c537748471436271a9e33a (diff)
tegra: Change parent clock for Tegra2 and Tegra3
Set display parent clock separately for Tegra2 and Tegra3. BUG=chromium-os:23496 TEST=Built ok for Cardhu Walgui and Seaboard. Tested on Waluigi. Change-Id: Ie03d37b8dda77dcfcb72e70c34e769a23323e598 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14697
-rw-r--r--arch/arm/cpu/armv7/tegra-common/display.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/tegra-common/display.c b/arch/arm/cpu/armv7/tegra-common/display.c
index a653f3aa270..2f12084447c 100644
--- a/arch/arm/cpu/armv7/tegra-common/display.c
+++ b/arch/arm/cpu/armv7/tegra-common/display.c
@@ -117,10 +117,16 @@ static int update_display_mode(struct dc_disp_reg *disp,
/*
* The pixel clock divider is in 7.1 format (where the bottom bit
* represents 0.5). Here we calculate the divider needed to get from
- * the display clock (typically 600MHz) to the pixel clock. We round
- * up or down as requried.
+ * the display clock (typically 600MHz for tegra2 and 216MHZ
+ * for tegra3) to the pixel clock. We round up or down as requried.
*/
+#if defined(CONFIG_TEGRA2)
rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
+#endif
+#if defined(CONFIG_TEGRA3)
+ rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_PERIPH);
+#endif
+
div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2;
debug("Display clock %lu, divider %lu\n", rate, div);