arm: Remove aspenite board

This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last armada100 platform, remove that support
as well.

Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

22 files changed, 0 insertions, 1122 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1b1767d7ba..6675a633f8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -551,11 +551,6 @@ config ARCH_AT91
 	select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
 	select SPL_SEPARATE_BSS if SPL
 
-config TARGET_ASPENITE
-	bool "Support aspenite"
-	select CPU_ARM926EJS
-	select GPIO_EXTRA_HEADER
-
 config ARCH_DAVINCI
 	bool "TI DaVinci"
 	select CPU_ARM926EJS
@@ -2144,7 +2139,6 @@ source "board/armltd/total_compute/Kconfig"
 
 source "board/bosch/shc/Kconfig"
 source "board/bosch/guardian/Kconfig"
-source "board/Marvell/aspenite/Kconfig"
 source "board/Marvell/octeontx/Kconfig"
 source "board/Marvell/octeontx2/Kconfig"
 source "board/armltd/vexpress/Kconfig"
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 98aafe805a..a6b29af8f4 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -12,7 +12,6 @@ extra-y	:=
 endif
 endif
 
-obj-$(CONFIG_ARMADA100) += armada100/
 obj-$(CONFIG_MX25) += mx25/
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile
deleted file mode 100644
index 77ac0e2624..0000000000
--- a/arch/arm/cpu/arm926ejs/armada100/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2010
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-
-obj-y	= cpu.o timer.o dram.o
diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c
deleted file mode 100644
index 96726b3144..0000000000
--- a/arch/arm/cpu/arm926ejs/armada100/cpu.c
+++ /dev/null
@@ -1,93 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <init.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/armada100.h>
-
-#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID	(1<<8)
-#define L2C_RAM_SEL	(1<<4)
-
-int arch_cpu_init(void)
-{
-	u32 val;
-	struct armd1cpu_registers *cpuregs =
-		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
-
-	struct armd1apb1_registers *apb1clkres =
-		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
-
-	struct armd1mpmu_registers *mpmu =
-		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
-
-	/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
-	val = readl(&cpuregs->cpu_conf);
-	val = val | SET_MRVL_ID;
-	writel(val, &cpuregs->cpu_conf);
-
-	/* Enable Clocks for all hardware units */
-	writel(0xFFFFFFFF, &mpmu->acgr);
-
-	/* Turn on AIB and AIB-APB Functional clock */
-	writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
-
-	/* ensure L2 cache is not mapped as SRAM */
-	val = readl(&cpuregs->cpu_conf);
-	val = val & ~(L2C_RAM_SEL);
-	writel(val, &cpuregs->cpu_conf);
-
-	/* Enable GPIO clock */
-	writel(APBC_APBCLK, &apb1clkres->gpio);
-
-#ifdef CONFIG_I2C_MV
-	/* Enable general I2C clock */
-	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
-	writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
-
-	/* Enable power I2C clock */
-	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
-	writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
-#endif
-
-	/*
-	 * Enable Functional and APB clock at 14.7456MHz
-	 * for configured UART console
-	 */
-#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
-	writel(UARTCLK14745KHZ, &apb1clkres->uart3);
-#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
-	writel(UARTCLK14745KHZ, &apb1clkres->uart2);
-#else
-	writel(UARTCLK14745KHZ, &apb1clkres->uart1);
-#endif
-	icache_enable();
-
-	return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	u32 id;
-	struct armd1cpu_registers *cpuregs =
-		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
-
-	id = readl(&cpuregs->chip_id);
-	printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_I2C_MV
-void i2c_clk_enable(void)
-{
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c
deleted file mode 100644
index c97b5b1940..0000000000
--- a/arch/arm/cpu/arm926ejs/armada100/dram.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/armada100.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * ARMADA100 DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet Appendix A.17
- */
-struct armd1ddr_map_registers {
-	u32	cs;	/* Memory Address Map Register -CS */
-	u32	pad[3];
-};
-
-struct armd1ddr_registers {
-	u8	pad[0x100 - 0x000];
-	struct armd1ddr_map_registers mmap[2];
-};
-
-/*
- * armd1_sdram_base - reads SDRAM Base Address Register
- */
-u32 armd1_sdram_base(int chip_sel)
-{
-	struct armd1ddr_registers *ddr_regs =
-		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
-	u32 result = 0;
-	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
-	if (!CS_valid)
-		return 0;
-
-	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
-	return result;
-}
-
-/*
- * armd1_sdram_size - reads SDRAM size
- */
-u32 armd1_sdram_size(int chip_sel)
-{
-	struct armd1ddr_registers *ddr_regs =
-		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
-	u32 result = 0;
-	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
-	if (!CS_valid)
-		return 0;
-
-	result = readl(&ddr_regs->mmap[chip_sel].cs);
-	result = (result >> 16) & 0xF;
-	if (result < 0x7) {
-		printf("Unknown DRAM Size\n");
-		return -1;
-	} else {
-		return ((0x8 << (result - 0x7)) * 1024 * 1024);
-	}
-}
-
-int dram_init(void)
-{
-	int i;
-
-	gd->ram_size = 0;
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = armd1_sdram_base(i);
-		gd->bd->bi_dram[i].size = armd1_sdram_size(i);
-		/*
-		 * It is assumed that all memory banks are consecutive
-		 * and without gaps.
-		 * If the gap is found, ram_size will be reported for
-		 * consecutive memory only
-		 */
-		if (gd->bd->bi_dram[i].start != gd->ram_size)
-			break;
-
-		gd->ram_size += gd->bd->bi_dram[i].size;
-
-	}
-
-	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
-		/* If above loop terminated prematurely, we need to set
-		 * remaining banks' start address & size as 0. Otherwise other
-		 * u-boot functions and Linux kernel gets wrong values which
-		 * could result in crash */
-		gd->bd->bi_dram[i].start = 0;
-		gd->bd->bi_dram[i].size = 0;
-	}
-	return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-int dram_init_banksize(void)
-{
-	dram_init();
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
deleted file mode 100644
index 4b96d4aa91..0000000000
--- a/arch/arm/cpu/arm926ejs/armada100/timer.c
+++ /dev/null
@@ -1,198 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <init.h>
-#include <time.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/armada100.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-/*
- * Timer registers
- * Refer Section A.6 in Datasheet
- */
-struct armd1tmr_registers {
-	u32 clk_ctrl;	/* Timer clk control reg */
-	u32 match[9];	/* Timer match registers */
-	u32 count[3];	/* Timer count registers */
-	u32 status[3];
-	u32 ie[3];
-	u32 preload[3];	/* Timer preload value */
-	u32 preload_ctrl[3];
-	u32 wdt_match_en;
-	u32 wdt_match_r;
-	u32 wdt_val;
-	u32 wdt_sts;
-	u32 icr[3];
-	u32 wdt_icr;
-	u32 cer;	/* Timer count enable reg */
-	u32 cmr;
-	u32 ilr[3];
-	u32 wcr;
-	u32 wfar;
-	u32 wsar;
-	u32 cvwr;
-};
-
-#define TIMER			0	/* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x)		((3 * TIMER) + x)
-#define TIMER_LOAD_VAL		0xffffffff
-#define	COUNT_RD_REQ		0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
-
-/* For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
-	struct armd1tmr_registers *armd1timers =
-		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
-	volatile int loop=100;
-
-	writel(COUNT_RD_REQ, &armd1timers->cvwr);
-	while (loop--);
-	return(readl(&armd1timers->cvwr));
-}
-
-static ulong get_timer_masked(void)
-{
-	ulong now = read_timer();
-
-	if (now >= gd->arch.tbl) {
-		/* normal mode */
-		gd->arch.tbu += now - gd->arch.tbl;
-	} else {
-		/* we have an overflow ... */
-		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
-	}
-	gd->arch.tbl = now;
-
-	return gd->arch.tbu;
-}
-
-ulong get_timer(ulong base)
-{
-	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
-		base);
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong delayticks;
-	ulong endtime;
-
-	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
-	endtime = get_timer_masked() + delayticks;
-
-	while (get_timer_masked() < endtime);
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
-	struct armd1apb1_registers *apb1clkres =
-		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
-	struct armd1tmr_registers *armd1timers =
-		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
-
-	/* Enable Timer clock at 3.25 MHZ */
-	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
-	/* load value into timer */
-	writel(0x0, &armd1timers->clk_ctrl);
-	/* Use Timer 0 Match Resiger 0 */
-	writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
-	/* Preload value is 0 */
-	writel(0x0, &armd1timers->preload[TIMER]);
-	/* Enable match comparator 0 for Timer 0 */
-	writel(0x1, &armd1timers->preload_ctrl[TIMER]);
-
-	/* Enable timer 0 */
-	writel(0x1, &armd1timers->cer);
-	/* init the gd->arch.tbu and gd->arch.tbl value */
-	gd->arch.tbl = read_timer();
-	gd->arch.tbu = 0;
-
-	return 0;
-}
-
-#define MPMU_APRR_WDTR	(1<<4)
-#define TMR_WFAR	0xbaba	/* WDT Register First key */
-#define TMP_WSAR	0xeb10	/* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu(void)
-{
-	struct armd1mpmu_registers *mpmu =
-		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
-	struct armd1tmr_registers *armd1timers =
-		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
-	u32 val;
-
-	/* negate hardware reset to the WDT after system reset */
-	val = readl(&mpmu->aprr);
-	val = val | MPMU_APRR_WDTR;
-	writel(val, &mpmu->aprr);
-
-	/* reset/enable WDT clock */
-	writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
-	readl(&mpmu->wdtpcr);
-	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
-	readl(&mpmu->wdtpcr);
-
-	/* clear previous WDT status */
-	writel(TMR_WFAR, &armd1timers->wfar);
-	writel(TMP_WSAR, &armd1timers->wsar);
-	writel(0, &armd1timers->wdt_sts);
-
-	/* set match counter */
-	writel(TMR_WFAR, &armd1timers->wfar);
-	writel(TMP_WSAR, &armd1timers->wsar);
-	writel(0xf, &armd1timers->wdt_match_r);
-
-	/* enable WDT reset */
-	writel(TMR_WFAR, &armd1timers->wfar);
-	writel(TMP_WSAR, &armd1timers->wsar);
-	writel(0x3, &armd1timers->wdt_match_en);
-
-	while(1);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return (ulong)CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
deleted file mode 100644
index dd21ad3c60..0000000000
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#ifndef _ASM_ARCH_ARMADA100_H
-#define _ASM_ARCH_ARMADA100_H
-
-#if defined (CONFIG_ARMADA100)
-
-/* Common APB clock register bit definitions */
-#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
-#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
-#define APBC_RST        (1<<2)  /* Reset Generation */
-/* Functional Clock Selection Mask */
-#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
-
-/* Fast Ethernet Controller Clock register definition */
-#define FE_CLK_RST		0x1
-#define FE_CLK_ENA		0x8
-
-/* SSP2 Clock Control */
-#define SSP2_APBCLK		0x01
-#define SSP2_FNCLK		0x02
-
-/* USB Clock/reset control bits */
-#define USB_SPH_AXICLK_EN	0x10
-#define USB_SPH_AXI_RST		0x02
-
-/* MPMU Clocks */
-#define APB2_26M_EN		(1 << 20)
-#define AP_26M			(1 << 4)
-
-/* Register Base Addresses */
-#define ARMD1_DRAM_BASE		0xB0000000
-#define ARMD1_FEC_BASE		0xC0800000
-#define ARMD1_TIMER_BASE	0xD4014000
-#define ARMD1_APBC1_BASE	0xD4015000
-#define ARMD1_APBC2_BASE	0xD4015800
-#define ARMD1_UART1_BASE	0xD4017000
-#define ARMD1_UART2_BASE	0xD4018000
-#define ARMD1_GPIO_BASE		0xD4019000
-#define ARMD1_SSP1_BASE		0xD401B000
-#define ARMD1_SSP2_BASE		0xD401C000
-#define ARMD1_MFPR_BASE		0xD401E000
-#define ARMD1_SSP3_BASE		0xD401F000
-#define ARMD1_SSP4_BASE		0xD4020000
-#define ARMD1_SSP5_BASE		0xD4021000
-#define ARMD1_UART3_BASE	0xD4026000
-#define ARMD1_MPMU_BASE		0xD4050000
-#define ARMD1_USB_HOST_BASE	0xD4209000
-#define ARMD1_APMU_BASE		0xD4282800
-#define ARMD1_CPU_BASE		0xD4282C00
-
-#endif /* CONFIG_ARMADA100 */
-#endif /* _ASM_ARCH_ARMADA100_H */
diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
deleted file mode 100644
index 2862dd072b..0000000000
--- a/arch/arm/include/asm/arch-armada100/config.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- */
-
-/*
- * This file should be included in board config header file.
- *
- * It supports common definitions for Armada100 platform
- */
-
-#ifndef _ARMD1_CONFIG_H
-#define _ARMD1_CONFIG_H
-
-#include <asm/arch/armada100.h>
-
-#define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
-#define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
-#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
-#define MV_MFPR_BASE		ARMD1_MFPR_BASE
-#define MV_UART_CONSOLE_BASE	ARMD1_UART1_BASE
-#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
-						represents UART Unit Enable */
-
-#endif /* _ARMD1_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h
deleted file mode 100644
index cd5e5051d5..0000000000
--- a/arch/arm/include/asm/arch-armada100/cpu.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#ifndef _ARMADA100CPU_H
-#define _ARMADA100CPU_H
-
-#include <asm/io.h>
-#include <asm/system.h>
-
-/*
- * Main Power Management (MPMU) Registers
- * Refer Datasheet Appendix A.8
- */
-struct armd1mpmu_registers {
-	u8 pad0[0x08 - 0x00];
-	u32 fccr;	/*0x0008*/
-	u32 pocr;	/*0x000c*/
-	u32 posr;	/*0x0010*/
-	u32 succr;	/*0x0014*/
-	u8 pad1[0x030 - 0x014 - 4];
-	u32 gpcr;	/*0x0030*/
-	u8 pad2[0x200 - 0x030 - 4];
-	u32 wdtpcr;	/*0x0200*/
-	u8 pad3[0x1000 - 0x200 - 4];
-	u32 apcr;	/*0x1000*/
-	u32 apsr;	/*0x1004*/
-	u8 pad4[0x1020 - 0x1004 - 4];
-	u32 aprr;	/*0x1020*/
-	u32 acgr;	/*0x1024*/
-	u32 arsr;	/*0x1028*/
-};
-
-/*
- * Application Subsystem Power Management
- * Refer Datasheet Appendix A.9
- */
-struct armd1apmu_registers {
-	u32 pcr;		/* 0x000 */
-	u32 ccr;		/* 0x004 */
-	u32 pad1;
-	u32 ccsr;		/* 0x00C */
-	u32 fc_timer;		/* 0x010 */
-	u32 pad2;
-	u32 ideal_cfg;		/* 0x018 */
-	u8 pad3[0x04C - 0x018 - 4];
-	u32 lcdcrc;		/* 0x04C */
-	u32 cciccrc;		/* 0x050 */
-	u32 sd1crc;		/* 0x054 */
-	u32 sd2crc;		/* 0x058 */
-	u32 usbcrc;		/* 0x05C */
-	u32 nfccrc;		/* 0x060 */
-	u32 dmacrc;		/* 0x064 */
-	u32 pad4;
-	u32 buscrc;		/* 0x06C */
-	u8 pad5[0x07C - 0x06C - 4];
-	u32 wake_clr;		/* 0x07C */
-	u8 pad6[0x090 - 0x07C - 4];
-	u32 core_status;	/* 0x090 */
-	u32 rfsc;		/* 0x094 */
-	u32 imr;		/* 0x098 */
-	u32 irwc;		/* 0x09C */
-	u32 isr;		/* 0x0A0 */
-	u8 pad7[0x0B0 - 0x0A0 - 4];
-	u32 mhst;		/* 0x0B0 */
-	u32 msr;		/* 0x0B4 */
-	u8 pad8[0x0C0 - 0x0B4 - 4];
-	u32 msst;		/* 0x0C0 */
-	u32 pllss;		/* 0x0C4 */
-	u32 smb;		/* 0x0C8 */
-	u32 gccrc;		/* 0x0CC */
-	u8 pad9[0x0D4 - 0x0CC - 4];
-	u32 smccrc;		/* 0x0D4 */
-	u32 pad10;
-	u32 xdcrc;		/* 0x0DC */
-	u32 sd3crc;		/* 0x0E0 */
-	u32 sd4crc;		/* 0x0E4 */
-	u8 pad11[0x0F0 - 0x0E4 - 4];
-	u32 cfcrc;		/* 0x0F0 */
-	u32 mspcrc;		/* 0x0F4 */
-	u32 cmucrc;		/* 0x0F8 */
-	u32 fecrc;		/* 0x0FC */
-	u32 pciecrc;		/* 0x100 */
-	u32 epdcrc;		/* 0x104 */
-};
-
-/*
- * APB1 Clock Reset/Control Registers
- * Refer Datasheet Appendix A.10
- */
-struct armd1apb1_registers {
-	u32 uart1;	/*0x000*/
-	u32 uart2;	/*0x004*/
-	u32 gpio;	/*0x008*/
-	u32 pwm1;	/*0x00c*/
-	u32 pwm2;	/*0x010*/
-	u32 pwm3;	/*0x014*/
-	u32 pwm4;	/*0x018*/
-	u8 pad0[0x028 - 0x018 - 4];
-	u32 rtc;	/*0x028*/
-	u32 twsi0;	/*0x02c*/
-	u32 kpc;	/*0x030*/
-	u32 timers;	/*0x034*/
-	u8 pad1[0x03c - 0x034 - 4];
-	u32 aib;	/*0x03c*/
-	u32 sw_jtag;	/*0x040*/
-	u32 timer1;	/*0x044*/
-	u32 onewire;	/*0x048*/
-	u8 pad2[0x050 - 0x048 - 4];
-	u32 asfar;	/*0x050 AIB Secure First Access Reg*/
-	u32 assar;	/*0x054 AIB Secure Second Access Reg*/
-	u8 pad3[0x06c - 0x054 - 4];
-	u32 twsi1;	/*0x06c*/
-	u32 uart3;	/*0x070*/
-	u8 pad4[0x07c - 0x070 - 4];
-	u32 timer2;	/*0x07C*/
-	u8 pad5[0x084 - 0x07c - 4];
-	u32 ac97;	/*0x084*/
-};
-
-/*
-* APB2 Clock Reset/Control Registers
-* Refer Datasheet Appendix A.11
-*/
-struct armd1apb2_registers {
-	u32 pad1[0x01C - 0x000];
-	u32 ssp1_clkrst;		/* 0x01C */
-	u32 ssp2_clkrst;		/* 0x020 */
-	u32 pad2[0x04C - 0x020 - 4];
-	u32 ssp3_clkrst;		/* 0x04C */
-	u32 pad3[0x058 - 0x04C - 4];
-	u32 ssp4_clkrst;		/* 0x058 */
-	u32 ssp5_clkrst;		/* 0x05C */
-};
-
-/*
- * CPU Interface Registers
- * Refer Datasheet Appendix A.2
- */
-struct armd1cpu_registers {
-	u32 chip_id;		/* Chip Id Reg */
-	u32 pad;
-	u32 cpu_conf;		/* CPU Conf Reg */
-	u32 pad1;
-	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
-	u32 pad2;
-	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
-	u32 mcb_conf;		/* MCB Conf Reg */
-	u32 sys_boot_ctl;	/* Sytem Boot Control */
-};
-
-/*
- * Functions
- */
-u32 armd1_sdram_base(int);
-u32 armd1_sdram_size(int);
-
-#endif /* _ARMADA100CPU_H */
diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h
deleted file mode 100644
index b85f6a53d9..0000000000
--- a/arch/arm/include/asm/arch-armada100/gpio.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <contact@8051projects.net>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- */
-
-#ifndef _ASM_ARCH_GPIO_H
-#define _ASM_ARCH_GPIO_H
-
-#include <asm/types.h>
-#include <asm/arch/armada100.h>
-
-#define GPIO_HIGH		1
-#define GPIO_LOW		0
-
-#define GPIO_TO_REG(gp)		(gp >> 5)
-#define GPIO_TO_BIT(gp)		(1 << (gp & 0x1F))
-#define GPIO_VAL(gp, val)	((val >> (gp & 0x1F)) & 0x01)
-
-static inline void *get_gpio_base(int bank)
-{
-	const unsigned int offset[4] = {0, 4, 8, 0x100};
-	/* gpio register bank offset - refer Appendix A.36 */
-	return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
-}
-
-#endif /* _ASM_ARCH_GPIO_H */
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h
deleted file mode 100644
index cd837eaef4..0000000000
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
- * (C) Copyright 2007
- * Marvell Semiconductor <www.marvell.com>
- * 2007-08-21: eric miao <eric.miao@marvell.com>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#ifndef __ARMADA100_MFP_H
-#define __ARMADA100_MFP_H
-
-/*
- * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
- *
- *				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-/* UART1 */
-#define MFP107_UART1_TXD	(MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
-#define MFP107_UART1_RXD	(MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
-#define MFP108_UART1_RXD	(MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
-#define MFP108_UART1_TXD	(MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
-#define MFP109_UART1_CTS	(MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP109_UART1_RTS	(MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP110_UART1_RTS	(MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP110_UART1_CTS	(MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP111_UART1_RI		(MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP111_UART1_DSR	(MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP112_UART1_DTR	(MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP112_UART1_DCD	(MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* UART2 */
-#define MFP47_UART2_RXD		(MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP48_UART2_TXD		(MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP88_UART2_RXD		(MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP89_UART2_TXD		(MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* UART3 */
-#define MFPO8_UART3_TXD		(MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFPO9_UART3_RXD		(MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* I2c */
-#define MFP105_CI2C_SDA		(MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-#define MFP106_CI2C_SCL		(MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
-
-/* Fast Ethernet */
-#define MFP086_ETH_TXCLK	(MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP087_ETH_TXEN		(MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP088_ETH_TXDQ3	(MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP089_ETH_TXDQ2	(MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP090_ETH_TXDQ1	(MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP091_ETH_TXDQ0	(MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP092_ETH_CRS		(MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP093_ETH_COL		(MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP094_ETH_RXCLK	(MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP095_ETH_RXER		(MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP096_ETH_RXDQ3	(MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP097_ETH_RXDQ2	(MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP098_ETH_RXDQ1	(MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP099_ETH_RXDQ0	(MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP100_ETH_MDC		(MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP101_ETH_MDIO		(MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-#define MFP103_ETH_RXDV		(MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
-
-/* SPI */
-#define MFP107_SSP2_RXD		(MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
-#define MFP108_SSP2_TXD		(MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM)
-#define MFP110_SSP2_CS		(MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP111_SSP2_CLK		(MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
-
-/* More macros can be defined here... */
-
-#define MFP_PIN_MAX	117
-
-#endif /* __ARMADA100_MFP_H */
diff --git a/arch/arm/include/asm/arch-armada100/spi.h b/arch/arm/include/asm/arch-armada100/spi.h
deleted file mode 100644
index 873ba6e91c..0000000000
--- a/arch/arm/include/asm/arch-armada100/spi.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <contact@8051projects.net>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- */
-
-#ifndef __ARMADA100_SPI_H_
-#define __ARMADA100_SPI_H_
-
-#include <asm/arch/armada100.h>
-
-#define CAT_BASE_ADDR(x)	ARMD1_SSP ## x ## _BASE
-#define SSP_REG_BASE(x)		CAT_BASE_ADDR(x)
-
-/*
- * SSP Serial Port Registers
- * refer Appendix A.26
- */
-struct ssp_reg {
-	u32 sscr0;	/* SSP Control Register 0 - 0x000 */
-	u32 sscr1;	/* SSP Control Register 1 - 0x004 */
-	u32 sssr;	/* SSP Status Register - 0x008 */
-	u32 ssitr;	/* SSP Interrupt Test Register - 0x00C */
-	u32 ssdr;	/* SSP Data Register - 0x010 */
-	u32 pad1[5];
-	u32 ssto;	/* SSP Timeout Register - 0x028 */
-	u32 sspsp;	/* SSP Programmable Serial Protocol Register - 0x02C */
-	u32 sstsa;	/* SSP TX Timeslot Active Register - 0x030 */
-	u32 ssrsa;	/* SSP RX Timeslot Active Register - 0x034 */
-	u32 sstss;	/* SSP Timeslot Status Register - 0x038 */
-};
-
-#define DEFAULT_WORD_LEN	8
-#define SSP_FLUSH_NUM		0x2000
-#define RX_THRESH_DEF		8
-#define TX_THRESH_DEF		8
-#define TIMEOUT_DEF		1000
-
-#define SSCR1_RIE	(1 << 0)	/* Receive FIFO Interrupt Enable */
-#define SSCR1_TIE	(1 << 1)	/* Transmit FIFO Interrupt Enable */
-#define SSCR1_LBM	(1 << 2)	/* Loop-Back Mode */
-#define SSCR1_SPO	(1 << 3)	/* Motorola SPI SSPSCLK polarity
-					   setting */
-#define SSCR1_SPH	(1 << 4)	/* Motorola SPI SSPSCLK phase setting */
-#define SSCR1_MWDS	(1 << 5)	/* Microwire Transmit Data Size */
-#define SSCR1_TFT	0x03c0		/* Transmit FIFO Threshold (mask) */
-#define SSCR1_RFT	0x3c00		/* Receive FIFO Threshold (mask) */
-
-#define SSCR1_TXTRESH(x)	((x - 1) << 6)	/* level [1..16] */
-#define SSCR1_RXTRESH(x)	((x - 1) << 10)	/* level [1..16] */
-#define SSCR1_TINTE		(1 << 19)	/* Receiver Time-out
-						   Interrupt enable */
-
-#define SSCR0_DSS		0x0f		/* Data Size Select (mask) */
-#define SSCR0_DATASIZE(x)	(x - 1)		/* Data Size Select [4..16] */
-#define SSCR0_FRF		0x30		/* FRame Format (mask) */
-#define SSCR0_MOTO		(0x0 << 4)	/* Motorola's Serial
-						   Peripheral Interface */
-#define SSCR0_TI		(0x1 << 4)	/* TI's Synchronous
-						   Serial Protocol (SSP) */
-#define SSCR0_NATIONAL		(0x2 << 4)	/* National Microwire */
-#define SSCR0_ECS		(1 << 6)	/* External clock select */
-#define SSCR0_SSE		(1 << 7)	/* Synchronous Serial Port
-						   Enable */
-
-#define SSSR_TNF	(1 << 2)	/* Transmit FIFO Not Full */
-#define SSSR_RNE	(1 << 3)	/* Receive FIFO Not Empty */
-#define SSSR_BSY	(1 << 4)	/* SSP Busy */
-#define SSSR_TFS	(1 << 5)	/* Transmit FIFO Service Request */
-#define SSSR_RFS	(1 << 6)	/* Receive FIFO Service Request */
-#define SSSR_ROR	(1 << 7)	/* Receive FIFO Overrun */
-#define SSSR_TINT	(1 << 19)	/* Receiver Time-out Interrupt */
-
-#endif /* __ARMADA100_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-armada100/utmi-armada100.h b/arch/arm/include/asm/arch-armada100/utmi-armada100.h
deleted file mode 100644
index 28147f42ac..0000000000
--- a/arch/arm/include/asm/arch-armada100/utmi-armada100.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2012
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <contact@8051projects.net>
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- */
-
-#ifndef __UTMI_ARMADA100__
-#define __UTMI_ARMADA100__
-
-#define UTMI_PHY_BASE		0xD4206000
-
-/* utmi_ctrl - bits */
-#define INPKT_DELAY_SOF		(1 << 28)
-#define PLL_PWR_UP		2
-#define PHY_PWR_UP		1
-
-/* utmi_pll - bits */
-#define PLL_FBDIV_MASK		0x00000FF0
-#define PLL_FBDIV		4
-#define PLL_REFDIV_MASK		0x0000000F
-#define PLL_REFDIV		0
-#define PLL_READY		0x800000
-#define VCOCAL_START		(1 << 21)
-
-#define N_DIVIDER		0xEE
-#define M_DIVIDER		0x0B
-
-/* utmi_tx - bits */
-#define CK60_PHSEL		17
-#define PHSEL_VAL		0x4
-#define RCAL_START		(1 << 12)
-
-/*
- * USB PHY registers
- * Refer Datasheet Appendix A.21
- */
-struct armd1usb_phy_reg {
-	u32 utmi_rev;	/* USB PHY Revision */
-	u32 utmi_ctrl;	/* USB PHY Control register */
-	u32 utmi_pll;	/* PLL register */
-	u32 utmi_tx;	/* Tx register */
-	u32 utmi_rx;	/* Rx register */
-	u32 utmi_ivref;	/* IVREF register */
-	u32 utmi_tst_g0;	/* Test group 0 register */
-	u32 utmi_tst_g1;	/* Test group 1 register */
-	u32 utmi_tst_g2;	/* Test group 2 register */
-	u32 utmi_tst_g3;	/* Test group 3 register */
-	u32 utmi_tst_g4;	/* Test group 4 register */
-	u32 utmi_tst_g5;	/* Test group 5 register */
-	u32 utmi_reserve;	/* Reserve Register */
-	u32 utmi_usb_int;	/* USB interuppt register */
-	u32 utmi_dbg_ctl;	/* Debug control register */
-	u32 utmi_otg_addon;	/* OTG addon register */
-};
-
-int utmi_init(void);
-
-#endif /* __UTMI_ARMADA100__ */
diff --git a/board/Marvell/aspenite/Kconfig b/board/Marvell/aspenite/Kconfig
deleted file mode 100644
index 4dd49c4452..0000000000
--- a/board/Marvell/aspenite/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_ASPENITE
-
-config SYS_BOARD
-	default "aspenite"
-
-config SYS_VENDOR
-	default "Marvell"
-
-config SYS_SOC
-	default "armada100"
-
-config SYS_CONFIG_NAME
-	default "aspenite"
-
-endif
diff --git a/board/Marvell/aspenite/MAINTAINERS b/board/Marvell/aspenite/MAINTAINERS
deleted file mode 100644
index a77d30eb78..0000000000
--- a/board/Marvell/aspenite/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ASPENITE BOARD
-M:	Prafulla Wadaskar <prafulla@marvell.com>
-S:	Maintained
-F:	board/Marvell/aspenite/
-F:	include/configs/aspenite.h
-F:	configs/aspenite_defconfig
diff --git a/board/Marvell/aspenite/Makefile b/board/Marvell/aspenite/Makefile
deleted file mode 100644
index f67a978a12..0000000000
--- a/board/Marvell/aspenite/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2010
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-# Contributor: Mahavir Jain <mjain@marvell.com>
-
-obj-y	:= aspenite.o
diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c
deleted file mode 100644
index 1f9389c0a7..0000000000
--- a/board/Marvell/aspenite/aspenite.c
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <mvmfp.h>
-#include <asm/global_data.h>
-#include <asm/mach-types.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mfp.h>
-#include <asm/arch/armada100.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	u32 mfp_cfg[] = {
-		/* I2C */
-		MFP105_CI2C_SDA,
-		MFP106_CI2C_SCL,
-
-		/* Enable Console on UART1 */
-		MFP107_UART1_RXD,
-		MFP108_UART1_TXD,
-
-		MFP_EOC		/*End of configureation*/
-	};
-	/* configure MFP's */
-	mfp_config(mfp_cfg);
-	return 0;
-}
-
-int board_init(void)
-{
-	/* arch number of Board */
-	gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
-	return 0;
-}
diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig
deleted file mode 100644
index b85f7241b6..0000000000
--- a/configs/aspenite_defconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_TARGET_ASPENITE=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x20000
-CONFIG_IDENT_STRING="\nMarvell-Aspenite DB"
-CONFIG_SYS_LOAD_ADDR=0x800000
-CONFIG_BOOTDELAY=3
-CONFIG_USE_PREBOOT=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
-# CONFIG_MMC is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 18917488c2..a9dc546a20 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_IPROC_GPIO)	+= iproc_gpio.o
 obj-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
 obj-$(CONFIG_KONA_GPIO)	+= kona_gpio.o
 obj-$(CONFIG_MARVELL_GPIO)	+= mvgpio.o
-obj-$(CONFIG_MARVELL_MFP)	+= mvmfp.o
 obj-$(CONFIG_MCP230XX_GPIO)	+= mcp230xx_gpio.o
 obj-$(CONFIG_MXC_GPIO)	+= mxc_gpio.o
 obj-$(CONFIG_MXS_GPIO)	+= mxs_gpio.o
diff --git a/drivers/gpio/mvmfp.c b/drivers/gpio/mvmfp.c
deleted file mode 100644
index 511042c199..0000000000
--- a/drivers/gpio/mvmfp.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <mvmfp.h>
-#include <asm/arch/mfp.h>
-
-/*
- * mfp_config
- *
- * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin
- * configuration registers to configure each GPIO/Function pin on the
- * SoC.
- *
- * This function reads the array of values for
- * MFPR_X registers and programms them into respective
- * Multi-Function Pin registers.
- * It supports - Alternate Function Selection programming.
- *
- * Whereas,
- * The Configureation value is constructed using MFP()
- * array consists of 32bit values as defined in MFP(xx,xx..) macro
- */
-void mfp_config(u32 *mfp_cfgs)
-{
-	u32 *p_mfpr = NULL;
-	u32 cfg_val, val;
-
-	do {
-		cfg_val = *mfp_cfgs++;
-		/* exit if End of configuration table detected */
-		if (cfg_val == MFP_EOC)
-			break;
-
-		p_mfpr = (u32 *)(MV_MFPR_BASE
-				+ MFP_REG_GET_OFFSET(cfg_val));
-
-		/* Write a mfg register as per configuration */
-		val = 0;
-		if (cfg_val & MFP_VALUE_MASK)
-			val |= cfg_val & MFP_VALUE_MASK;
-
-		writel(val, p_mfpr);
-	} while (1);
-	/*
-	 * perform a read-back of any MFPR register to make sure the
-	 * previous writings are finished
-	 */
-	readl(p_mfpr);
-}
diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index 591137f50e..336ebf1410 100644
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -44,29 +44,6 @@ static void sdhci_mvebu_mbus_config(void __iomem *base)
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 static struct sdhci_ops mv_ops;
-
-#if defined(CONFIG_SHEEVA_88SV331xV5)
-#define SD_CE_ATA_2	0xEA
-#define  MMC_CARD	0x1000
-#define  MMC_WIDTH	0x0100
-static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
-{
-	struct mmc *mmc = host->mmc;
-	u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
-
-	if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
-		if (mmc->bus_width == 8)
-			writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);
-		else
-			writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);
-	}
-
-	writeb(val, host->ioaddr + reg);
-}
-
-#else
-#define mv_sdhci_writeb	NULL
-#endif /* CONFIG_SHEEVA_88SV331xV5 */
 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
 
 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
@@ -84,7 +61,6 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
 	host->max_clk = max_clk;
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 	memset(&mv_ops, 0, sizeof(struct sdhci_ops));
-	mv_ops.write_b = mv_sdhci_writeb;
 	host->ops = &mv_ops;
 #endif
 
diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h
deleted file mode 100644
index 4a25d56165..0000000000
--- a/include/configs/aspenite.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- * Contributor: Mahavir Jain <mjain@marvell.com>
- */
-
-#ifndef __CONFIG_ASPENITE_H
-#define __CONFIG_ASPENITE_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_SHEEVA_88SV331xV5	1	/* CPU Core subversion */
-#define CONFIG_ARMADA100		1	/* SOC Family Name */
-
-/*
- * There is no internal RAM in ARMADA100, using DRAM
- * TBD: dcache to be used for this
- */
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - 0x00200000)
-
-#include "mv-common.h"
-
-/*
- * Environment variables configurations
- */
-
-#endif	/* __CONFIG_ASPENITE_H */