ARM: dts: renesas: Add RZ/A1 GR-Peach board

Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach,
which is a cheap development platform with RZ/A1H SoC. The
DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Currently supported are UART, ethernet and RPC SPI. The board
can be booted from RPC SPI by writing the u-boot.bin binary
to the beginning of the SPI NOR, e.g. using the "sf" command.
The board can also be booted via JTAG by setting text base to
0x20020000, loading u-boot.bin there via JTAG and executing it
from that address.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

11 files changed, 513 insertions, 0 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8e082f2840..a199f3f988 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -603,6 +603,9 @@ dtb-$(CONFIG_RCAR_GEN3) += \
 	r8a77990-ebisu-u-boot.dtb \
 	r8a77995-draak-u-boot.dtb
 
+dtb-$(CONFIG_RZA1) += \
+	r7s72100-gr-peach-u-boot.dtb
+
 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
 	keystone-k2l-evm.dtb \
 	keystone-k2e-evm.dtb \
diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
new file mode 100644
index 0000000000..28247d19d7
--- /dev/null
+++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the GR Peach board
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include "r7s72100-gr-peach.dts"
+
+/ {
+	aliases {
+		spi0 = &rpc;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+
+	leds {
+		led1 {
+			label = "peach:bottom:red";
+		};
+
+		led-red {
+			label = "peach:tri:red";
+			gpios = <&port6 13 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-green {
+			label = "peach:tri:green";
+			gpios = <&port6 14 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-blue {
+			label = "peach:tri:blue";
+			gpios = <&port6 15 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	rpc: rpc@0xee200000 {
+		compatible = "renesas,rpc-r7s72100", "renesas,rpc";
+		reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>;
+		bank-width = <2>;
+		num-cs = <1>;
+		status = "okay";
+		spi-max-frequency = <50000000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		flash0: spi-flash@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "jedec,spi-nor";
+			spi-max-frequency = <50000000>;
+			spi-tx-bus-width = <1>;
+			spi-rx-bus-width = <1>;
+			reg = <0>;
+			status = "okay";
+		};
+	};
+};
+
+&ostm0 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&scif2 {
+	u-boot,dm-pre-reloc;
+	clock = <66666666>;	/* ToDo: Replace by DM clock driver */
+};
+
+&scif2_pins {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/r7s72100-gr-peach.dts b/arch/arm/dts/r7s72100-gr-peach.dts
new file mode 100644
index 0000000000..fe1a4aa4d7
--- /dev/null
+++ b/arch/arm/dts/r7s72100-gr-peach.dts
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the GR-Peach board
+ *
+ * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ * Copyright (C) 2016 Renesas Electronics
+ */
+
+/dts-v1/;
+#include "r7s72100.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
+
+/ {
+	model = "GR-Peach";
+	compatible = "renesas,gr-peach", "renesas,r7s72100";
+
+	aliases {
+		serial0 = &scif2;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@20000000 {
+		device_type = "memory";
+		reg = <0x20000000 0x00a00000>;
+	};
+
+	lbsc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
+	flash@18000000 {
+		compatible = "mtd-rom";
+		probe-type = "map_rom";
+		reg = <0x18000000 0x00800000>;
+		bank-width = <4>;
+		device-width = <1>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		rootfs@600000 {
+			label = "rootfs";
+			reg = <0x00600000 0x00200000>;
+		};
+	};
+
+	leds {
+		status = "okay";
+		compatible = "gpio-leds";
+
+		led1 {
+			gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&pinctrl {
+	scif2_pins: serial2 {
+		/* P6_2 as RxD2; P6_3 as TxD2 */
+		pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
+	};
+
+	ether_pins: ether {
+		/* Ethernet on Ports 1,3,5,10 */
+		pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL   */
+			 <RZA1_PINMUX(3, 0, 2)>,  /* P3_0 = ET_TXCLK  */
+			 <RZA1_PINMUX(3, 3, 2)>,  /* P3_3 = ET_MDIO   */
+			 <RZA1_PINMUX(3, 4, 2)>,  /* P3_4 = ET_RXCLK  */
+			 <RZA1_PINMUX(3, 5, 2)>,  /* P3_5 = ET_RXER   */
+			 <RZA1_PINMUX(3, 6, 2)>,  /* P3_6 = ET_RXDV   */
+			 <RZA1_PINMUX(5, 9, 2)>,  /* P5_9 = ET_MDC    */
+			 <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER  */
+			 <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN  */
+			 <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS   */
+			 <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0  */
+			 <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1  */
+			 <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2  */
+			 <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3  */
+			 <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0  */
+			 <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1  */
+			 <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
+			 <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
+	};
+};
+
+&extal_clk {
+	clock-frequency = <13333000>;
+};
+
+&usb_x1_clk {
+	clock-frequency = <48000000>;
+};
+
+&mtu2 {
+	status = "okay";
+};
+
+&ostm0 {
+	status = "okay";
+};
+
+&ostm1 {
+	status = "okay";
+};
+
+&scif2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&scif2_pins>;
+
+	status = "okay";
+};
+
+&ether {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ether_pins>;
+
+	status = "okay";
+
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+
+		reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <5>;
+	};
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.rza1 b/arch/arm/mach-rmobile/Kconfig.rza1
index efb703b92b..8cf033fb13 100644
--- a/arch/arm/mach-rmobile/Kconfig.rza1
+++ b/arch/arm/mach-rmobile/Kconfig.rza1
@@ -13,9 +13,16 @@ config CPU_RZA1
 choice
 	prompt "Renesas RZ/A1 board select"
 
+# Renesas Supported Boards
+config TARGET_GRPEACH
+	bool "GR-PEACH board"
+
 endchoice
 
 config SYS_SOC
 	default "rmobile"
 
+# Renesas Supported Boards
+source "board/renesas/grpeach/Kconfig"
+
 endif
diff --git a/board/renesas/grpeach/Kconfig b/board/renesas/grpeach/Kconfig
new file mode 100644
index 0000000000..00dc496b86
--- /dev/null
+++ b/board/renesas/grpeach/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GRPEACH
+
+config SYS_BOARD
+	default "grpeach"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "grpeach"
+
+endif
diff --git a/board/renesas/grpeach/MAINTAINERS b/board/renesas/grpeach/MAINTAINERS
new file mode 100644
index 0000000000..4ab7773b0a
--- /dev/null
+++ b/board/renesas/grpeach/MAINTAINERS
@@ -0,0 +1,6 @@
+GRPEACH BOARD
+M:	Marek Vasut <marek.vasut@gmail.com>
+S:	Maintained
+F:	board/renesas/grpeach/
+F:	include/configs/grpeach.h
+F:	configs/grpeach_defconfig
diff --git a/board/renesas/grpeach/Makefile b/board/renesas/grpeach/Makefile
new file mode 100644
index 0000000000..48e185ce3e
--- /dev/null
+++ b/board/renesas/grpeach/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2017 Renesas Electronics
+# Copyright (C) 2017 Chris Brandt
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	:= grpeach.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c
new file mode 100644
index 0000000000..4f901eea71
--- /dev/null
+++ b/board/renesas/grpeach/grpeach.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Renesas Electronics
+ * Copyright (C) Chris Brandt
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+#define RZA1_WDT_BASE	0xfcfe0000
+#define WTCSR		0x00
+#define WTCNT		0x02
+#define WRCSR		0x04
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	/* Dummy read (must read WRCSR:WOVF at least once before clearing) */
+	readb(RZA1_WDT_BASE + WRCSR);
+
+	writew(0xa500, RZA1_WDT_BASE + WRCSR);
+	writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
+	writew(0x5a00, RZA1_WDT_BASE + WTCNT);
+	writew(0xa578, RZA1_WDT_BASE + WTCSR);
+
+	for (;;)
+		asm volatile("wfi");
+}
diff --git a/board/renesas/grpeach/lowlevel_init.S b/board/renesas/grpeach/lowlevel_init.S
new file mode 100644
index 0000000000..9a66dfa6c6
--- /dev/null
+++ b/board/renesas/grpeach/lowlevel_init.S
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Renesas Electronics
+ * Copyright (C) 2017 Chris Brandt
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+
+/* Watchdog Registers */
+#define RZA1_WDT_BASE	0xFCFE0000
+#define WTCSR	(RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */
+#define WTCNT	(RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */
+#define WRCSR	(RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */
+
+/* Standby controller registers (chapter 55) */
+#define RZA1_STBCR_BASE	0xFCFE0020
+#define STBCR1	(RZA1_STBCR_BASE + 0x00)
+#define STBCR2	(RZA1_STBCR_BASE + 0x04)
+#define STBCR3	(RZA1_STBCR_BASE + 0x400)
+#define STBCR4	(RZA1_STBCR_BASE + 0x404)
+#define STBCR5	(RZA1_STBCR_BASE + 0x408)
+#define STBCR6	(RZA1_STBCR_BASE + 0x40c)
+#define STBCR7	(RZA1_STBCR_BASE + 0x410)
+#define STBCR8	(RZA1_STBCR_BASE + 0x414)
+#define STBCR9	(RZA1_STBCR_BASE + 0x418)
+#define STBCR10	(RZA1_STBCR_BASE + 0x41c)
+#define STBCR11	(RZA1_STBCR_BASE + 0x420)
+#define STBCR12	(RZA1_STBCR_BASE + 0x424)
+#define STBCR13	(RZA1_STBCR_BASE + 0x450)
+
+/* Clock Registers */
+#define RZA1_FRQCR_BASE	0xFCFE0010
+#define FRQCR	(RZA1_FRQCR_BASE + 0x00)
+#define FRQCR2	(RZA1_FRQCR_BASE + 0x04)
+
+#define SYSCR1	0xFCFE0400 /* System control register 1 */
+#define SYSCR2	0xFCFE0404 /* System control register 2 */
+#define SYSCR3	0xFCFE0408 /* System control register 3 */
+
+/* Disable WDT */
+#define WTCSR_D		0xA518
+#define WTCNT_D		0x5A00
+
+/* Enable all peripheral clocks */
+#define STBCR3_D	0x00000000
+#define STBCR4_D	0x00000000
+#define STBCR5_D	0x00000000
+#define STBCR6_D	0x00000000
+#define STBCR7_D	0x00000024
+#define STBCR8_D	0x00000005
+#define STBCR9_D	0x00000000
+#define STBCR10_D	0x00000000
+#define STBCR11_D	0x000000c0
+#define STBCR12_D	0x000000f0
+
+/*
+ * Set all system clocks to full speed.
+ * On reset, the CPU will be running at 1/2 speed.
+ * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges
+ */
+#define FRQCR_D		0x0035
+#define FRQCR2_D	0x0001
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	/* PL310 init */
+	write32 0x3fffff80, 0x00000001
+
+	/* Disable WDT */
+	write16	WTCSR, WTCSR_D
+	write16	WTCNT, WTCNT_D
+
+	/* Set clocks */
+	write16	FRQCR, FRQCR_D
+	write16	FRQCR2, FRQCR2_D
+
+	/* Enable all peripherals(Standby Control) */
+	write8 STBCR3, STBCR3_D
+	write8 STBCR4, STBCR4_D
+	write8 STBCR5, STBCR5_D
+	write8 STBCR6, STBCR6_D
+	write8 STBCR7, STBCR7_D
+	write8 STBCR8, STBCR8_D
+	write8 STBCR9, STBCR9_D
+	write8 STBCR10, STBCR10_D
+	write8 STBCR11, STBCR11_D
+	write8 STBCR12, STBCR12_D
+
+	/* For serial booting, enable read ahead caching to speed things up */
+#define DRCR_0  0x3FEFA00C
+	write32 DRCR_0, 0x00010100	/* Read Burst ON, Length=2 */
+
+	/* Enable all internal RAM */
+	write8 SYSCR1, 0xFF
+	write8 SYSCR2, 0xFF
+	write8 SYSCR3, 0xFF
+
+	nop
+	/* back to arch calling code */
+	mov	pc, lr
+
+	.align 4
diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig
new file mode 100644
index 0000000000..32254b3b0e
--- /dev/null
+++ b/configs/grpeach_defconfig
@@ -0,0 +1,53 @@
+CONFIG_ARM=y
+# CONFIG_SPL_SYS_THUMB_BUILD is not set
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_TEXT_BASE=0x18000000
+CONFIG_RZA1=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=50000000
+CONFIG_USE_ENV_SPI_MODE=y
+CONFIG_ENV_SPI_MODE=0x0
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_DM_GPIO=y
+CONFIG_RZA1_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
+CONFIG_SH_ETHER=y
+CONFIG_PINCTRL=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
+CONFIG_TIMER=y
+CONFIG_RENESAS_OSTM_TIMER=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
new file mode 100644
index 0000000000..01704d84c2
--- /dev/null
+++ b/include/configs/grpeach.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the Renesas GRPEACH board
+ *
+ * Copyright (C) 2017-2019 Renesas Electronics
+ */
+
+#ifndef __GRPEACH_H
+#define __GRPEACH_H
+
+/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
+#define CONFIG_SYS_CLK_FREQ	66666666
+
+/* Serial Console */
+#define CONFIG_BAUDRATE		115200
+
+/* Miscellaneous */
+#define CONFIG_SYS_PBSIZE	256
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_ARCH_CPU_INIT
+
+/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		(10 * 1024 * 1024)
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+
+#define CONFIG_ENV_OVERWRITE		1
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_SIZE			(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET		0xc0000
+
+/* Malloc */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+/* Kernel Boot */
+#define CONFIG_BOOTARGS			"ignore_loglevel"
+
+/* Network interface */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+#endif	/* __GRPEACH_H */