diff options
| author | Pratyush Yadav <p.yadav@ti.com> | 2023-04-28 16:50:09 +0530 |
|---|---|---|
| committer | Udit Kumar <u-kumar1@ti.com> | 2023-05-22 22:07:17 +0530 |
| commit | 9a62668f7eb36e12e89a99653d265e93e7ef37d1 (patch) | |
| tree | 27e0246cb2cbd46ccbfd6cbc6c165f1327f80ff3 | |
| parent | 85e73333bfc2402693234d8597536930715291e1 (diff) | |
spi: cadence-qspi: Add device tree property to specify PHY support
If the device supports PHY tuning, we don't need to run
spi_calibration(). The PHY tuning algorithm will take care of that.
We pull the read delay for non-PHY reads in that case from the device
tree since those two are not always the same.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
| -rw-r--r-- | drivers/spi/cadence_qspi.c | 2 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index f931e4cf3e2..456f23facad 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -205,6 +205,7 @@ static int cadence_spi_probe(struct udevice *bus) priv->fifo_width = plat->fifo_width; priv->trigger_address = plat->trigger_address; priv->read_delay = plat->read_delay; + priv->has_phy = plat->has_phy; priv->ahbsize = plat->ahbsize; priv->max_hz = plat->max_hz; @@ -432,6 +433,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) */ plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay", -1); + plat->has_phy = ofnode_read_bool(subnode, "cdns,phy-mode"); debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 1c59d1a9d9a..01611ae10d0 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -208,6 +208,7 @@ struct cadence_spi_plat { fdt_addr_t ahbsize; bool use_dac_mode; int read_delay; + bool has_phy; /* Flash parameters */ u32 page_size; @@ -239,6 +240,7 @@ struct cadence_spi_priv { unsigned int previous_hz; u32 wr_delay; int read_delay; + bool has_phy; struct reset_ctl_bulk *resets; u32 page_size; |