Convert CONFIG_SYS_SRIO et al to Kconfig

This converts the following to Kconfig:
   CONFIG_SRIO1
   CONFIG_SRIO2
   CONFIG_SRIO_PCIE_BOOT_MASTER
   CONFIG_SYS_SRIO

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

20 files changed, 61 insertions, 29 deletions

diff --git a/README b/README
index b095937121..bb35a895b7 100644
--- a/README
+++ b/README
@@ -1686,18 +1686,6 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_OR_TIMING_SDRAM:
 		SDRAM timing
 
-- CONFIG_SYS_SRIO:
-		Chip has SRIO or not
-
-- CONFIG_SRIO1:
-		Board has SRIO 1 port available
-
-- CONFIG_SRIO2:
-		Board has SRIO 2 port available
-
-- CONFIG_SRIO_PCIE_BOOT_MASTER
-		Board can support master function for Boot from SRIO and PCIE
-
 - CONFIG_SYS_SRIOn_MEM_VIRT:
 		Virtual Address of SRIO port 'n' memory region
 
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index c355a95453..cf93a7b1da 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -44,6 +44,21 @@ config SYS_INIT_RAM_LOCK
 	bool "Lock some portion of L1 for initial ram stack"
 	depends on MPC83xx || MPC85xx
 
+config SYS_SRIO
+	bool "Serial RapidIO support"
+
+config SRIO1
+	bool "Board has SRIO 1 port available"
+	depends on SYS_SRIO
+
+config SRIO2
+	bool "Board has SRIO 2 port available"
+	depends on SYS_SRIO
+
+config SRIO_PCIE_BOOT_MASTER
+	bool "Board can support master function for Boot from SRIO and PCIE"
+	depends on SYS_SRIO
+
 source "arch/powerpc/cpu/mpc83xx/Kconfig"
 source "arch/powerpc/cpu/mpc85xx/Kconfig"
 source "arch/powerpc/cpu/mpc8xx/Kconfig"
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index 85b055a93f..86a67d7b21 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
 CONFIG_ENV_ADDR=0xFFF60000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 0d21b893d8..2ac4f26685 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
 CONFIG_ENV_ADDR=0xFFF60000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index b01919ec67..faabd7bc04 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
 CONFIG_ENV_ADDR=0xFFF60000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 0eec508933..3d24b1a78c 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -6,6 +6,10 @@ CONFIG_ENV_OFFSET=0xE0000
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index f9f4c31ddb..cec55a1412 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -6,6 +6,10 @@ CONFIG_ENV_OFFSET=0xCF400
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 6a97437008..5fcf154642 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -7,6 +7,10 @@ CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 1725a8a5a9..ce198e28cb 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -7,6 +7,10 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index dd7473ef7f..637842cda2 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -11,6 +11,10 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 364aab5847..35ab9931e7 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -12,6 +12,10 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index c6710a0413..93b02a5e99 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -4,6 +4,10 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index a705542eea..7d25bbbb0b 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -14,6 +14,10 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index d6d6ec0fbf..2846f63d47 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -5,6 +5,10 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_ADDR=0xFFE20000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 802213de2b..a7dc88c0bf 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -6,6 +6,10 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 6a51149a94..eb75f8b37d 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -13,9 +13,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
 #ifndef __ASSEMBLY__
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index d7e06d23ec..be8d09f6dd 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -32,11 +32,6 @@
 
 #define CFG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-#define CONFIG_SRIO2			/* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-
 #ifndef __ASSEMBLY__
 #include <linux/stringify.h>
 #endif
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 616387f487..f9f9318448 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -49,8 +49,6 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-/* PCIe Boot - Master */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 8f56de40ce..acaad1bfc8 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -14,11 +14,6 @@
 #include <linux/stringify.h>
 
 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
-#define CONFIG_SRIO1		/* SRIO port 1 */
-#define CONFIG_SRIO2		/* SRIO port 2 */
-#endif
 
 /* High Level Configuration Options */
 
@@ -52,7 +47,6 @@
 
 #endif /* CONFIG_RAMBOOT_PBL */
 
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index e9db4a224f..7315afa39f 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -47,7 +47,6 @@
 
 #endif /* CONFIG_RAMBOOT_PBL */
 
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)