diff options
| author | Bhavya Kapoor <b-kapoor@ti.com> | 2024-01-08 11:26:48 +0530 |
|---|---|---|
| committer | Francesco Dolcini <francesco.dolcini@toradex.com> | 2024-03-21 14:26:33 +0000 |
| commit | 8b865a8575fcdacd8d62af1537fba70763011330 (patch) | |
| tree | 3d39ef0766ddace0d49a212193ce6fe030ca4cd4 | |
| parent | 472d8561da0cec7cc2e9ba2baacccaf28c88abf0 (diff) | |
arm: dts: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode
DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay
Value is not present in the device tree. Thus, add Itap Delay Value
for MMCSD Ultra High Speed DDR which is DDR50 speed mode for J721s2 SoC
according to datasheet for J721s2 [1].
[1] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in
J721s2 datasheet
- https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
| -rw-r--r-- | arch/arm/dts/k3-j721s2-main.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi index da633856468..c3ee187ff83 100644 --- a/arch/arm/dts/k3-j721s2-main.dtsi +++ b/arch/arm/dts/k3-j721s2-main.dtsi @@ -392,6 +392,7 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; |