diff options
author | Madalin Bucur <madalin.bucur@oss.nxp.com> | 2020-11-04 15:09:17 +0200 |
---|---|---|
committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-12-10 13:56:39 +0530 |
commit | 848a2efd142ab6d879b1afed0cdbfada30522fa7 (patch) | |
tree | 32ef8b42f1aed1b1ff610cea82df8d7a497bd824 | |
parent | ccedd4ff8e359acfbf1877af14937a9e5045b25f (diff) |
board: freescale: powerpc: add support for all RGMII modes
Make sure all RGMII internal delay modes are covered.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
-rw-r--r-- | board/freescale/corenet_ds/eth_hydra.c | 6 | ||||
-rw-r--r-- | board/freescale/corenet_ds/eth_p4080.c | 6 | ||||
-rw-r--r-- | board/freescale/corenet_ds/eth_superhydra.c | 12 | ||||
-rw-r--r-- | board/freescale/p2041rdb/eth.c | 29 | ||||
-rw-r--r-- | board/freescale/t102xrdb/eth_t102xrdb.c | 3 | ||||
-rw-r--r-- | board/freescale/t104xrdb/eth.c | 3 | ||||
-rw-r--r-- | board/freescale/t208xqds/eth_t208xqds.c | 3 | ||||
-rw-r--r-- | board/freescale/t208xrdb/eth_t208xrdb.c | 3 |
8 files changed, 55 insertions, 10 deletions
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 8112c12568d..6500c2fcf67 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -350,6 +350,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "emi1_rgmii"); break; default: @@ -449,6 +452,9 @@ int board_eth_init(struct bd_info *bis) miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * If DTSEC4 is RGMII, then it's routed via via EC1 to * the first on-board RGMII port. If DTSEC5 is RGMII, diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 650013bb6fc..df5a69bcba3 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -367,6 +367,9 @@ int board_eth_init(struct bd_info *bis) }; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fm_info_set_phy_address(i, 0); mdio_mux[i] = EMI1_RGMII; fm_info_set_mdio(i, @@ -434,6 +437,9 @@ int board_eth_init(struct bd_info *bis) }; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fm_info_set_phy_address(i, 0); mdio_mux[i] = EMI1_RGMII; fm_info_set_mdio(i, diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c index 35daa1e80f3..de7b692f3fe 100644 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -317,6 +317,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "hydra_rg"); debug("Enabled MDIO node hydra_rg\n"); break; @@ -353,6 +356,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "hydra_rg"); debug("Enabled MDIO node hydra_rg\n"); break; @@ -557,6 +563,9 @@ int board_eth_init(struct bd_info *bis) miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the @@ -704,6 +713,9 @@ int board_eth_init(struct bd_info *bis) break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 396981605d2..23fd619ceed 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -81,17 +81,21 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, { phy_interface_t intf = fm_info_get_enet_if(port); char phy[16]; + int lane; + u8 slot; + switch (intf) { /* The RGMII PHY is identified by the MAC connected to it */ - if (intf == PHY_INTERFACE_MODE_RGMII) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); fdt_set_phy_handle(fdt, compat, addr, phy); - } - + break; /* The SGMII PHY is identified by the MAC connected to it */ - if (intf == PHY_INTERFACE_MODE_SGMII) { - int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); - u8 slot; + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); if (lane < 0) return; slot = lane_to_slot[lane]; @@ -106,16 +110,18 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + (port - FM1_DTSEC1)); fdt_set_phy_handle(fdt, compat, addr, phy); } - } - - if (intf == PHY_INTERFACE_MODE_XGMII) { + break; + case PHY_INTERFACE_MODE_XGMII: /* XAUI */ - int lane = serdes_get_first_lane(XAUI_FM1); + lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { /* The XAUI PHY is identified by the slot */ sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); fdt_set_phy_handle(fdt, compat, addr, phy); } + break; + default: + break; } } #endif /* #ifdef CONFIG_FMAN_ENET */ @@ -169,6 +175,9 @@ int board_eth_init(struct bd_info *bis) fm_info_set_phy_address(i, riser_phy_addr[i]); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ fm_info_set_phy_address(i, i == FM1_DTSEC5 ? CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index b64590f9d79..56e6109288f 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -89,6 +89,9 @@ int board_eth_init(struct bd_info *bis) interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 8e2f0358740..b034f11d68a 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -77,6 +77,9 @@ int board_eth_init(struct bd_info *bis) break; #endif case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: if (FM1_DTSEC4 == i) phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; if (FM1_DTSEC5 == i) diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 5044b5695b6..aaa3490aaa2 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -765,6 +765,9 @@ int board_eth_init(struct bd_info *bis) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4 || FM1_DTSEC10) diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c index c16538850cd..e77f3f7146f 100644 --- a/board/freescale/t208xrdb/eth_t208xrdb.c +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -76,6 +76,9 @@ int board_eth_init(struct bd_info *bis) interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; |