diff options
| author | Aswath Govindraju <a-govindraju@ti.com> | 2023-05-16 16:23:40 +0530 |
|---|---|---|
| committer | Udit Kumar <u-kumar1@ti.com> | 2023-05-17 11:52:17 +0530 |
| commit | 67d8d2de4f054fbdce1edcb983f0683da8e28f2b (patch) | |
| tree | bd5561e98e05445c34f047690a2b9b0a44dc5a02 | |
| parent | 62c04970e29fca9188f6c23f514bf42d93f7aebd (diff) | |
arm: dts: k3-j721s2-main: Add PCIe device tree node
Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j721s2.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
| -rw-r--r-- | arch/arm/dts/k3-j721s2-main.dtsi | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi index 5af3162045e..8d04968661c 100644 --- a/arch/arm/dts/k3-j721s2-main.dtsi +++ b/arch/arm/dts/k3-j721s2-main.dtsi @@ -784,6 +784,49 @@ }; }; + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 41>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb013>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + status = "disabled"; /* Needs gpio and serdes info */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, |