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authorSimon Glass <sjg@chromium.org>2015-01-14 21:37:04 -0700
committerSimon Glass <sjg@chromium.org>2015-01-23 17:24:54 -0700
commit4a2708a097eacd7aa3d10ccf26a70a467fa69217 (patch)
treec2e07f6db9d83dbb45d2054343eff5172c34ae8f
parent07570e709765e93f2b1e9506cfd8fa24455636b5 (diff)
x86: Access the VGA ROM when needed
Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
-rw-r--r--drivers/pci/pci_auto.c28
-rw-r--r--drivers/pci/pci_rom.c7
-rw-r--r--include/pci.h9
3 files changed, 42 insertions, 2 deletions
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 44470fa812..ed92857406 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -11,7 +11,7 @@
*/
#include <common.h>
-
+#include <errno.h>
#include <pci.h>
#undef DEBUG
@@ -191,6 +191,32 @@ void pciauto_setup_device(struct pci_controller *hose,
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}
+int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev)
+{
+ pci_addr_t bar_value;
+ pci_size_t bar_size;
+ u32 bar_response;
+ u16 cmdstat = 0;
+
+ pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 0xfffffffe);
+ pci_hose_read_config_dword(hose, dev, PCI_ROM_ADDRESS, &bar_response);
+ if (!bar_response)
+ return -ENOENT;
+
+ bar_size = -(bar_response & ~1);
+ DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size);
+ if (pciauto_region_allocate(hose->pci_mem, bar_size, &bar_value) == 0) {
+ pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS,
+ bar_value);
+ }
+ DEBUGF("\n");
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
+ cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
+
+ return 0;
+}
+
void pciauto_prescan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus)
{
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index a16e99f1da..eb7659177b 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -81,7 +81,12 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
#ifdef CONFIG_X86_OPTION_ROM_ADDR
rom_address = CONFIG_X86_OPTION_ROM_ADDR;
#else
- pci_write_config_dword(dev, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
+
+ if (pciauto_setup_rom(pci_bus_to_hose(PCI_BUS(dev)), dev)) {
+ debug("Cannot find option ROM\n");
+ return -ENOENT;
+ }
+
pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address);
if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
debug("%s: rom_address=%x\n", __func__, rom_address);
diff --git a/include/pci.h b/include/pci.h
index 7f67ca6542..4fbb8f6729 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -697,5 +697,14 @@ void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
* */
u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
+/**
+ * pciauto_setup_rom() - Set up access to a device ROM
+ *
+ * @hose: PCI hose to use
+ * @dev: PCI device to adjust
+ * @return 0 if done, -ve on error
+ */
+int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev);
+
#endif /* __ASSEMBLY__ */
#endif /* _PCI_H */