rockchip: pinctrl: rk3399: add support for I2C[123467]

This adds support for the (to date unsupported) I2C controllers 1~4
and 6~7 (i.e. now all controllers except I2C5, which is not accessible
on the RK3399-Q7, are supported by pinctrl).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

2 files changed, 85 insertions, 6 deletions

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index fbcec932b48..91e8d2d216f 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -324,13 +324,29 @@ struct rk3399_pmusgrf_regs {
 check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
 
 enum {
+	/* GRF_GPIO2A_IOMUX */
+	GRF_GPIO2A0_SEL_SHIFT   = 0,
+	GRF_GPIO2A0_SEL_MASK    = 3 << GRF_GPIO2A0_SEL_SHIFT,
+	GRF_I2C2_SDA            = 2,
+	GRF_GPIO2A1_SEL_SHIFT   = 2,
+	GRF_GPIO2A1_SEL_MASK    = 3 << GRF_GPIO2A1_SEL_SHIFT,
+	GRF_I2C2_SCL            = 2,
+	GRF_GPIO2A7_SEL_SHIFT   = 14,
+	GRF_GPIO2A7_SEL_MASK    = 3 << GRF_GPIO2A7_SEL_SHIFT,
+	GRF_I2C7_SDA            = 2,
+
 	/* GRF_GPIO2B_IOMUX */
+	GRF_GPIO2B0_SEL_SHIFT   = 0,
+	GRF_GPIO2B0_SEL_MASK    = 3 << GRF_GPIO2B0_SEL_SHIFT,
+	GRF_I2C7_SCL            = 2,
 	GRF_GPIO2B1_SEL_SHIFT	= 2,
 	GRF_GPIO2B1_SEL_MASK	= 3 << GRF_GPIO2B1_SEL_SHIFT,
 	GRF_SPI2TPM_RXD		= 1,
+	GRF_I2C6_SDA            = 2,
 	GRF_GPIO2B2_SEL_SHIFT	= 4,
 	GRF_GPIO2B2_SEL_MASK	= 3 << GRF_GPIO2B2_SEL_SHIFT,
 	GRF_SPI2TPM_TXD		= 1,
+	GRF_I2C6_SCL            = 2,
 	GRF_GPIO2B3_SEL_SHIFT	= 6,
 	GRF_GPIO2B3_SEL_MASK	= 3 << GRF_GPIO2B3_SEL_SHIFT,
 	GRF_SPI2TPM_CLK		= 1,
@@ -414,6 +430,14 @@ enum {
 	GRF_GPIO3C1_SEL_MASK	= 3 << GRF_GPIO3C1_SEL_SHIFT,
 	GRF_MAC_TXCLK           = 1,
 
+	/* GRF_GPIO4A_IOMUX */
+	GRF_GPIO4A1_SEL_SHIFT   = 2,
+	GRF_GPIO4A1_SEL_MASK    = 3 << GRF_GPIO4A1_SEL_SHIFT,
+	GRF_I2C1_SDA            = 1,
+	GRF_GPIO4A2_SEL_SHIFT   = 4,
+	GRF_GPIO4A2_SEL_MASK    = 3 << GRF_GPIO4A2_SEL_SHIFT,
+	GRF_I2C1_SCL            = 1,
+
 	/* GRF_GPIO4B_IOMUX */
 	GRF_GPIO4B0_SEL_SHIFT	= 0,
 	GRF_GPIO4B0_SEL_MASK	= 3 << GRF_GPIO4B0_SEL_SHIFT,
@@ -575,6 +599,12 @@ enum {
 	PMUGRF_GPIO1B2_SEL_SHIFT        = 4,
 	PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
 	PMUGRF_SPI1EC_CSN0      = 2,
+	PMUGRF_GPIO1B3_SEL_SHIFT	= 6,
+	PMUGRF_GPIO1B3_SEL_MASK	= 3 << PMUGRF_GPIO1B3_SEL_SHIFT,
+	PMUGRF_I2C4_SDA         = 1,
+	PMUGRF_GPIO1B4_SEL_SHIFT        = 8,
+	PMUGRF_GPIO1B4_SEL_MASK	= 3 << PMUGRF_GPIO1B4_SEL_SHIFT,
+	PMUGRF_I2C4_SCL	        = 1,
 	PMUGRF_GPIO1B6_SEL_SHIFT        = 12,
 	PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
 	PMUGRF_PWM_3B           = 1,
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index 19a74155220..c7052257aa4 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -70,6 +70,60 @@ static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
 			     PMUGRF_GPIO1C0_SEL_MASK,
 			     PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
 		break;
+
+	case PERIPH_ID_I2C1:
+		rk_clrsetreg(&grf->gpio4a_iomux,
+			     GRF_GPIO4A1_SEL_MASK,
+			     GRF_I2C1_SDA << GRF_GPIO4A1_SEL_SHIFT);
+		rk_clrsetreg(&grf->gpio4a_iomux,
+			     GRF_GPIO4A2_SEL_MASK,
+			     GRF_I2C1_SCL << GRF_GPIO4A2_SEL_SHIFT);
+		break;
+
+	case PERIPH_ID_I2C2:
+		rk_clrsetreg(&grf->gpio2a_iomux,
+			     GRF_GPIO2A0_SEL_MASK,
+			     GRF_I2C2_SDA << GRF_GPIO2A0_SEL_SHIFT);
+		rk_clrsetreg(&grf->gpio2a_iomux,
+			     GRF_GPIO2A1_SEL_MASK,
+			     GRF_I2C2_SCL << GRF_GPIO2A1_SEL_SHIFT);
+		break;
+	case PERIPH_ID_I2C3:
+		rk_clrsetreg(&grf->gpio4c_iomux,
+			     GRF_GPIO4C0_SEL_MASK,
+			     GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT);
+		rk_clrsetreg(&grf->gpio4c_iomux,
+			     GRF_GPIO4C1_SEL_MASK,
+			     GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT);
+		break;
+
+	case PERIPH_ID_I2C4:
+		rk_clrsetreg(&pmugrf->gpio1b_iomux,
+			     PMUGRF_GPIO1B3_SEL_MASK,
+			     PMUGRF_I2C4_SDA << PMUGRF_GPIO1B3_SEL_SHIFT);
+		rk_clrsetreg(&pmugrf->gpio1b_iomux,
+			     PMUGRF_GPIO1B4_SEL_MASK,
+			     PMUGRF_I2C4_SCL << PMUGRF_GPIO1B4_SEL_SHIFT);
+		break;
+
+	case PERIPH_ID_I2C7:
+		rk_clrsetreg(&grf->gpio2a_iomux,
+			     GRF_GPIO2A7_SEL_MASK,
+			     GRF_I2C7_SDA << GRF_GPIO2A7_SEL_SHIFT);
+		rk_clrsetreg(&grf->gpio2b_iomux,
+			     GRF_GPIO2B0_SEL_MASK,
+			     GRF_I2C7_SCL << GRF_GPIO2B0_SEL_SHIFT);
+		break;
+
+	case PERIPH_ID_I2C6:
+		rk_clrsetreg(&grf->gpio2b_iomux,
+			     GRF_GPIO2B1_SEL_MASK,
+			     GRF_I2C6_SDA << GRF_GPIO2B1_SEL_SHIFT);
+		rk_clrsetreg(&grf->gpio2b_iomux,
+			     GRF_GPIO2B2_SEL_MASK,
+			     GRF_I2C6_SDA << GRF_GPIO2B2_SEL_SHIFT);
+		break;
+
 	case PERIPH_ID_I2C8:
 		rk_clrsetreg(&pmugrf->gpio1c_iomux,
 			     PMUGRF_GPIO1C4_SEL_MASK,
@@ -78,13 +132,8 @@ static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
 			     PMUGRF_GPIO1C5_SEL_MASK,
 			     PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT);
 		break;
-	case PERIPH_ID_I2C1:
-	case PERIPH_ID_I2C2:
-	case PERIPH_ID_I2C3:
-	case PERIPH_ID_I2C4:
+
 	case PERIPH_ID_I2C5:
-	case PERIPH_ID_I2C6:
-	case PERIPH_ID_I2C7:
 	default:
 		debug("i2c id = %d iomux error!\n", i2c_id);
 		break;