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authorJian Li <jian.li@nxp.com>2020-02-27 09:40:10 +0800
committerPeng Fan <peng.fan@nxp.com>2020-07-14 15:23:46 +0800
commit3f63d27c177a84dd97f77fb843ff4e4c6d7d45eb (patch)
treebe1e34e84d79011ff9711c723f3d6706f45a40c1
parent5865d14dde8f60f678e144e432a5e5ad223915d0 (diff)
imx8mp: Disables use of MR4 TUF flag (MR4[7]) bit
In uMCTL2 Databook, for LPDDR4, it is recommended to set this register to 1. This can avoid ddr bandwidth is lower after booting with running for a while. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jian Li <jian.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
-rw-r--r--board/freescale/imx8mp_evk/lpddr4_timing.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
index 75d6b530d25..7658262b37d 100644
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -11,7 +11,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
- { 0x3d400020, 0x323 },
+ { 0x3d400020, 0x1323 },
{ 0x3d400024, 0x1e84800 },
{ 0x3d400064, 0x7a0118 },
{ 0x3d4000d0, 0xc00307a3 },