diff options
author | Tom Rini <trini@konsulko.com> | 2021-04-09 13:10:59 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2021-04-09 13:10:59 -0400 |
commit | 3f2e3c7845df11ca8359a6cc804bfd6eb5ce215b (patch) | |
tree | 423c18c94b1e62122f8988b94668bada1b85340b | |
parent | 92c4eb7ae3e8fe2c2b3c5b37f882b42282a08e84 (diff) | |
parent | 2c2d7d6a72ba4a4f9323f24b8caa3b1e05546d83 (diff) |
Merge tag 'u-boot-stm32-20210409' of https://source.denx.de/u-boot/custodians/u-boot-stm
Add rt-thread art-pi board support based on STM32H750 SoC
Add Engicam i.Core STM32MP1 SoM
Add FIP header support for STM32programmer
Update uart number when no serial device found for STM32MP1
Remove board_check_usb_power function when ADC flag is not set
Update SPL size limitation for STM32MP1
Set soc_type, soc_pkg, soc_rev env variables for STM32MP1
51 files changed, 3085 insertions, 513 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4df1f037e1f..c09ce8f8881 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -456,7 +456,8 @@ dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ stm32f769-disco.dtb \ stm32746g-eval.dtb dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \ - stm32h743i-eval.dtb + stm32h743i-eval.dtb \ + stm32h750i-art-pi.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ @@ -1031,6 +1032,10 @@ dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb dtb-$(CONFIG_STM32MP15x) += \ stm32mp157a-dk1.dtb \ stm32mp157a-avenger96.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2.dtb \ + stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ + stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ + stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \ diff --git a/arch/arm/dts/stm32h7-pinctrl.dtsi b/arch/arm/dts/stm32h7-pinctrl.dtsi new file mode 100644 index 00000000000..aefa32468dc --- /dev/null +++ b/arch/arm/dts/stm32h7-pinctrl.dtsi @@ -0,0 +1,274 @@ +/* + * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +&pinctrl { + + i2c1_pins_a: i2c1-0 { + pins { + pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */ + <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + ethernet_rmii: rmii-0 { + pins { + pinmux = <STM32_PINMUX('G', 11, AF11)>, + <STM32_PINMUX('G', 13, AF11)>, + <STM32_PINMUX('G', 12, AF11)>, + <STM32_PINMUX('C', 4, AF11)>, + <STM32_PINMUX('C', 5, AF11)>, + <STM32_PINMUX('A', 7, AF11)>, + <STM32_PINMUX('C', 1, AF11)>, + <STM32_PINMUX('A', 2, AF11)>, + <STM32_PINMUX('A', 1, AF11)>; + slew-rate = <2>; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ + <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */ + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */ + <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */ + <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */ + <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */ + <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */ + <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */ + <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */ + <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */ + <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */ + <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */ + }; + }; + + spi1_pins: spi1-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 5, AF5)>, + /* SPI1_CLK */ + <STM32_PINMUX('B', 5, AF5)>; + /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('G', 9, AF5)>; + /* SPI1_MISO */ + bias-disable; + }; + }; + + uart4_pins: uart4-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + usart1_pins: usart1-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */ + bias-disable; + }; + }; + + usart2_pins: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart3_pins: usart3-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */ + <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usbotg_hs_pins_a: usbotg-hs-0 { + pins { + pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */ + <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */ + <STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */ + <STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */ + <STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */ + <STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */ + <STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */ + <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */ + <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */ + <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */ + <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */ + <STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; +}; diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi index 54dd406b6ba..84dc7656d1b 100644 --- a/arch/arm/dts/stm32h7-u-boot.dtsi +++ b/arch/arm/dts/stm32h7-u-boot.dtsi @@ -20,6 +20,7 @@ gpio9 = &gpioj; gpio10 = &gpiok; mmc0 = &sdmmc1; + pinctrl0 = &pinctrl; }; soc { @@ -36,30 +37,6 @@ pinctrl-0 = <&fmc_pins>; pinctrl-names = "default"; status = "okay"; - - /* - * Memory configuration from sdram datasheet IS42S32800G-6BLI - * first bank is bank@0 - * second bank is bank@1 - */ - bank1: bank@1 { - st,sdram-control = /bits/ 8 <NO_COL_9 - NO_ROW_12 - MWIDTH_32 - BANKS_4 - CAS_2 - SDCLK_3 - RD_BURST_EN - RD_PIPE_DL_0>; - st,sdram-timing = /bits/ 8 <TMRD_1 - TXSR_1 - TRAS_1 - TRC_6 - TRP_2 - TWR_1 - TRCD_1>; - st,sdram-refcount = <1539>; - }; }; }; }; @@ -136,77 +113,6 @@ compatible = "st,stm32-gpio"; }; -&pinctrl { - fmc_pins: fmc@0 { - pins { - pinmux = <STM32_PINMUX('D', 0, AF12)>, - <STM32_PINMUX('D', 1, AF12)>, - <STM32_PINMUX('D', 8, AF12)>, - <STM32_PINMUX('D', 9, AF12)>, - <STM32_PINMUX('D',10, AF12)>, - <STM32_PINMUX('D',14, AF12)>, - <STM32_PINMUX('D',15, AF12)>, - - <STM32_PINMUX('E', 0, AF12)>, - <STM32_PINMUX('E', 1, AF12)>, - <STM32_PINMUX('E', 7, AF12)>, - <STM32_PINMUX('E', 8, AF12)>, - <STM32_PINMUX('E', 9, AF12)>, - <STM32_PINMUX('E',10, AF12)>, - <STM32_PINMUX('E',11, AF12)>, - <STM32_PINMUX('E',12, AF12)>, - <STM32_PINMUX('E',13, AF12)>, - <STM32_PINMUX('E',14, AF12)>, - <STM32_PINMUX('E',15, AF12)>, - - <STM32_PINMUX('F', 0, AF12)>, - <STM32_PINMUX('F', 1, AF12)>, - <STM32_PINMUX('F', 2, AF12)>, - <STM32_PINMUX('F', 3, AF12)>, - <STM32_PINMUX('F', 4, AF12)>, - <STM32_PINMUX('F', 5, AF12)>, - <STM32_PINMUX('F',11, AF12)>, - <STM32_PINMUX('F',12, AF12)>, - <STM32_PINMUX('F',13, AF12)>, - <STM32_PINMUX('F',14, AF12)>, - <STM32_PINMUX('F',15, AF12)>, - - <STM32_PINMUX('G', 0, AF12)>, - <STM32_PINMUX('G', 1, AF12)>, - <STM32_PINMUX('G', 2, AF12)>, - <STM32_PINMUX('G', 4, AF12)>, - <STM32_PINMUX('G', 5, AF12)>, - <STM32_PINMUX('G', 8, AF12)>, - <STM32_PINMUX('G',15, AF12)>, - - <STM32_PINMUX('H', 5, AF12)>, - <STM32_PINMUX('H', 6, AF12)>, - <STM32_PINMUX('H', 7, AF12)>, - <STM32_PINMUX('H', 8, AF12)>, - <STM32_PINMUX('H', 9, AF12)>, - <STM32_PINMUX('H',10, AF12)>, - <STM32_PINMUX('H',11, AF12)>, - <STM32_PINMUX('H',12, AF12)>, - <STM32_PINMUX('H',13, AF12)>, - <STM32_PINMUX('H',14, AF12)>, - <STM32_PINMUX('H',15, AF12)>, - - <STM32_PINMUX('I', 0, AF12)>, - <STM32_PINMUX('I', 1, AF12)>, - <STM32_PINMUX('I', 2, AF12)>, - <STM32_PINMUX('I', 3, AF12)>, - <STM32_PINMUX('I', 4, AF12)>, - <STM32_PINMUX('I', 5, AF12)>, - <STM32_PINMUX('I', 6, AF12)>, - <STM32_PINMUX('I', 7, AF12)>, - <STM32_PINMUX('I', 9, AF12)>, - <STM32_PINMUX('I',10, AF12)>; - - slew-rate = <3>; - }; - }; -}; - &pwrcfg { u-boot,dm-pre-reloc; }; @@ -222,3 +128,7 @@ &timer5 { u-boot,dm-pre-reloc; }; + +&pinctrl { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi deleted file mode 100644 index 141083f8d12..00000000000 --- a/arch/arm/dts/stm32h743-pinctrl.dtsi +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include <dt-bindings/pinctrl/stm32-pinfunc.h> - -/ { - soc { - pinctrl: pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32h743-pinctrl"; - ranges = <0 0x58020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@58020000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA_CK>; - st,bank-name = "GPIOA"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiob: gpio@58020400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc GPIOB_CK>; - st,bank-name = "GPIOB"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioc: gpio@58020800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc GPIOC_CK>; - st,bank-name = "GPIOC"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiod: gpio@58020c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc GPIOD_CK>; - st,bank-name = "GPIOD"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioe: gpio@58021000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOE_CK>; - st,bank-name = "GPIOE"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiof: gpio@58021400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc GPIOF_CK>; - st,bank-name = "GPIOF"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiog: gpio@58021800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc GPIOG_CK>; - st,bank-name = "GPIOG"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioh: gpio@58021c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc GPIOH_CK>; - st,bank-name = "GPIOH"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioi: gpio@58022000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOI_CK>; - st,bank-name = "GPIOI"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioj: gpio@58022400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc GPIOJ_CK>; - st,bank-name = "GPIOJ"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiok: gpio@58022800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc GPIOK_CK>; - st,bank-name = "GPIOK"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c1_pins_a: i2c1-0 { - pins { - pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */ - <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - ethernet_rmii: rmii-0 { - pins { - pinmux = <STM32_PINMUX('G', 11, AF11)>, - <STM32_PINMUX('G', 13, AF11)>, - <STM32_PINMUX('G', 12, AF11)>, - <STM32_PINMUX('C', 4, AF11)>, - <STM32_PINMUX('C', 5, AF11)>, - <STM32_PINMUX('A', 7, AF11)>, - <STM32_PINMUX('C', 1, AF11)>, - <STM32_PINMUX('A', 2, AF11)>, - <STM32_PINMUX('A', 1, AF11)>; - slew-rate = <2>; - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ - <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */ - <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ - <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - pins2{ - pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ - <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ - <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_dir_pins_a: sdmmc1-dir-0 { - pins1 { - pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - pins2{ - pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { - pins { - pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ - <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */ - }; - }; - - usart1_pins: usart1-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */ - bias-disable; - }; - }; - - usart2_pins: usart2-0 { - pins1 { - pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ - bias-disable; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */ - <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */ - <STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */ - <STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */ - <STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */ - <STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */ - <STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */ - <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */ - <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */ - <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */ - <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */ - <STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index e4e472336b1..ed6857512f7 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -99,6 +99,22 @@ clocks = <&rcc USART2_CK>; }; + usart3: serial@40004800 { + compatible = "st,stm32h7-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + status = "disabled"; + clocks = <&rcc USART3_CK>; + }; + + uart4: serial@40004c00 { + compatible = "st,stm32h7-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + status = "disabled"; + clocks = <&rcc UART4_CK>; + }; + i2c1: i2c@40005400 { compatible = "st,stm32f7-i2c"; #address-cells = <1>; @@ -123,7 +139,7 @@ status = "disabled"; }; - i2c3: i2c@40005C00 { + i2c3: i2c@40005c00 { compatible = "st,stm32f7-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -238,7 +254,7 @@ dmamux1: dma-router@40020800 { compatible = "st,stm32h7-dmamux"; - reg = <0x40020800 0x1c>; + reg = <0x40020800 0x40>; #dma-cells = <3>; dma-channels = <16>; dma-requests = <128>; @@ -332,6 +348,20 @@ max-frequency = <120000000>; }; + sdmmc2: sdmmc@48022400 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x48022400 0x400>; + interrupts = <124>; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC2_CK>; + clock-names = "apb_pclk"; + resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + }; + exti: interrupt-controller@58000000 { compatible = "st,stm32h7-exti"; interrupt-controller; @@ -356,7 +386,7 @@ status = "disabled"; }; - i2c4: i2c@58001C00 { + i2c4: i2c@58001c00 { compatible = "st,stm32f7-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -519,6 +549,148 @@ snps,pbl = <8>; status = "disabled"; }; + + pinctrl: pin-controller@58020000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32h743-pinctrl"; + ranges = <0 0x58020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + pins-are-numbered; + + gpioa: gpio@58020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc GPIOA_CK>; + st,bank-name = "GPIOA"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@58020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc GPIOB_CK>; + st,bank-name = "GPIOB"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@58020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc GPIOC_CK>; + st,bank-name = "GPIOC"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@58020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc GPIOD_CK>; + st,bank-name = "GPIOD"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@58021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc GPIOE_CK>; + st,bank-name = "GPIOE"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@58021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc GPIOF_CK>; + st,bank-name = "GPIOF"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@58021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc GPIOG_CK>; + st,bank-name = "GPIOG"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@58021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc GPIOH_CK>; + st,bank-name = "GPIOH"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@58022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc GPIOI_CK>; + st,bank-name = "GPIOI"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@58022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc GPIOJ_CK>; + st,bank-name = "GPIOJ"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@58022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc GPIOK_CK>; + st,bank-name = "GPIOK"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; + }; }; }; diff --git a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi index 5965afcbe46..02e28c63f28 100644 --- a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi @@ -1,3 +1,101 @@ // SPDX-License-Identifier: GPL-2.0+ #include <stm32h7-u-boot.dtsi> + +&fmc { + + /* + * Memory configuration from sdram datasheet IS42S32800G-6BLI + * first bank is bank@0 + * second bank is bank@1 + */ + bank1: bank@1 { + st,sdram-control = /bits/ 8 <NO_COL_9 + NO_ROW_12 + MWIDTH_32 + BANKS_4 + CAS_2 + SDCLK_3 + RD_BURST_EN + RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_1 + TXSR_1 + TRAS_1 + TRC_6 + TRP_2 + TWR_1 + TRCD_1>; + st,sdram-refcount = <1539>; + }; +}; + +&pinctrl { + fmc_pins: fmc@0 { + pins { + pinmux = <STM32_PINMUX('D', 0, AF12)>, + <STM32_PINMUX('D', 1, AF12)>, + <STM32_PINMUX('D', 8, AF12)>, + <STM32_PINMUX('D', 9, AF12)>, + <STM32_PINMUX('D',10, AF12)>, + <STM32_PINMUX('D',14, AF12)>, + <STM32_PINMUX('D',15, AF12)>, + + <STM32_PINMUX('E', 0, AF12)>, + <STM32_PINMUX('E', 1, AF12)>, + <STM32_PINMUX('E', 7, AF12)>, + <STM32_PINMUX('E', 8, AF12)>, + <STM32_PINMUX('E', 9, AF12)>, + <STM32_PINMUX('E',10, AF12)>, + <STM32_PINMUX('E',11, AF12)>, + <STM32_PINMUX('E',12, AF12)>, + <STM32_PINMUX('E',13, AF12)>, + <STM32_PINMUX('E',14, AF12)>, + <STM32_PINMUX('E',15, AF12)>, + + <STM32_PINMUX('F', 0, AF12)>, + <STM32_PINMUX('F', 1, AF12)>, + <STM32_PINMUX('F', 2, AF12)>, + <STM32_PINMUX('F', 3, AF12)>, + <STM32_PINMUX('F', 4, AF12)>, + <STM32_PINMUX('F', 5, AF12)>, + <STM32_PINMUX('F',11, AF12)>, + <STM32_PINMUX('F',12, AF12)>, + <STM32_PINMUX('F',13, AF12)>, + <STM32_PINMUX('F',14, AF12)>, + <STM32_PINMUX('F',15, AF12)>, + + <STM32_PINMUX('G', 0, AF12)>, + <STM32_PINMUX('G', 1, AF12)>, + <STM32_PINMUX('G', 2, AF12)>, + <STM32_PINMUX('G', 4, AF12)>, + <STM32_PINMUX('G', 5, AF12)>, + <STM32_PINMUX('G', 8, AF12)>, + <STM32_PINMUX('G',15, AF12)>, + + <STM32_PINMUX('H', 5, AF12)>, + <STM32_PINMUX('H', 6, AF12)>, + <STM32_PINMUX('H', 7, AF12)>, + <STM32_PINMUX('H', 8, AF12)>, + <STM32_PINMUX('H', 9, AF12)>, + <STM32_PINMUX('H',10, AF12)>, + <STM32_PINMUX('H',11, AF12)>, + <STM32_PINMUX('H',12, AF12)>, + <STM32_PINMUX('H',13, AF12)>, + <STM32_PINMUX('H',14, AF12)>, + <STM32_PINMUX('H',15, AF12)>, + + <STM32_PINMUX('I', 0, AF12)>, + <STM32_PINMUX('I', 1, AF12)>, + <STM32_PINMUX('I', 2, AF12)>, + <STM32_PINMUX('I', 3, AF12)>, + <STM32_PINMUX('I', 4, AF12)>, + <STM32_PINMUX('I', 5, AF12)>, + <STM32_PINMUX('I', 6, AF12)>, + <STM32_PINMUX('I', 7, AF12)>, + <STM32_PINMUX('I', 9, AF12)>, + <STM32_PINMUX('I',10, AF12)>; + + slew-rate = <3>; + }; + }; +}; diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts index 7927310d8e2..3a01ebd563c 100644 --- a/arch/arm/dts/stm32h743i-disco.dts +++ b/arch/arm/dts/stm32h743i-disco.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "stm32h743.dtsi" -#include "stm32h743-pinctrl.dtsi" +#include "stm32h7-pinctrl.dtsi" / { model = "STMicroelectronics STM32H743i-Discovery board"; diff --git a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi index 5965afcbe46..02e28c63f28 100644 --- a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi @@ -1,3 +1,101 @@ // SPDX-License-Identifier: GPL-2.0+ #include <stm32h7-u-boot.dtsi> + +&fmc { + + /* + * Memory configuration from sdram datasheet IS42S32800G-6BLI + * first bank is bank@0 + * second bank is bank@1 + */ + bank1: bank@1 { + st,sdram-control = /bits/ 8 <NO_COL_9 + NO_ROW_12 + MWIDTH_32 + BANKS_4 + CAS_2 + SDCLK_3 + RD_BURST_EN + RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_1 + TXSR_1 + TRAS_1 + TRC_6 + TRP_2 + TWR_1 + TRCD_1>; + st,sdram-refcount = <1539>; + }; +}; + +&pinctrl { + fmc_pins: fmc@0 { + pins { + pinmux = <STM32_PINMUX('D', 0, AF12)>, + <STM32_PINMUX('D', 1, AF12)>, + <STM32_PINMUX('D', 8, AF12)>, + <STM32_PINMUX('D', 9, AF12)>, + <STM32_PINMUX('D',10, AF12)>, + <STM32_PINMUX('D',14, AF12)>, + <STM32_PINMUX('D',15, AF12)>, + + <STM32_PINMUX('E', 0, AF12)>, + <STM32_PINMUX('E', 1, AF12)>, + <STM32_PINMUX('E', 7, AF12)>, + <STM32_PINMUX('E', 8, AF12)>, + <STM32_PINMUX('E', 9, AF12)>, + <STM32_PINMUX('E',10, AF12)>, + <STM32_PINMUX('E',11, AF12)>, + <STM32_PINMUX('E',12, AF12)>, + <STM32_PINMUX('E',13, AF12)>, + <STM32_PINMUX('E',14, AF12)>, + <STM32_PINMUX('E',15, AF12)>, + + <STM32_PINMUX('F', 0, AF12)>, + <STM32_PINMUX('F', 1, AF12)>, + <STM32_PINMUX('F', 2, AF12)>, + <STM32_PINMUX('F', 3, AF12)>, + <STM32_PINMUX('F', 4, AF12)>, + <STM32_PINMUX('F', 5, AF12)>, + <STM32_PINMUX('F',11, AF12)>, + <STM32_PINMUX('F',12, AF12)>, + <STM32_PINMUX('F',13, AF12)>, + <STM32_PINMUX('F',14, AF12)>, + <STM32_PINMUX('F',15, AF12)>, + + <STM32_PINMUX('G', 0, AF12)>, + <STM32_PINMUX('G', 1, AF12)>, + <STM32_PINMUX('G', 2, AF12)>, + <STM32_PINMUX('G', 4, AF12)>, + <STM32_PINMUX('G', 5, AF12)>, + <STM32_PINMUX('G', 8, AF12)>, + <STM32_PINMUX('G',15, AF12)>, + + <STM32_PINMUX('H', 5, AF12)>, + <STM32_PINMUX('H', 6, AF12)>, + <STM32_PINMUX('H', 7, AF12)>, + <STM32_PINMUX('H', 8, AF12)>, + <STM32_PINMUX('H', 9, AF12)>, + <STM32_PINMUX('H',10, AF12)>, + <STM32_PINMUX('H',11, AF12)>, + <STM32_PINMUX('H',12, AF12)>, + <STM32_PINMUX('H',13, AF12)>, + <STM32_PINMUX('H',14, AF12)>, + <STM32_PINMUX('H',15, AF12)>, + + <STM32_PINMUX('I', 0, AF12)>, + <STM32_PINMUX('I', 1, AF12)>, + <STM32_PINMUX('I', 2, AF12)>, + <STM32_PINMUX('I', 3, AF12)>, + <STM32_PINMUX('I', 4, AF12)>, + <STM32_PINMUX('I', 5, AF12)>, + <STM32_PINMUX('I', 6, AF12)>, + <STM32_PINMUX('I', 7, AF12)>, + <STM32_PINMUX('I', 9, AF12)>, + <STM32_PINMUX('I',10, AF12)>; + + slew-rate = <3>; + }; + }; +}; diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts index 8f398178f5e..38cc7faf688 100644 --- a/arch/arm/dts/stm32h743i-eval.dts +++ b/arch/arm/dts/stm32h743i-eval.dts @@ -42,7 +42,7 @@ /dts-v1/; #include "stm32h743.dtsi" -#include "stm32h743-pinctrl.dtsi" +#include "stm32h7-pinctrl.dtsi" / { model = "STMicroelectronics STM32H743i-EVAL board"; diff --git a/arch/arm/dts/stm32h750.dtsi b/arch/arm/dts/stm32h750.dtsi new file mode 100644 index 00000000000..99533f356b5 --- /dev/null +++ b/arch/arm/dts/stm32h750.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */ + +#include "stm32h743.dtsi" + diff --git a/arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi b/arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi new file mode 100644 index 00000000000..326a5533b78 --- /dev/null +++ b/arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <stm32h7-u-boot.dtsi> + +&fmc { + /* + * Memory configuration from sdram datasheet W9825G6KH + * first bank is bank@0 + * second bank is bank@1 + */ + bank1: bank@0 { + st,sdram-control = /bits/ 8 <NO_COL_9 + NO_ROW_13 + MWIDTH_16 + BANKS_4 + CAS_2 + SDCLK_3 + RD_BURST_EN + RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_2 + TXSR_6 + TRAS_6 + TRC_6 + TRP_2 + TWR_2 + TRCD_2>; + st,sdram-refcount = <677>; + }; +}; + +&pinctrl { + fmc_pins: fmc@0 { + pins { + pinmux = <STM32_PINMUX('D', 0, AF12)>, + <STM32_PINMUX('D', 1, AF12)>, + <STM32_PINMUX('D', 8, AF12)>, + <STM32_PINMUX('D', 9, AF12)>, + <STM32_PINMUX('D',10, AF12)>, + <STM32_PINMUX('D',14, AF12)>, + <STM32_PINMUX('D',15, AF12)>, + + <STM32_PINMUX('E', 0, AF12)>, + <STM32_PINMUX('E', 1, AF12)>, + <STM32_PINMUX('E', 7, AF12)>, + <STM32_PINMUX('E', 8, AF12)>, + <STM32_PINMUX('E', 9, AF12)>, + <STM32_PINMUX('E',10, AF12)>, + <STM32_PINMUX('E',11, AF12)>, + <STM32_PINMUX('E',12, AF12)>, + <STM32_PINMUX('E',13, AF12)>, + <STM32_PINMUX('E',14, AF12)>, + <STM32_PINMUX('E',15, AF12)>, + + <STM32_PINMUX('F', 0, AF12)>, + <STM32_PINMUX('F', 1, AF12)>, + <STM32_PINMUX('F', 2, AF12)>, + <STM32_PINMUX('F', 3, AF12)>, + <STM32_PINMUX('F', 4, AF12)>, + <STM32_PINMUX('F', 5, AF12)>, + <STM32_PINMUX('F',11, AF12)>, + <STM32_PINMUX('F',12, AF12)>, + <STM32_PINMUX('F',13, AF12)>, + <STM32_PINMUX('F',14, AF12)>, + <STM32_PINMUX('F',15, AF12)>, + + <STM32_PINMUX('G', 0, AF12)>, + <STM32_PINMUX('G', 1, AF12)>, + <STM32_PINMUX('G', 2, AF12)>, + <STM32_PINMUX('G', 4, AF12)>, + <STM32_PINMUX('G', 5, AF12)>, + <STM32_PINMUX('G', 8, AF12)>, + <STM32_PINMUX('G',15, AF12)>, + + <STM32_PINMUX('H', 5, AF12)>, + <STM32_PINMUX('C', 2, AF12)>, + <STM32_PINMUX('C', 3, AF12)>; + + slew-rate = <3>; + }; + }; +}; diff --git a/arch/arm/dts/stm32h750i-art-pi.dts b/arch/arm/dts/stm32h750i-art-pi.dts new file mode 100644 index 00000000000..2a4d1cb4965 --- /dev/null +++ b/arch/arm/dts/stm32h750i-art-pi.dts @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com> + * + */ + +/dts-v1/; +#include "stm32h750.dtsi" +#include "stm32h7-pinctrl.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "RT-Thread STM32H750i-ART-PI board"; + compatible = "st,stm32h750i-art-pi", "st,stm32h750"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:2000000n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x2000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + no-map; + size = <0x100000>; + linux,dma-default; + }; + }; + + aliases { + serial0 = &uart4; + serial1 = &usart3; + }; + + leds { + compatible = "gpio-leds"; + led-red { + gpios = <&gpioi 8 0>; + }; + led-green { + gpios = <&gpioc 15 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + +&mac { + status = "disabled"; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + dmas = <&dmamux1 37 0x400 0x05>, + <&dmamux1 38 0x400 0x05>; + dma-names = "rx", "tx"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + + partition@0 { + label = "root filesystem"; + reg = <0 0x1000000>; + }; + }; +}; + +&usart2 { + pinctrl-0 = <&usart2_pins>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins>; + dmas = <&dmamux1 45 0x400 0x05>, + <&dmamux1 46 0x400 0x05>; + dma-names = "rx", "tx"; + st,hw-flow-ctrl; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>; + max-speed = <115200>; + }; +}; + +&uart4 { + pinctrl-0 = <&uart4_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi new file mode 100644 index 00000000000..24c81269b09 --- /dev/null +++ b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved + */ + +/* + * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs + * DDR type: DDR3 / DDR3L + * DDR width: 32bits + * DDR density: 4Gb + * System frequency: 528000Khz + * Relaxed Timing Mode: false + * Address mapping type: RBC + * + * Save Date: 2019.05.14, save Time: 11:25:16 + */ +#define DDR_MEM_COMPATIBLE ddr3-icore-1066-888-bin-g-1x4gb-528mhz +#define DDR_MEM_NAME "DDR3-DDR3L 32bits 528000kHz" +#define DDR_MEM_SPEED 528000 +#define DDR_MEM_SIZE 0x20000000 + +#define DDR_MSTR 0x00040401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0080008A +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041B +#define DDR_DRAMTMG2 0x0607080F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x07040607 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02050105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000C01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x01000001 +#define DDR_PERFLPR1 0x08000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00010000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x02100C03 +#define DDR_PCFGQOS1_0 0x00800100 +#define DDR_PCFGWQOS0_0 0x01100C03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PCFGR_1 0x00010000 +#define DDR_PCFGW_1 0x00000000 +#define DDR_PCFGQOS0_1 0x02100C03 +#define DDR_PCFGQOS1_1 0x00800040 +#define DDR_PCFGWQOS0_1 0x01100C03 +#define DDR_PCFGWQOS1_1 0x01000200 +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x07070707 +#define DDR_ADDRMAP6 0x0F0F0707 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022A41B +#define DDR_PTR1 0x047C0740 +#define DDR_PTR2 0x042D9C80 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200001F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x36D477D0 +#define DDR_DTPR1 0x098A00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000830 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX0DLLCR 0x40000000 +#define DDR_DX0DQTR 0xFFFFFFFF +#define DDR_DX0DQSTR 0x3DB02000 +#define DDR_DX1GCR 0x0000CE81 +#define DDR_DX1DLLCR 0x40000000 +#define DDR_DX1DQTR 0xFFFFFFFF +#define DDR_DX1DQSTR 0x3DB02000 +#define DDR_DX2GCR 0x0000CE81 +#define DDR_DX2DLLCR 0x40000000 +#define DDR_DX2DQTR 0xFFFFFFFF +#define DDR_DX2DQSTR 0x3DB02000 +#define DDR_DX3GCR 0x0000CE81 +#define DDR_DX3DLLCR 0x40000000 +#define DDR_DX3DQTR 0xFFFFFFFF +#define DDR_DX3DQSTR 0x3DB02000 + +#include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi new file mode 100644 index 00000000000..96fe4612351 --- /dev/null +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Amarula Solutions(India) + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +#include "stm32mp157a-icore-stm32mp1-u-boot.dtsi" + +/{ + aliases { + mmc0 = &sdmmc1; + }; + + chosen { + stdout-path = &uart4; + }; +}; + +&sdmmc1 { + u-boot,dm-pre-reloc; +}; + +&sdmmc1_b4_pins_a { + u-boot,dm-pre-reloc; + + pins1 { + u-boot,dm-pre-reloc; + }; + + pins2 { + u-boot,dm-pre-reloc; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_a { + u-boot,dm-pre-reloc; + + pins1 { + u-boot,dm-pre-reloc; + }; + + pins2 { + u-boot,dm-pre-reloc; + bias-pull-up; + }; +}; diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts new file mode 100644 index 00000000000..d3058a036c7 --- /dev/null +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-icore-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Engicam i.Core STM32MP1 C.TOUCH 2.0"; + compatible = "engicam,icore-stm32mp1-ctouch2", + "engicam,icore-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi new file mode 100644 index 00000000000..96fe4612351 --- /dev/null +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Amarula Solutions(India) + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +#include "stm32mp157a-icore-stm32mp1-u-boot.dtsi" + +/{ + aliases { + mmc0 = &sdmmc1; + }; + + chosen { + stdout-path = &uart4; + }; +}; + +&sdmmc1 { + u-boot,dm-pre-reloc; +}; + +&sdmmc1_b4_pins_a { + u-boot,dm-pre-reloc; + + pins1 { + u-boot,dm-pre-reloc; + }; + + pins2 { + u-boot,dm-pre-reloc; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_a { + u-boot,dm-pre-reloc; + + pins1 { + u-boot,dm-pre-reloc; + }; + + pins2 { + u-boot,dm-pre-reloc; + bias-pull-up; + }; +}; diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts new file mode 100644 index 00000000000..ec9f1d1cd50 --- /dev/null +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-icore-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit"; + compatible = "engicam,icore-stm32mp1-edimm2.2", + "engicam,icore-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi new file mode 100644 index 00000000000..d62c24d4ce2 --- /dev/null +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Amarula Solutions(India) + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +#include <dt-bindings/clock/stm32mp1-clksrc.h> +#include "stm32mp15-u-boot.dtsi" +#include "stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi" + +&vddcore { + u-boot,dm-pre-reloc; +}; + +&vdd { + u-boot,dm-pre-reloc; +}; + +&vdd_usb { + u-boot,dm-pre-reloc; +}; + +&vdda { + u-boot,dm-pre-reloc; +}; + +&vdd_ddr { + u-boot,dm-pre-reloc; +}; + +&vtt_ddr { + u-boot,dm-pre-reloc; +}; + +&vref_ddr { + u-boot,dm-pre-reloc; +}; + +&vdd_sd { + u-boot,dm-pre-reloc; +}; + +&v3v3 { + u-boot,dm-pre-reloc; +}; + +&v2v8 { + u-boot,dm-pre-reloc; +}; + +&v1v8 { + u-boot,dm-pre-reloc; +}; + +&rcc { + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; + + st,pkcs = < + CLK_CKPER_HSE + CLK_FMC_ACLK + CLK_QSPI_ACLK + CLK_ETH_DISABLED + CLK_SDMMC12_PLL4P + CLK_DSI_DSIPLL + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_SPI2S1_PLL3Q + CLK_SPI2S23_PLL3Q + CLK_SPI45_HSI + CLK_SPI6_HSI + CLK_I2C46_HSI + CLK_SDMMC3_PLL4P + CLK_USBO_USBPHY + CLK_ADC_CKPER + CLK_CEC_LSE + CLK_I2C12_HSI + CLK_I2C35_HSI + CLK_UART1_HSI + CLK_UART24_HSI + CLK_UART35_HSI + CLK_UART6_HSI + CLK_UART78_HSI + CLK_SPDIF_PLL4P + CLK_FDCAN_PLL4R + CLK_SAI1_PLL3Q + CLK_SAI2_PLL3Q + CLK_SAI3_PLL3Q + CLK_SAI4_PLL3Q + CLK_RNG1_LSI + CLK_RNG2_LSI + CLK_LPTIM1_PCLK1 + CLK_LPTIM23_PCLK3 + CLK_LPTIM45_LSE + >; + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ + pll2: st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = < 2 65 1 0 0 PQR(1,1,1) >; + frac = < 0x1400 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ + pll3: st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = < 1 33 1 16 36 PQR(1,1,1) >; + frac = < 0x1a04 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ + pll4: st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = < 3 98 5 7 7 PQR(1,1,1) >; + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi b/arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi new file mode 100644 index 00000000000..01166ccacf2 --- /dev/null +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/ { + compatible = "engicam,icore-stm32mp1", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + vddcore: regulator-vddcore { + compatible = "regulator-fixed"; + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_usb: regulator-vdd-usb { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdda: regulator-vdda { + compatible = "regulator-fixed"; + regulator-name = "vdda"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_ddr: regulator-vdd-ddr { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vtt_ddr: regulator-vtt-ddr { + compatible = "regulator-fixed"; + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <675000>; + regulator-always-on; + vin-supply = <&vdd>; + }; + + vref_ddr: regulator-vref-ddr { + compatible = "regulator-fixed"; + regulator-name = "vref_ddr"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <675000>; + regulator-always-on; + vin-supply = <&vdd>; + }; + + vdd_sd: regulator-vdd-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2v8: regulator-v2v8 { + compatible = "regulator-fixed"; + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&v3v3>; + }; + + v1v8: regulator-v1v8 { + compatible = "regulator-fixed"; + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&v3v3>; + }; +}; + +&dts { + status = "okay"; +}; + +&i2c2 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + status = "okay"; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2{ + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc{ + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; + +&rtc{ + status = "okay"; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi new file mode 100644 index 00000000000..e4bd2158120 --- /dev/null +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Amarula Solutions(India) + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +#include "stm32mp157a-microgea-stm32mp1-u-boot.dtsi" + +/{ + aliases { + mmc0 = &sdmmc1; + }; + + chosen { + stdout-path = &uart4; + }; +}; + +&sdmmc1 { + u-boot,dm-pre-reloc; +}; + +&sdmmc1_b4_pins_a { + u-boot,dm-pre-reloc; + + pins1 { + u-boot,dm-pre-reloc; + }; + + pins2 { + u-boot,dm-pre-reloc; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_a { + u-boot,dm-pre-reloc; + + pins1 { + u-boot,dm-pre-reloc; + }; + + pins2 { + u-boot,dm-pre-reloc; + bias-pull-up; + }; +}; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts new file mode 100644 index 00000000000..674b2d330dc --- /dev/null +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-microgea-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame"; + compatible = "engicam,microgea-stm32mp1-microdev2.0-of7", + "engicam,microgea-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + serial1 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + default-on; + }; + + lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + power-supply = <&panel_pwr>; + }; + + panel_pwr: regulator-panel-pwr { + compatible = "regulator-fixed"; + regulator-name = "panel_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiob 10 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + panel { + compatible = "auo,b101aw03"; + backlight = <&backlight>; + enable-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>; + power-supply = <&lcd_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + }; +}; + +&i2c2 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + status = "okay"; +}; + +<dc { + pinctrl-names = "default"; + pinctrl-0 = <<dc_pins>; + status = "okay"; + + port { + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pinctrl { + ltdc_pins: ltdc { + pins { + pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */ + <STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */ + <STM32_PINMUX('H', 11, AF14)>, /* LTDC_R5 */ + <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ + <STM32_PINMUX('D', 9, AF14)>, /* LTDC_B0 */ + <STM32_PINMUX('E', 5, AF14)>, /* LTDC_G0 */ + <STM32_PINMUX('E', 6, AF14)>, /* LTDC_G1 */ + <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */ + <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ + <STM32_PINMUX('G', 7, AF14)>, /* LTDC_CLK */ + <STM32_PINMUX('G', 12, AF14)>, /* LTDC_B1 */ + <STM32_PINMUX('H', 2, AF14)>, /* LTDC_R0 */ + <STM32_PINMUX('H', 3, AF14)>, /* LTDC_R1 */ + <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ + <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ + <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ + <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ + <STM32_PINMUX('H', 14, AF14)>, /* LTDC_G3 */ + <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */ + <STM32_PINMUX('I', 0, AF14)>, /* LTDC_G5 */ + <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ + <STM32_PINMUX('I', 2, AF14)>, /* LTDC_G7 */ + <STM32_PINMUX('I', 4, AF14)>, /* LTDC_B4 */ + <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */ + <STM32_PINMUX('B', 8, AF14)>, /* LTDC_B6 */ + <STM32_PINMUX('I', 7, AF14)>, /* LTDC_B7 */ + <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ + <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&vdd>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; + +/* J31: RS323 */ +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi new file mode 100644 index 00000000000..e4bd2158120 --- /dev/null +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Amarula Solutions(India) + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +#include "stm32mp157a-microgea-stm32mp1-u-boot.dtsi" + +/{ + aliases { + mmc0 = &sdmmc1; + }; + + chosen { + stdout-path = &uart4; + }; +}; + +&sdmmc1 { + u-boot,dm-pre-reloc; +}; + +&sdmmc1_b4_pins_a { + u-boot,dm-pre-reloc; + + pins1 { + u-boot,dm-pre-reloc; + }; + + pins2 { + u-boot,dm-pre-reloc; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_a { + u-boot,dm-pre-reloc; + + pins1 { + u-boot,dm-pre-reloc; + }; + + pins2 { + u-boot,dm-pre-reloc; + bias-pull-up; + }; +}; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts new file mode 100644 index 00000000000..7a75868164d --- /dev/null +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-microgea-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board"; + compatible = "engicam,microgea-stm32mp1-microdev2.0", + "engicam,microgea-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + serial1 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&vdd>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; + +/* J31: RS323 */ +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi new file mode 100644 index 00000000000..836df6f7462 --- /dev/null +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Amarula Solutions(India) + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +#include <dt-bindings/clock/stm32mp1-clksrc.h> +#include "stm32mp15-u-boot.dtsi" +#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" + +&vin { + u-boot,dm-pre-reloc; +}; + +&vddcore { + u-boot,dm-pre-reloc; +}; + +&vdd { + u-boot,dm-pre-reloc; +}; + +&vddq_ddr { + u-boot,dm-pre-reloc; +}; + +&rcc { + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; + + st,pkcs = < + CLK_CKPER_HSE + CLK_FMC_ACLK + CLK_QSPI_ACLK + CLK_ETH_DISABLED + CLK_SDMMC12_PLL4P + CLK_DSI_DSIPLL + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_SPI2S1_PLL3Q + CLK_SPI2S23_PLL3Q + CLK_SPI45_HSI + CLK_SPI6_HSI + CLK_I2C46_HSI + CLK_SDMMC3_PLL4P + CLK_USBO_USBPHY + CLK_ADC_CKPER + CLK_CEC_LSE + CLK_I2C12_HSI + CLK_I2C35_HSI + CLK_UART1_HSI + CLK_UART24_HSI + CLK_UART35_HSI + CLK_UART6_HSI + CLK_UART78_HSI + CLK_SPDIF_PLL4P + CLK_FDCAN_PLL4R + CLK_SAI1_PLL3Q + CLK_SAI2_PLL3Q + CLK_SAI3_PLL3Q + CLK_SAI4_PLL3Q + CLK_RNG1_LSI + CLK_RNG2_LSI + CLK_LPTIM1_PCLK1 + CLK_LPTIM23_PCLK3 + CLK_LPTIM45_LSE + >; + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ + pll2: st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = < 2 65 1 0 0 PQR(1,1,1) >; + frac = < 0x1400 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ + pll3: st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = < 1 33 1 16 36 PQR(1,1,1) >; + frac = < 0x1a04 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ + pll4: st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = < 3 98 5 7 7 PQR(1,1,1) >; + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi new file mode 100644 index 00000000000..0b85175f151 --- /dev/null +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/ { + compatible = "engicam,microgea-stm32mp1", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + vin: regulator-vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vddcore: regulator-vddcore { + compatible = "regulator-fixed"; + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <&vin>; + }; + + vdd: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vin>; + }; + + vddq_ddr: regulator-vddq-ddr { + compatible = "regulator-fixed"; + regulator-name = "vddq_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vin>; + }; +}; + +&dts { + status = "okay"; +}; + +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_a>; + pinctrl-1 = <&fmc_sleep_pins_a>; + status = "okay"; + + nand-controller@4,0 { + status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2{ + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc{ + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; + +&rtc{ + status = "okay"; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; diff --git a/arch/arm/mach-stm32/stm32h7/Kconfig b/arch/arm/mach-stm32/stm32h7/Kconfig index 55e62179504..70233a4b23c 100644 --- a/arch/arm/mach-stm32/stm32h7/Kconfig +++ b/arch/arm/mach-stm32/stm32h7/Kconfig @@ -6,7 +6,11 @@ config TARGET_STM32H743_DISCO config TARGET_STM32H743_EVAL bool "STM32H743 Evaluation board" +config TARGET_STM32H750_ART_PI + bool "STM32H750 ART Pi board" + source "board/st/stm32h743-eval/Kconfig" source "board/st/stm32h743-disco/Kconfig" +source "board/st/stm32h750-art-pi/Kconfig" endif diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 079d66a80c1..7c25266f33e 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -16,13 +16,13 @@ config SPL select SPL_REGMAP select SPL_DM_RESET select SPL_SERIAL_SUPPORT - select SPL_SPI_LOAD select SPL_SYSCON select SPL_WATCHDOG_SUPPORT if WATCHDOG imply BOOTSTAGE_STASH if SPL_BOOTSTAGE imply SPL_BOOTSTAGE if BOOTSTAGE imply SPL_DISPLAY_PRINT imply SPL_LIBDISK_SUPPORT + imply SPL_SPI_LOAD if SPL_SPI_SUPPORT config SYS_SOC default "stm32mp" @@ -77,6 +77,57 @@ config TARGET_ST_STM32MP15x Evalulation board (EV1) or Discovery board (DK1 and DK2). The difference between board are managed with devicetree +config TARGET_MICROGEA_STM32MP1 + bool "Engicam MicroGEA STM32MP1 SOM" + select STM32MP15x + imply BOOTCOUNT_LIMIT + imply BOOTSTAGE + imply CMD_BOOTCOUNT + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + MicroGEA STM32MP1 is a STM32MP157A based Micro SOM. + + MicroGEA STM32MP1 MicroDev 2.0: + * MicroDev 2.0 is a general purpose miniature carrier board with CAN, + LTE and LVDS panel interfaces. + * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board + for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. + + MicroGEA STM32MP1 MicroDev 2.0 7" OF: + * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS + panel and toucscreen. + * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with + pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" + Open Frame Solution board. + +config TARGET_ICORE_STM32MP1 + bool "Engicam i.Core STM32MP1 SOM" + select STM32MP15x + imply BOOTCOUNT_LIMIT + imply BOOTSTAGE + imply CMD_BOOTCOUNT + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A. + + i.Core STM32MP1 EDIMM2.2: + * EDIMM2.2 is a Form Factor Capacitive Evaluation Board. + * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for + creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. + + i.Core STM32MP1 C.TOUCH 2.0 + * C.TOUCH 2.0 is a general purpose Carrier board. + * i.Core STM32MP1 needs to mount on top of this Carrier board + for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. + config TARGET_DH_STM32MP1_PDK2 bool "DH STM32MP1 PDK2" select STM32MP15x @@ -161,7 +212,8 @@ config DEBUG_UART_CLOCK endif source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" -source "board/st/stm32mp1/Kconfig" source "board/dhelectronics/dh_stm32mp1/Kconfig" +source "board/engicam/stm32mp1/Kconfig" +source "board/st/stm32mp1/Kconfig" endif diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index a7e2861764c..e36501a86b2 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -73,15 +73,16 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, size = simple_strtoul(argv[4], NULL, 16); /* check STM32IMAGE presence */ - if (size == 0 && - !stm32prog_header_check((struct raw_header_s *)addr, &header)) { - size = header.image_length + BL_HEADER_SIZE; - - /* uImage detected in STM32IMAGE, execute the script */ - if (IMAGE_FORMAT_LEGACY == - genimg_get_format((void *)(addr + BL_HEADER_SIZE))) - return image_source_script(addr + BL_HEADER_SIZE, - "script@1"); + if (size == 0) { + stm32prog_header_check((struct raw_header_s *)addr, &header); + if (header.type == HEADER_STM32IMAGE) { + size = header.image_length + BL_HEADER_SIZE; + + /* uImage detected in STM32IMAGE, execute the script */ + if (IMAGE_FORMAT_LEGACY == + genimg_get_format((void *)(addr + BL_HEADER_SIZE))) + return image_source_script(addr + BL_HEADER_SIZE, "script@1"); + } } if (IS_ENABLED(CONFIG_DM_VIDEO)) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index d0518d12235..4c4d8a7a69e 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -60,8 +60,6 @@ static const efi_guid_t uuid_mmc[3] = { ROOTFS_MMC2_UUID }; -DECLARE_GLOBAL_DATA_PTR; - /* order of column in flash layout file */ enum stm32prog_col_t { COL_OPTION, @@ -73,6 +71,16 @@ enum stm32prog_col_t { COL_NB_STM32 }; +#define FIP_TOC_HEADER_NAME 0xAA640001 + +struct fip_toc_header { + u32 name; + u32 serial_number; + u64 flags; +}; + +DECLARE_GLOBAL_DATA_PTR; + /* partition handling routines : CONFIG_CMD_MTDPARTS */ int mtdparts_init(void); int find_dev_and_part(const char *id, struct mtd_device **dev, @@ -88,46 +96,57 @@ char *stm32prog_get_error(struct stm32prog_data *data) return data->error; } -u8 stm32prog_header_check(struct raw_header_s *raw_header, - struct image_header_s *header) +static bool stm32prog_is_fip_header(struct fip_toc_header *header) +{ + return (header->name == FIP_TOC_HEADER_NAME) && header->serial_number; +} + +void stm32prog_header_check(struct raw_header_s *raw_header, + struct image_header_s *header) { unsigned int i; - header->present = 0; + if (!raw_header || !header) { + log_debug("%s:no header data\n", __func__); + return; + } + + header->type = HEADER_NONE; header->image_checksum = 0x0; header->image_length = 0x0; - if (!raw_header || !header) { - log_debug("%s:no header data\n", __func__); - return -1; + if (stm32prog_is_fip_header((struct fip_toc_header *)raw_header)) { + header->type = HEADER_FIP; + return; } + if (raw_header->magic_number != (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) { log_debug("%s:invalid magic number : 0x%x\n", __func__, raw_header->magic_number); - return -2; + return; } /* only header v1.0 supported */ if (raw_header->header_version != 0x00010000) { log_debug("%s:invalid header version : 0x%x\n", __func__, raw_header->header_version); - return -3; + return; } if (raw_header->reserved1 != 0x0 || raw_header->reserved2) { log_debug("%s:invalid reserved field\n", __func__); - return -4; + return; } for (i = 0; i < (sizeof(raw_header->padding) / 4); i++) { if (raw_header->padding[i] != 0) { log_debug("%s:invalid padding field\n", __func__); - return -5; + return; } } - header->present = 1; + header->type = HEADER_STM32IMAGE; header->image_checksum = le32_to_cpu(raw_header->image_checksum); header->image_length = le32_to_cpu(raw_header->image_length); - return 0; + return; } static u32 stm32prog_header_checksum(u32 addr, struct image_header_s *header) @@ -356,8 +375,8 @@ static int parse_flash_layout(struct stm32prog_data *data, data->part_nb = 0; /* check if STM32image is detected */ - if (!stm32prog_header_check((struct raw_header_s *)addr, - &data->header)) { + stm32prog_header_check((struct raw_header_s *)addr, &data->header); + if (data->header.type == HEADER_STM32IMAGE) { u32 checksum; addr = addr + BL_HEADER_SIZE; @@ -1410,7 +1429,7 @@ static int stm32prog_copy_fsbl(struct stm32prog_part_t *part) if (part->target != STM32PROG_NAND && part->target != STM32PROG_SPI_NAND) - return -1; + return -EINVAL; dfu = dfu_get_entity(part->alt_id); @@ -1420,8 +1439,10 @@ static int stm32prog_copy_fsbl(struct stm32prog_part_t *part) ret = dfu->read_medium(dfu, 0, (void *)&raw_header, &size); if (ret) return ret; - if (stm32prog_header_check(&raw_header, &header)) - return -1; + + stm32prog_header_check(&raw_header, &header); + if (header.type != HEADER_STM32IMAGE) + return -ENOENT; /* read header + payload */ size = header.image_length + BL_HEADER_SIZE; diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index 18af99c78bc..581b10d0ac9 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -37,8 +37,14 @@ enum stm32prog_link_t { LINK_UNDEFINED, }; +enum stm32prog_header_t { + HEADER_NONE, + HEADER_STM32IMAGE, + HEADER_FIP, +}; + struct image_header_s { - bool present; + enum stm32prog_header_t type; u32 image_checksum; u32 image_length; }; @@ -160,8 +166,8 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, int stm32prog_pmic_start(struct stm32prog_data *data); /* generic part*/ -u8 stm32prog_header_check(struct raw_header_s *raw_header, - struct image_header_s *header); +void stm32prog_header_check(struct raw_header_s *raw_header, + struct image_header_s *header); int stm32prog_dfu_init(struct stm32prog_data *data); void stm32prog_next_phase(struct stm32prog_data *data); void stm32prog_do_reset(struct stm32prog_data *data); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index a51e5e3ec86..2b92e3b1498 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -309,11 +309,10 @@ static u8 stm32prog_header(struct stm32prog_data *data) /* force cleanup to avoid issue with previous read */ dfu_transaction_cleanup(dfu_entity); - ret = stm32prog_header_check(data->header_data, - &data->header); + stm32prog_header_check(data->header_data, &data->header); - /* no header : max size is partition size */ - if (ret) { + /* no stm32 image header : max size is partition size */ + if (data->header.type != HEADER_STM32IMAGE) { dfu_entity->get_medium_size(dfu_entity, &size); data->header.image_length = size; } @@ -389,7 +388,7 @@ static u8 stm32prog_start(struct stm32prog_data *data, u32 address) data->dfu_seq = 0; printf("\n received length = 0x%x\n", data->cursor); - if (data->header.present) { + if (data->header.type == HEADER_STM32IMAGE) { if (data->cursor != (data->header.image_length + BL_HEADER_SIZE)) { stm32prog_err("transmission interrupted (length=0x%x expected=0x%x)", @@ -789,7 +788,7 @@ static void download_command(struct stm32prog_data *data) } } - if (image_header->present) { + if (data->header.type == HEADER_STM32IMAGE) { if (data->cursor <= BL_HEADER_SIZE) goto end; /* compute checksum on payload */ diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 897ec13ad81..8115d58b199 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -372,89 +372,78 @@ u32 get_cpu_package(void) return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); } -void get_soc_name(char name[SOC_NAME_SIZE]) +static const char * const soc_type[] = { + "????", + "151C", "151A", "151F", "151D", + "153C", "153A", "153F", "153D", + "157C", "157A", "157F", "157D" +}; + +static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" }; +static const char * const soc_rev[] = { "?", "A", "B", "Z" }; + +static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, + unsigned int *rev) { - char *cpu_s, *cpu_r, *pkg; + u32 cpu_type = get_cpu_type(); + u32 ct = cpu_type & ~(BIT(7) | BIT(0)); + u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0)); + u32 cp = get_cpu_package(); - /* MPUs Part Numbers */ - switch (get_cpu_type()) { - case CPU_STM32MP157Fxx: - cpu_s = "157F"; - break; - case CPU_STM32MP157Dxx: - cpu_s = "157D"; - break; - case CPU_STM32MP157Cxx: - cpu_s = "157C"; - break; - case CPU_STM32MP157Axx: - cpu_s = "157A"; - break; - case CPU_STM32MP153Fxx: - cpu_s = "153F"; - break; - case CPU_STM32MP153Dxx: - cpu_s = "153D"; + /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */ + switch (ct) { + case CPU_STM32MP151Cxx: + *type = cm + 1; break; case CPU_STM32MP153Cxx: - cpu_s = "153C"; - break; - case CPU_STM32MP153Axx: - cpu_s = "153A"; - break; - case CPU_STM32MP151Fxx: - cpu_s = "151F"; - break; - case CPU_STM32MP151Dxx: - cpu_s = "151D"; + *type = cm + 5; break; - case CPU_STM32MP151Cxx: - cpu_s = "151C"; - break; - case CPU_STM32MP151Axx: - cpu_s = "151A"; + case CPU_STM32MP157Cxx: + *type = cm + 9; break; default: - cpu_s = "????"; + *type = 0; break; } /* Package */ - switch (get_cpu_package()) { + switch (cp) { case PKG_AA_LBGA448: - pkg = "AA"; - break; case PKG_AB_LBGA354: - pkg = "AB"; - break; case PKG_AC_TFBGA361: - pkg = "AC"; - break; case PKG_AD_TFBGA257: - pkg = "AD"; + *pkg = cp; break; default: - pkg = "??"; + *pkg = 0; break; } - /* REVISION */ + /* Revision */ switch (get_cpu_rev()) { case CPU_REVA: - cpu_r = "A"; + *rev = 1; break; case CPU_REVB: - cpu_r = "B"; + *rev = 2; break; case CPU_REVZ: - cpu_r = "Z"; + *rev = 3; break; default: - cpu_r = "?"; + *rev = 0; break; } +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + unsigned int type, pkg, rev; - snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); + get_cpu_string_offsets(&type, &pkg, &rev); + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", + soc_type[type], soc_pkg[pkg], soc_rev[rev]); } #if defined(CONFIG_DISPLAY_CPUINFO) @@ -502,8 +491,8 @@ static void setup_boot_mode(void) if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL)) gd->flags &= ~(GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE); - printf("uart%d = %s not found in device tree!\n", - instance, cmd); + log_err("uart%d = %s not found in device tree!\n", + instance + 1, cmd); break; } sprintf(cmd, "%d", dev_seq(dev)); @@ -514,7 +503,7 @@ static void setup_boot_mode(void) if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) { gd->flags &= ~(GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE); - printf("serial boot with console enabled!\n"); + log_info("serial boot with console enabled!\n"); } break; case BOOT_SERIAL_USB: @@ -546,7 +535,7 @@ static void setup_boot_mode(void) switch (forced_mode) { case BOOT_FASTBOOT: - printf("Enter fastboot!\n"); + log_info("Enter fastboot!\n"); env_set("preboot", "env set preboot; fastboot 0"); break; case BOOT_STM32PROG: @@ -556,7 +545,7 @@ static void setup_boot_mode(void) case BOOT_UMS_MMC0: case BOOT_UMS_MMC1: case BOOT_UMS_MMC2: - printf("Enter UMS!\n"); + log_info("Enter UMS!\n"); instance = forced_mode - BOOT_UMS_MMC0; sprintf(cmd, "env set preboot; ums 0 mmc %d", instance); env_set("preboot", cmd); @@ -646,11 +635,23 @@ static int setup_serial_number(void) return 0; } +static void setup_soc_type_pkg_rev(void) +{ + unsigned int type, pkg, rev; + + get_cpu_string_offsets(&type, &pkg, &rev); + + env_set("soc_type", soc_type[type]); + env_set("soc_pkg", soc_pkg[pkg]); + env_set("soc_rev", soc_rev[rev]); +} + int arch_misc_init(void) { setup_boot_mode(); setup_mac_address(); setup_serial_number(); + setup_soc_type_pkg_rev(); return 0; } diff --git a/board/engicam/stm32mp1/Kconfig b/board/engicam/stm32mp1/Kconfig new file mode 100644 index 00000000000..c800fd4e601 --- /dev/null +++ b/board/engicam/stm32mp1/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ICORE_STM32MP1 || TARGET_MICROGEA_STM32MP1 + +config SYS_BOARD + default "stm32mp1" + +config SYS_VENDOR + default "engicam" + +config SYS_CONFIG_NAME + default "stm32mp1" + +endif diff --git a/board/engicam/stm32mp1/MAINTAINERS b/board/engicam/stm32mp1/MAINTAINERS new file mode 100644 index 00000000000..405ff991851 --- /dev/null +++ b/board/engicam/stm32mp1/MAINTAINERS @@ -0,0 +1,26 @@ +MicroGEA-STM32MP1-MICRODEV2.0 +M: Jagan Teki <jagan@amarulasolutions.com> +M: Matteo Lisi <matteo.lisi@engicam.com> +S: Maintained +F: arch/arm/dts/stm32mp15*microgea* +F: configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig + +MicroGEA-STM32MP1-MICRODEV2.0-OF7 +M: Jagan Teki <jagan@amarulasolutions.com> +M: Matteo Lisi <matteo.lisi@engicam.com> +S: Maintained +F: configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig + +i.Core-STM32MP1-CTOUCH2.0 +M: Jagan Teki <jagan@amarulasolutions.com> +M: Matteo Lisi <matteo.lisi@engicam.com> +S: Maintained +F: configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig + +i.Core-STM32MP1-EDIMM2.2 +M: Jagan Teki <jagan@amarulasolutions.com> +M: Matteo Lisi <matteo.lisi@engicam.com> +S: Maintained +F: arch/arm/dts/stm32mp15*icore* +F: board/engicam/stm32mp1 +F: configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig diff --git a/board/engicam/stm32mp1/Makefile b/board/engicam/stm32mp1/Makefile new file mode 100644 index 00000000000..65560df2900 --- /dev/null +++ b/board/engicam/stm32mp1/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += stm32mp1.o +endif diff --git a/board/engicam/stm32mp1/spl.c b/board/engicam/stm32mp1/spl.c new file mode 100644 index 00000000000..79adb5f5295 --- /dev/null +++ b/board/engicam/stm32mp1/spl.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Copyright (C) 2020 Engicam S.r.l. + * Copyright (C) 2020 Amarula Solutions(India) + */ + +#include <common.h> +#include <asm/io.h> + +/* board early initialisation in board_f: need to use global variable */ +static u32 opp_voltage_mv __section(".data"); + +void board_vddcore_init(u32 voltage_mv) +{ + if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER_SUPPORT)) + opp_voltage_mv = voltage_mv; +} + +int board_early_init_f(void) +{ + return 0; +} + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ +#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) + +#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) +#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) + + /* UART4 clock enable */ + setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); + +#define GPIOG_BASE 0x50008000 + /* GPIOG clock enable */ + writel(BIT(6), RCC_MP_AHB4ENSETR); + /* GPIO configuration for ST boards: Uart4 TX = G11 */ + writel(0xffbfffff, GPIOG_BASE + 0x00); + writel(0x00006000, GPIOG_BASE + 0x24); +#else + +#error("CONFIG_DEBUG_UART_BASE: not supported value") + +#endif +} +#endif diff --git a/board/engicam/stm32mp1/stm32mp1.c b/board/engicam/stm32mp1/stm32mp1.c new file mode 100644 index 00000000000..8bf9c9c67d3 --- /dev/null +++ b/board/engicam/stm32mp1/stm32mp1.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Copyright (C) 2020 Engicam S.r.l. + * Copyright (C) 2020 Amarula Solutions(India) + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +#include <common.h> +#include <env.h> +#include <env_internal.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + char *mode; + const char *fdt_compat; + int fdt_compat_len; + + if (IS_ENABLED(CONFIG_TFABOOT)) + mode = "trusted"; + else + mode = "basic"; + + printf("Board: stm32mp1 in %s mode", mode); + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) + printf(" (%s)", fdt_compat); + puts("\n"); + + return 0; +} + +/* board dependent setup after realloc */ +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; + + if (IS_ENABLED(CONFIG_DM_REGULATOR)) + regulators_enable_boot_on(_DEBUG); + + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +enum env_location env_get_location(enum env_operation op, int prio) +{ + u32 bootmode = get_bootmode(); + + if (prio) + return ENVL_UNKNOWN; + + switch (bootmode & TAMP_BOOT_DEVICE_MASK) { + case BOOT_FLASH_SD: + case BOOT_FLASH_EMMC: + if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) + return ENVL_MMC; + else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4)) + return ENVL_EXT4; + else + return ENVL_NOWHERE; + + case BOOT_FLASH_NAND: + case BOOT_FLASH_SPINAND: + if (CONFIG_IS_ENABLED(ENV_IS_IN_UBI)) + return ENVL_UBI; + else + return ENVL_NOWHERE; + + case BOOT_FLASH_NOR: + if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + else + return ENVL_NOWHERE; + + default: + return ENVL_NOWHERE; + } +} + +const char *env_ext4_get_intf(void) +{ + u32 bootmode = get_bootmode(); + + switch (bootmode & TAMP_BOOT_DEVICE_MASK) { + case BOOT_FLASH_SD: + case BOOT_FLASH_EMMC: + return "mmc"; + default: + return ""; + } +} + +const char *env_ext4_get_dev_part(void) +{ + static char *const dev_part[] = {"0:auto", "1:auto", "2:auto"}; + u32 bootmode = get_bootmode(); + + return dev_part[(bootmode & TAMP_BOOT_INSTANCE_MASK) - 1]; +} + +int mmc_get_env_dev(void) +{ + u32 bootmode = get_bootmode(); + + return (bootmode & TAMP_BOOT_INSTANCE_MASK) - 1; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif diff --git a/board/st/stm32h750-art-pi/Kconfig b/board/st/stm32h750-art-pi/Kconfig new file mode 100644 index 00000000000..c31b9849fde --- /dev/null +++ b/board/st/stm32h750-art-pi/Kconfig @@ -0,0 +1,19 @@ +if TARGET_STM32H750_ART_PI + +config SYS_BOARD + string + default "stm32h750-art-pi" + +config SYS_VENDOR + string + default "st" + +config SYS_SOC + string + default "stm32h7" + +config SYS_CONFIG_NAME + string + default "stm32h750-art-pi" + +endif diff --git a/board/st/stm32h750-art-pi/MAINTAINERS b/board/st/stm32h750-art-pi/MAINTAINERS new file mode 100644 index 00000000000..9578833068b --- /dev/null +++ b/board/st/stm32h750-art-pi/MAINTAINERS @@ -0,0 +1,7 @@ +STM32H750 ART PI BOARD +M: Dillon Min <dillon.minfei@gmail.com> +S: Maintained +F: board/st/stm32h750-art-pi +F: include/configs/stm32h750-art-pi.h +F: configs/stm32h750-art-pi_defconfig +F: arch/arm/dts/stm32h7* diff --git a/board/st/stm32h750-art-pi/Makefile b/board/st/stm32h750-art-pi/Makefile new file mode 100644 index 00000000000..a06de87526b --- /dev/null +++ b/board/st/stm32h750-art-pi/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021, RT-Thread - All Rights Reserved +# Author(s): Dillon Min, <dillon.minfei@gmail.com> for RT-Thread. + +obj-y := stm32h750-art-pi.o diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c new file mode 100644 index 00000000000..5785b2e5750 --- /dev/null +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, STMicroelectronics - All Rights Reserved + * Author(s): Dillon Min <dillon.minfei@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <init.h> +#include <log.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + if (fdtdec_setup_mem_size_base() != 0) + ret = -EINVAL; + + return ret; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +u32 get_board_rev(void) +{ + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + return 0; +} diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 759181fb5d1..261ec15e1b0 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -347,6 +347,9 @@ static int board_check_usb_power(void) u32 nb_blink; u8 i; + if (!IS_ENABLED(CONFIG_ADC)) + return -ENODEV; + node = ofnode_path("/config"); if (!ofnode_valid(node)) { log_debug("no /config node?\n"); @@ -370,11 +373,7 @@ static int board_check_usb_power(void) /* perform maximum of 2 ADC measurements to detect power supply current */ for (i = 0; i < 2; i++) { - if (IS_ENABLED(CONFIG_ADC)) - ret = adc_measurement(node, adc_count, &min_uV, &max_uV); - else - ret = -ENODEV; - + ret = adc_measurement(node, adc_count, &min_uV, &max_uV); if (ret) return ret; diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig new file mode 100644 index 00000000000..447af5b654e --- /dev/null +++ b/configs/stm32h750-art-pi_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32=y +CONFIG_SYS_TEXT_BASE=0x90000000 +CONFIG_SYS_MALLOC_F_LEN=0xF00 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_STM32H7=y +CONFIG_TARGET_STM32H750_ART_PI=y +CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_DEFAULT_FDT_FILE="stm32h750i-art-pi" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_DM_MMC=y +CONFIG_STM32_SDMMC2=y +# CONFIG_PINCTRL_FULL is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_BAUDRATE=2000000 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttySTM0,2000000 root=/dev/ram loglevel=8" +CONFIG_BOOTCOMMAND="bootm 90080000" +CONFIG_REQUIRE_SERIAL_CONSOLE=y +CONFIG_SERIAL_PRESENT=y +CONFIG_DM_SERIAL=y +CONFIG_STM32_SERIAL=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x0 +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y +CONFIG_FIT_FULL_CHECK=y +CONFIG_FIT_PRINT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_DM_DMA=y diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig new file mode 100644 index 00000000000..55f9fb94277 --- /dev/null +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 +CONFIG_ENV_OFFSET=0x280000 +CONFIG_SPL_TEXT_BASE=0x2FFC2500 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL=y +CONFIG_TARGET_ICORE_STM32MP1=y +CONFIG_ENV_OFFSET_REDUND=0x2C0000 +# CONFIG_ARMV7_VIRT is not set +CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-ctouch2" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_CMD_ADTIMG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_ADC=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_SPL_ENV_IS_NOWHERE is not set +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_STM32=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y +CONFIG_STM32_FMC2_EBI=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_STM32_SDMMC2=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DWC_ETH_QOS=y +CONFIG_PHY=y +CONFIG_PINCONF=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_PINCTRL_STMFX=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_STPMIC1=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REMOTEPROC_STM32_COPRO=y +CONFIG_DM_RTC=y +CONFIG_RTC_STM32=y +CONFIG_SERIAL_RX_BUFFER=y +CONFIG_WDT=y +CONFIG_WDT_STM32MP=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig new file mode 100644 index 00000000000..2bfaf65d3cc --- /dev/null +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 +CONFIG_ENV_OFFSET=0x280000 +CONFIG_SPL_TEXT_BASE=0x2FFC2500 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL=y +CONFIG_TARGET_ICORE_STM32MP1=y +CONFIG_ENV_OFFSET_REDUND=0x2C0000 +# CONFIG_ARMV7_VIRT is not set +CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-icore-stm32mp1-edimm2.2" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_CMD_ADTIMG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_ADC=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_SPL_ENV_IS_NOWHERE is not set +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_STM32=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y +CONFIG_STM32_FMC2_EBI=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_STM32_SDMMC2=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DWC_ETH_QOS=y +CONFIG_PHY=y +CONFIG_PINCONF=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_PINCTRL_STMFX=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_STPMIC1=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REMOTEPROC_STM32_COPRO=y +CONFIG_DM_RTC=y +CONFIG_RTC_STM32=y +CONFIG_SERIAL_RX_BUFFER=y +CONFIG_WDT=y +CONFIG_WDT_STM32MP=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig new file mode 100644 index 00000000000..c0c7ff11c8b --- /dev/null +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 +CONFIG_ENV_OFFSET=0x280000 +CONFIG_SPL_TEXT_BASE=0x2FFC2500 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL=y +CONFIG_TARGET_MICROGEA_STM32MP1=y +CONFIG_ENV_OFFSET_REDUND=0x2C0000 +# CONFIG_ARMV7_VIRT is not set +CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0-of7" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_CMD_ADTIMG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_ADC=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_SPL_ENV_IS_NOWHERE is not set +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_STM32=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y +CONFIG_STM32_FMC2_EBI=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_STM32_SDMMC2=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DWC_ETH_QOS=y +CONFIG_PHY=y +CONFIG_PINCONF=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_PINCTRL_STMFX=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_STPMIC1=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REMOTEPROC_STM32_COPRO=y +CONFIG_DM_RTC=y +CONFIG_RTC_STM32=y +CONFIG_SERIAL_RX_BUFFER=y +CONFIG_WDT=y +CONFIG_WDT_STM32MP=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig new file mode 100644 index 00000000000..17aad82b88c --- /dev/null +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_SYS_MEMTEST_START=0xc0000000 +CONFIG_SYS_MEMTEST_END=0xc4000000 +CONFIG_ENV_OFFSET=0x280000 +CONFIG_SPL_TEXT_BASE=0x2FFC2500 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL=y +CONFIG_TARGET_MICROGEA_STM32MP1=y +CONFIG_ENV_OFFSET_REDUND=0x2C0000 +# CONFIG_ARMV7_VIRT is not set +CONFIG_DEFAULT_DEVICE_TREE="stm32mp157a-microgea-stm32mp1-microdev2.0" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SYS_PROMPT="STM32MP> " +CONFIG_CMD_ADTIMG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_ADC=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_SPL_ENV_IS_NOWHERE is not set +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_STM32=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y +CONFIG_STM32_FMC2_EBI=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_STM32_SDMMC2=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DWC_ETH_QOS=y +CONFIG_PHY=y +CONFIG_PINCONF=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_PINCTRL_STMFX=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_STPMIC1=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REMOTEPROC_STM32_COPRO=y +CONFIG_DM_RTC=y +CONFIG_RTC_STM32=y +CONFIG_SERIAL_RX_BUFFER=y +CONFIG_WDT=y +CONFIG_WDT_STM32MP=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 540ad851387..3e25cc7a018 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -268,6 +268,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev) u32 swp_fmc; ofnode bank_node; char *bank_name; + char _bank_name[128] = {0}; u8 bank = 0; int ret; @@ -300,6 +301,8 @@ static int stm32_fmc_of_to_plat(struct udevice *dev) dev_for_each_subnode(bank_node, dev) { /* extract the bank index from DT */ bank_name = (char *)ofnode_get_name(bank_node); + strlcpy(_bank_name, bank_name, sizeof(_bank_name)); + bank_name = (char *)_bank_name; strsep(&bank_name, "@"); if (!bank_name) { pr_err("missing sdram bank index"); diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h new file mode 100644 index 00000000000..3fd54611677 --- /dev/null +++ b/include/configs/stm32h750-art-pi.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021, STMicroelectronics - All Rights Reserved + * Author(s): Dillon Min <dillon.minfei@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <config.h> +#include <linux/sizes.h> + +/* For booting Linux, use the first 16MB of memory */ +#define CONFIG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M) + +#define CONFIG_SYS_FLASH_BASE 0x90000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_SYS_LOAD_ADDR 0xC1800000 +#define CONFIG_LOADADDR 0xC1800000 + +#define CONFIG_SYS_HZ_CLOCK 1000000 + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0xC0008000\0" \ + "fdtfile=stm32h750i-art-pi.dtb\0" \ + "fdt_addr_r=0xC0408000\0" \ + "scriptaddr=0xC0418000\0" \ + "pxefile_addr_r=0xC0428000\0" \ + "ramdisk_addr_r=0xC0438000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index db2117a3d7c..440efa1a55a 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -50,13 +50,12 @@ /* SPL support */ #ifdef CONFIG_SPL /* SPL use DDR */ -#define CONFIG_SPL_BSS_START_ADDR 0xC0200000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0xC0300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x01D00000 -/* limit SYSRAM usage to first 128 KB */ -#define CONFIG_SPL_MAX_SIZE 0x00020000 +/* Restrict SPL to fit within SYSRAM */ +#define STM32_SYSRAM_END (STM32_SYSRAM_BASE + STM32_SYSRAM_SIZE) +#define CONFIG_SPL_MAX_FOOTPRINT (STM32_SYSRAM_END - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_STACK (STM32_SYSRAM_BASE + \ STM32_SYSRAM_SIZE) #endif /* #ifdef CONFIG_SPL */ diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h index ab91d2b7f63..90ef2e15906 100644 --- a/include/dt-bindings/memory/stm32-sdram.h +++ b/include/dt-bindings/memory/stm32-sdram.h @@ -34,8 +34,10 @@ #define TXSR_1 (1 - 1) #define TXSR_6 (6 - 1) #define TXSR_7 (7 - 1) +#define TXSR_8 (8 - 1) #define TRAS_1 (1 - 1) #define TRAS_4 (4 - 1) +#define TRAS_6 (6 - 1) #define TRC_6 (6 - 1) #define TWR_1 (1 - 1) #define TWR_2 (2 - 1) |