diff options
| author | Neha Malcom Francis <n-francis@ti.com> | 2024-01-30 18:33:02 +0530 |
|---|---|---|
| committer | Francesco Dolcini <francesco.dolcini@toradex.com> | 2024-03-21 14:26:33 +0000 |
| commit | 33aa9b544a4ab8ce34d1bd7f2574b3669ea94f84 (patch) | |
| tree | 1d533b4934105217c4c98028f05747f653355a7c | |
| parent | aeafe13005fa46935cde80c62bfe71ca6a94bc8b (diff) | |
arm: mach-k3: j721s2_init: Support less than max DDR controllers
The number of DDR controllers to be initialised and used should depend
on the device tree with the constraint of the maximum number of
controllers the device supports. Since J721S2 has multiple (2)
controllers, instead of hardcoding the number of probes, move to
depending on the device tree UCLASS_RAM nodes present.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
| -rw-r--r-- | arch/arm/mach-k3/j721s2_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index 81f0e7305a1..7818f5121bf 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -236,7 +236,7 @@ void k3_mem_init(void) panic("DRAM 0 init failed: %d\n", ret); ret = uclass_next_device_err(&dev); - if (ret) + if (ret && ret != -ENODEV) panic("DRAM 1 init failed: %d\n", ret); } spl_enable_cache(); |