diff options
| author | Hari Nagalla <hnagalla@ti.com> | 2023-05-31 00:56:06 -0500 |
|---|---|---|
| committer | Udit Kumar <u-kumar1@ti.com> | 2023-05-31 16:21:19 +0530 |
| commit | 1d6d1188b043a56710153a713a6723f892a8b587 (patch) | |
| tree | 24ef1cc9b5cecec0b7f5d6d6cb541830d8ebb007 | |
| parent | f8424f0d73a2deae9d6e2ebfb097bb61f534a019 (diff) | |
arm: dts: k3-j784s4-mcu: Add R5F remote processor node
The J784S4 SoCs have a dual-core Arm Cortex-R5F processor (R5FSS)
subsystem/cluster in MCU voltage domain.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
| -rw-r--r-- | arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi index 64bd3dee14..010390bc8f 100644 --- a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi @@ -309,4 +309,44 @@ ti,cpts-periodic-outputs = <2>; }; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41000000 0x00010000>, + <0x41010000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <346>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 346 1>; + firmware-name = "j784s4-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41400000 0x00010000>, + <0x41410000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <347>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 347 1>; + firmware-name = "j784s4-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; }; |