diff options
| author | Tom Rini <trini@konsulko.com> | 2020-12-28 07:44:03 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-12-28 07:44:03 -0500 |
| commit | ab865a8ee5c1a069f72a171270c02c99ccda7bfa (patch) | |
| tree | b4ac4a8519bc0128f12de2a13a8311c0f845f5b5 | |
| parent | 1c3d1aa00617dbbdd92f0d5a2df40d7784dfcc13 (diff) | |
| parent | 26c7048dd9d04158a23e9dbfe3f0dccc4febcaed (diff) | |
Merge tag 'u-boot-imx-20201227' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Fixes for 2021.1
----------------
CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/5680
- fixes for Variscite dart6ul
- imx8mp : increase malloc area
- fixes for bx50v3
- imx8m: HS400ES and UHS for EVK
- imx8qm-rom7720: fix phy bind
37 files changed, 428 insertions, 105 deletions
diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi index 80d6475b7c0..9e0d264b71f 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -118,8 +118,11 @@ &usdhc1 { u-boot,dm-spl; + mmc-hs400-1_8v; }; &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi index 771ab635f1a..701af4434d5 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi @@ -118,8 +118,11 @@ &usdhc1 { u-boot,dm-spl; + mmc-hs400-1_8v; }; &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; diff --git a/arch/arm/dts/imx6q-ba16.dtsi b/arch/arm/dts/imx6q-ba16.dtsi index 7d8f61f2fd7..9da2bb6e869 100644 --- a/arch/arm/dts/imx6q-ba16.dtsi +++ b/arch/arm/dts/imx6q-ba16.dtsi @@ -174,6 +174,17 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; status = "okay"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@4 { + reg = <4>; + qca,clk-out-frequency = <125000000>; + }; + }; }; &hdmi { diff --git a/arch/arm/dts/imx6ull-dart-6ul.dtsi b/arch/arm/dts/imx6ull-dart-6ul.dtsi index e96669f493b..805a382da9a 100644 --- a/arch/arm/dts/imx6ull-dart-6ul.dtsi +++ b/arch/arm/dts/imx6ull-dart-6ul.dtsi @@ -14,6 +14,10 @@ chosen { stdout-path = &uart1; }; + + aliases { + eeprom0 = &eeprom_som; + }; }; &fec1 { @@ -52,6 +56,10 @@ }; }; +&gpio1 { + u-boot,dm-pre-reloc; +}; + &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; @@ -96,10 +104,13 @@ scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; status = "okay"; + u-boot,dm-pre-reloc; - eeprom@50 { - compatible = "cat,24c32"; + eeprom_som: eeprom@50 { + u-boot,dm-pre-reloc; + compatible = "atmel,24c04"; reg = <0x50>; + status = "okay"; }; }; @@ -205,6 +216,7 @@ }; pinctrl_i2c2: i2cgrp { + u-boot,dm-pre-reloc; fsl,pins = < MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 @@ -212,6 +224,7 @@ }; pinctrl_i2c2_gpio: i2c2grp_gpio { + u-boot,dm-pre-reloc; fsl,pins = < MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi index baa5f997d01..d6b9dedd168 100644 --- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi @@ -10,19 +10,19 @@ led0 { label = "gen_led0"; gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led1 { label = "gen_led1"; gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led2 { label = "gen_led2"; gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; - default-state = "none"; + default-state = "off"; }; led3 { @@ -70,7 +70,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_espi2>; - cs-gpios = <&gpio5 9 0>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; eeprom@0 { @@ -210,7 +210,7 @@ >; }; - pinctrl_pcal6414: pcal6414-gpio { + pinctrl_pcal6414: pcal6414-gpiogrp { fsl,pins = < MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 >; @@ -240,7 +240,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 @@ -259,7 +259,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 @@ -271,7 +271,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi index fc1aebb2feb..6d80a529ae7 100644 --- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi @@ -37,6 +37,10 @@ /delete-property/ assigned-clock-rates; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + &fec1 { phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi index 801bd02eaed..b88c3c99b00 100644 --- a/arch/arm/dts/imx8mm-beacon-som.dtsi +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi @@ -24,6 +24,26 @@ cpu-supply = <&buck2_reg>; }; +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -52,9 +72,10 @@ pmic@4b { compatible = "rohm,bd71847"; reg = <0x4b>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; regulators { @@ -116,7 +137,7 @@ ldo1_reg: LDO1 { regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; + regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; @@ -124,7 +145,7 @@ ldo2_reg: LDO2 { regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; @@ -164,7 +185,7 @@ status = "okay"; eeprom@50 { - compatible = "microchip, at24c64d", "atmel,24c64"; + compatible = "microchip,24c64", "atmel,24c64"; pagesize = <32>; read-only; /* Manufacturing EEPROM programmed at factory */ reg = <0x50>; @@ -190,6 +211,7 @@ host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; clocks = <&osc_32k>; + max-speed = <4000000>; clock-names = "extclk"; }; }; @@ -270,9 +292,9 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; @@ -289,7 +311,7 @@ >; }; - pinctrl_usdhc1_gpio: usdhc1grpgpio { + pinctrl_usdhc1_gpio: usdhc1gpiogrp { fsl,pins = < MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 >; @@ -306,7 +328,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 @@ -317,7 +339,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 @@ -344,7 +366,7 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 @@ -360,7 +382,7 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index b5c12105a9d..e843a5648e8 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -46,6 +46,10 @@ u-boot,dm-spl; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + &pinctrl_reg_usdhc2_vmmc { u-boot,dm-spl; }; @@ -96,10 +100,14 @@ &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; }; &i2c1 { diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index 1e5e11592f7..05ee062548e 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -18,10 +18,18 @@ aliases { ethernet0 = &fec1; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -29,14 +37,6 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; }; cpus { @@ -68,6 +68,7 @@ nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -80,6 +81,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -92,6 +94,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -104,6 +107,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -125,7 +129,7 @@ opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; + opp-microvolt = <950000>; opp-supported-hw = <0xc>, <0x7>; clock-latency-ns = <150000>; opp-suspend; @@ -204,6 +208,38 @@ arm,no-tick-in-suspend; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + usbphynop1: usbphynop1 { compatible = "usb-nop-xceiv"; clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; @@ -227,12 +263,14 @@ ranges = <0x0 0x0 0x0 0x3e000000>; aips1: bus@30000000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30000000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x30000000 0x30000000 0x400000>; sai1: sai@30010000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30010000 0x10000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; @@ -246,6 +284,7 @@ }; sai2: sai@30020000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; @@ -273,6 +312,7 @@ }; sai5: sai@30050000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; @@ -286,6 +326,7 @@ }; sai6: sai@30060000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; @@ -363,6 +404,13 @@ gpio-ranges = <&iomuxc 0 119 30>; }; + tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; + }; + wdog1: watchdog@30280000 { compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; @@ -419,7 +467,7 @@ reg = <0x30340000 0x10000>; }; - ocotp: ocotp-ctrl@30350000 { + ocotp: efuse@30350000 { compatible = "fsl,imx8mm-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; @@ -455,6 +503,8 @@ compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; + clock-names = "snvs-pwrkey"; linux,keycode = <KEY_POWER>; wakeup-source; status = "disabled"; @@ -469,16 +519,20 @@ <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MM_CLK_NOC>, + assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, + <&clk IMX8MM_CLK_A53_CORE>, + <&clk IMX8MM_CLK_NOC>, <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MM_SYS_PLL3>, <&clk IMX8MM_VIDEO_PLL1>, <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_ARM_PLL_OUT>, + <&clk IMX8MM_SYS_PLL3_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; - assigned-clock-rates = <0>, + assigned-clock-rates = <0>, <0>, <0>, <400000000>, <400000000>, <750000000>, @@ -496,7 +550,8 @@ }; aips2: bus@30400000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30400000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x30400000 0x30400000 0x400000>; @@ -555,10 +610,12 @@ }; aips3: bus@30800000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30800000 0x400000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x8000000 0x8000000 0x10000000>; ecspi1: spi@30820000 { compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; @@ -718,6 +775,14 @@ status = "disabled"; }; + mu: mailbox@30aa0000 { + compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_MU_ROOT>; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; @@ -760,6 +825,19 @@ status = "disabled"; }; + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, + <&clk IMX8MM_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; @@ -776,7 +854,8 @@ reg = <0x30be0000 0x10000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, <&clk IMX8MM_CLK_ENET1_ROOT>, <&clk IMX8MM_CLK_ENET_TIMER>, @@ -800,7 +879,8 @@ }; aips4: bus@32c00000 { - compatible = "simple-bus"; + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x32c00000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; @@ -896,7 +976,6 @@ ddr-pmu@3d800000 { compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; - interrupt-parent = <&gic>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 4419679d4c6..025090fff4d 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -47,6 +47,10 @@ u-boot,dm-spl; }; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + &pinctrl_uart2 { u-boot,dm-spl; }; @@ -93,10 +97,14 @@ &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; }; &wdog1 { diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 24a93ac2d69..4f00b5a3a91 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -49,6 +49,10 @@ }; ®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + +®_usdhc2_vmmc { u-boot,dm-spl; }; @@ -122,10 +126,14 @@ &usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; }; &wdog1 { diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi new file mode 100644 index 00000000000..44af6637271 --- /dev/null +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + +&usdhc1 { + mmc-hs400-1_8v; +}; + +&usdhc2 { + sd-uhs-sdr104; + sd-uhs-ddr50; +}; diff --git a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi new file mode 100644 index 00000000000..4712cf6a445 --- /dev/null +++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts b/arch/arm/dts/imx8qm-rom7720-a1.dts index 5f9ac955ed4..d1f2fff869f 100644 --- a/arch/arm/dts/imx8qm-rom7720-a1.dts +++ b/arch/arm/dts/imx8qm-rom7720-a1.dts @@ -293,7 +293,7 @@ &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy0>; fsl,ar8031-phy-fixup; fsl,magic-packet; @@ -318,7 +318,7 @@ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec2>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy1>; fsl,ar8031-phy-fixup; fsl,magic-packet; diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 4bb7c469215..600a1108cec 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -303,10 +303,11 @@ static int confirm_close(void) static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + int confirmed = argc >= 2 && !strcmp(argv[1], "-y"); int err; u16 lc; - if (!confirm_close()) + if (!confirmed && !confirm_close()) return -EACCES; err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index aba9461d920..6a1bad855eb 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -916,7 +916,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) } if (5 == i) { - printf("Fail to set rate to %dkhz", freq); + printf("Fail to set rate to %u kHz", freq); return; } } @@ -936,7 +936,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) } if (best == 0) { - printf("Fail to set rate to %dkhz", freq); + printf("Fail to set rate to %u kHz", freq); return; } @@ -1115,17 +1115,17 @@ int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, printf("\n"); - printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); - printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); + printf("IPG %8u kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); + printf("UART %8u kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); #ifdef CONFIG_MXC_SPI - printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); + printf("CSPI %8u kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); #endif - printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); - printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); - printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); - printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); - printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); - printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); + printf("AHB %8u kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); + printf("AXI %8u kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); + printf("DDR %8u kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); + printf("USDHC1 %8u kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); + printf("USDHC2 %8u kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); + printf("USDHC3 %8u kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); return 0; } diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 0d343da519f..9a176f47118 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -575,12 +575,6 @@ int board_late_init(void) return 0; } -int checkboard(void) -{ - puts("Board: MX6-SabreSD\n"); - return 0; -} - #ifdef CONFIG_SPL_BUILD #include <asm/arch/mx6-ddr.h> #include <spl.h> diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 4754647fb4a..3ea9425fd1e 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -47,6 +47,10 @@ DECLARE_GLOBAL_DATA_PTR; #define VPD_PRODUCT_B650 2 #define VPD_PRODUCT_B450 3 +#define AR8033_DBG_REG_ADDR 0x1d +#define AR8033_DBG_REG_DATA 0x1e +#define AR8033_SERDES_REG 0x5 + static int productid; /* Default to generic. */ static struct vpd_cache vpd; @@ -61,31 +65,16 @@ int dram_init(void) return 0; } -static int mx6_rgmii_rework(struct phy_device *phydev) -{ - /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ - /* set device address 0x7 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - /* offset 0x8016: CLK_25M Clock Select */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - /* enable register write, no post increment, address 0x7 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - /* set to 125 MHz from local PLL source */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18); - - /* rgmii tx clock delay enable */ - /* set debug port address: SerDes Test and System Mode Control */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - /* enable rgmii tx clock delay */ - /* set the reserved bits to avoid board specific voltage peak issue*/ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); - - return 0; -} - int board_phy_config(struct phy_device *phydev) { - mx6_rgmii_rework(phydev); + /* + * Set reserved bits to avoid board specific voltage peak issue. The + * value is a magic number provided directly by Qualcomm. Note, that + * PHY driver will take control of BIT(8) in this register to control + * TX clock delay, so we do not initialize that bit here. + */ + phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_ADDR, AR8033_SERDES_REG); + phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_DATA, 0x3c47); if (phydev->drv->config) phydev->drv->config(phydev); @@ -356,15 +345,12 @@ static void process_vpd(struct vpd_cache *vpd) switch (vpd->product_id) { case VPD_PRODUCT_B450: - env_set("confidx", "1"); i210_index = 1; break; case VPD_PRODUCT_B650: - env_set("confidx", "2"); i210_index = 1; break; case VPD_PRODUCT_B850: - env_set("confidx", "3"); i210_index = 2; break; } @@ -554,16 +540,23 @@ int ft_board_setup(void *blob, struct bd_info *bd) int board_fit_config_name_match(const char *name) { + const char *machine = name; + if (!vpd.is_read) return strcmp(name, "imx6q-bx50v3"); + if (!strncmp(machine, "Boot ", 5)) + machine += 5; + if (!strncmp(machine, "imx6q-", 6)) + machine += 6; + switch (vpd.product_id) { case VPD_PRODUCT_B450: - return strcmp(name, "imx6q-b450v3"); + return strcasecmp(machine, "b450v3"); case VPD_PRODUCT_B650: - return strcmp(name, "imx6q-b650v3"); + return strcasecmp(machine, "b650v3"); case VPD_PRODUCT_B850: - return strcmp(name, "imx6q-b850v3"); + return strcasecmp(machine, "b850v3"); default: return -1; } diff --git a/board/toradex/apalis-imx8x/MAINTAINERS b/board/toradex/apalis-imx8x/MAINTAINERS index fbf93799315..52721544476 100644 --- a/board/toradex/apalis-imx8x/MAINTAINERS +++ b/board/toradex/apalis-imx8x/MAINTAINERS @@ -1,5 +1,5 @@ Apalis iMX8X -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: http://developer.toradex.com/software/linux/linux-software S: Maintained F: arch/arm/dts/fsl-imx8x-apalis.dts diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS index 4a2707e771b..fde4d92dc3d 100644 --- a/board/toradex/apalis_imx6/MAINTAINERS +++ b/board/toradex/apalis_imx6/MAINTAINERS @@ -1,5 +1,5 @@ Apalis iMX6 -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS index 4107d29876b..899b1ff555c 100644 --- a/board/toradex/colibri-imx6ull/MAINTAINERS +++ b/board/toradex/colibri-imx6ull/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX6ULL -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS index 76f9446bbad..2cbf65433da 100644 --- a/board/toradex/colibri_imx6/MAINTAINERS +++ b/board/toradex/colibri_imx6/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX6 -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS index 61a504487a3..3d7d010d8a6 100644 --- a/board/toradex/colibri_imx7/MAINTAINERS +++ b/board/toradex/colibri_imx7/MAINTAINERS @@ -1,5 +1,5 @@ Colibri iMX7 -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS index 2a8e6fb74b7..61fbd2c1e0d 100644 --- a/board/toradex/colibri_t20/MAINTAINERS +++ b/board/toradex/colibri_t20/MAINTAINERS @@ -1,5 +1,5 @@ COLIBRI_T20 -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> S: Maintained F: board/toradex/colibri_t20/ F: include/configs/colibri_t20.h diff --git a/board/toradex/colibri_t30/MAINTAINERS b/board/toradex/colibri_t30/MAINTAINERS index 00c03c89b88..ded9e28295f 100644 --- a/board/toradex/colibri_t30/MAINTAINERS +++ b/board/toradex/colibri_t30/MAINTAINERS @@ -1,5 +1,5 @@ Colibri T30 -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> S: Maintained F: board/toradex/colibri_t30/ F: include/configs/colibri_t30.h diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index f94cc0fbe2a..c6627654a25 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -1,5 +1,5 @@ Colibri VFxx -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/verdin-imx8mm/MAINTAINERS b/board/toradex/verdin-imx8mm/MAINTAINERS index 2495696e9d8..08c370178cc 100644 --- a/board/toradex/verdin-imx8mm/MAINTAINERS +++ b/board/toradex/verdin-imx8mm/MAINTAINERS @@ -1,5 +1,5 @@ Verdin iMX8M Mini -M: Igor Opaniuk <igor.opaniuk@toradex.com> +M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini S: Maintained F: arch/arm/dts/imx8mm-verdin.dts diff --git a/board/variscite/dart_6ul/dart_6ul.c b/board/variscite/dart_6ul/dart_6ul.c index d8e383d323e..360be758bb2 100644 --- a/board/variscite/dart_6ul/dart_6ul.c +++ b/board/variscite/dart_6ul/dart_6ul.c @@ -12,8 +12,11 @@ #include <asm/arch/sys_proto.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/mxc_i2c.h> +#include <dm.h> #include <fsl_esdhc_imx.h> +#include <i2c_eeprom.h> #include <linux/bitops.h> +#include <malloc.h> #include <miiphy.h> #include <netdev.h> #include <usb.h> @@ -222,9 +225,108 @@ int board_init(void) return 0; } +/* length of strings stored in the eeprom */ +#define DART6UL_PN_LEN 16 +#define DART6UL_ASSY_LEN 16 +#define DART6UL_DATE_LEN 12 + +/* eeprom content, 512 bytes */ +struct dart6ul_info { + u32 magic; + u8 partnumber[DART6UL_PN_LEN]; + u8 assy[DART6UL_ASSY_LEN]; + u8 date[DART6UL_DATE_LEN]; + u32 custom_addr_val[32]; + struct cmd { + u8 addr; + u8 index; + } custom_cmd[150]; + u8 res[33]; + u8 som_info; + u8 ddr_size; + u8 crc; +} __attribute__ ((__packed__)); + +#define DART6UL_INFO_STORAGE_GET(n) ((n) & 0x3) +#define DART6UL_INFO_WIFI_GET(n) ((n) >> 2 & 0x1) +#define DART6UL_INFO_REV_GET(n) ((n) >> 3 & 0x3) +#define DART6UL_DDRSIZE_IN_MIB(n) ((n) << 8) +#define DART6UL_INFO_MAGIC 0x32524156 + +static const char *som_info_storage_to_str(u8 som_info) +{ + switch (DART6UL_INFO_STORAGE_GET(som_info)) { + case 0x0: return "none (SD only)"; + case 0x1: return "NAND"; + case 0x2: return "eMMC"; + default: return "unknown"; + } +} + +static const char *som_info_rev_to_str(u8 som_info) +{ + switch (DART6UL_INFO_REV_GET(som_info)) { + case 0x0: return "2.4G"; + case 0x1: return "5G"; + default: return "unknown"; + } +} + int checkboard(void) { - puts("Board: Variscite DART-6UL Evaluation Kit\n"); + const char *path = "eeprom0"; + struct dart6ul_info *info; + struct udevice *dev; + int ret, off; + + off = fdt_path_offset(gd->fdt_blob, path); + if (off < 0) { + printf("%s: fdt_path_offset() failed: %d\n", __func__, off); + return off; + } + + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); + if (ret) { + printf("%s: uclass_get_device_by_of_offset() failed: %d\n", __func__, ret); + return ret; + } + + info = malloc(sizeof(struct dart6ul_info)); + if (!info) + return -ENOMEM; + + ret = i2c_eeprom_read(dev, 0, (uint8_t *)info, + sizeof(struct dart6ul_info)); + if (ret) { + printf("%s: i2c_eeprom_read() failed: %d\n", __func__, ret); + free(info); + return ret; + } + + if (info->magic != DART6UL_INFO_MAGIC) { + printf("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n", + info->magic, DART6UL_INFO_MAGIC); + /* do not fail if the content is invalid */ + free(info); + return 0; + } + + /* make sure strings are null terminated */ + info->partnumber[DART6UL_PN_LEN - 1] = '\0'; + info->assy[DART6UL_ASSY_LEN - 1] = '\0'; + info->date[DART6UL_DATE_LEN - 1] = '\0'; + + printf("Board: PN: %s, Assy: %s, Date: %s\n" + " Storage: %s, Wifi: %s, DDR: %d MiB, Rev: %s\n", + info->partnumber, + info->assy, + info->date, + som_info_storage_to_str(info->som_info), + DART6UL_INFO_WIFI_GET(info->som_info) ? "yes" : "no", + DART6UL_DDRSIZE_IN_MIB(info->ddr_size), + som_info_rev_to_str(info->som_info)); + + free(info); return 0; } diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index c5d331f617a..49d54530787 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -70,6 +70,13 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 91d3bc3ac94..1aef1ab40d1 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -66,6 +66,10 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 22e5f5aeeaa..41889c46242 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -65,6 +65,10 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHYLIB=y CONFIG_DM_ETH=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index cd5724e811a..6166d103e32 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 CONFIG_SYS_I2C_MXC_I2C1=y @@ -70,6 +70,9 @@ CONFIG_LED_GPIO=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHYLIB=y CONFIG_DM_ETH=y diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index 5f94cea5ddc..721882567de 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -36,6 +36,8 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MXC=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_PHYLIB=y diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 7609594bd01..d486dab0439 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -954,7 +954,7 @@ static int mxc_i2c_probe(struct udevice *bus) !dm_gpio_is_valid(&i2c_bus->scl_gpio) || ret || ret2) { dev_err(bus, - "i2c bus %d at %lu, fail to request scl/sda gpio\n", + "i2c bus %d at 0x%2lx, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base); return -EINVAL; } diff --git a/include/compiler.h b/include/compiler.h index 90b7afae537..27b9843497a 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -6,6 +6,7 @@ #define __COMPILER_H__ #include <stddef.h> +#include <stdbool.h> #ifdef USE_HOSTCC @@ -150,4 +151,12 @@ typedef unsigned long int uintptr_t; #define MEM_SUPPORT_64BIT_DATA 0 #endif +static inline bool host_build(void) { +#ifdef USE_HOSTCC + return true; +#else + return false; +#endif +} + #endif diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index e5c580b3f91..2d854af9a06 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -62,7 +62,7 @@ "networkboot=" \ "run setnetworkboot; " \ "nfs ${loadaddr} /srv/nfs/fitImage; " \ - "bootm ${loadaddr}#conf@${confidx}\0" \ + "bootm ${loadaddr}\0" \ #define CONFIG_NETWORKBOOTCOMMAND \ "run networkboot; " \ @@ -111,7 +111,7 @@ "doboot=" \ "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ "run setargs; " \ - "bootm ${loadaddr}#conf@${confidx}\0" \ + "bootm ${loadaddr}\0" \ "tryboot=" \ "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ "run loadimage || run swappartitions && run loadimage || " \ diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index 07e6c686f3e..e63a5530aed 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -248,6 +248,32 @@ #define IMX8MM_CLK_SNVS_ROOT 228 #define IMX8MM_CLK_GIC 229 -#define IMX8MM_CLK_END 230 +#define IMX8MM_SYS_PLL1_40M_CG 230 +#define IMX8MM_SYS_PLL1_80M_CG 231 +#define IMX8MM_SYS_PLL1_100M_CG 232 +#define IMX8MM_SYS_PLL1_133M_CG 233 +#define IMX8MM_SYS_PLL1_160M_CG 234 +#define IMX8MM_SYS_PLL1_200M_CG 235 +#define IMX8MM_SYS_PLL1_266M_CG 236 +#define IMX8MM_SYS_PLL1_400M_CG 237 +#define IMX8MM_SYS_PLL2_50M_CG 238 +#define IMX8MM_SYS_PLL2_100M_CG 239 +#define IMX8MM_SYS_PLL2_125M_CG 240 +#define IMX8MM_SYS_PLL2_166M_CG 241 +#define IMX8MM_SYS_PLL2_200M_CG 242 +#define IMX8MM_SYS_PLL2_250M_CG 243 +#define IMX8MM_SYS_PLL2_333M_CG 244 +#define IMX8MM_SYS_PLL2_500M_CG 245 + +#define IMX8MM_CLK_M4_CORE 246 +#define IMX8MM_CLK_VPU_CORE 247 +#define IMX8MM_CLK_GPU3D_CORE 248 +#define IMX8MM_CLK_GPU2D_CORE 249 + +#define IMX8MM_CLK_CLKO2 250 + +#define IMX8MM_CLK_A53_CORE 251 + +#define IMX8MM_CLK_END 252 #endif |