diff options
| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2020-04-28 10:19:28 +0800 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-04-28 17:46:46 +0530 |
| commit | 6ebd48835f2d9f6f70118c77493fdb597b95a40e (patch) | |
| tree | b3ec0993091b2f35887fc0e88f6400c4ad1d0cad | |
| parent | 35ad8f7af4ec7a2e449322c86c5301c48765a269 (diff) | |
fsl-layerscape: Add RESV_RAM check in resv_ram addr
The initialization of gd->arch.resv_ram pointer should depend on if the
RESV_RAM config is enabled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index b443894453..1b7729c046 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1379,7 +1379,7 @@ static int tfa_dram_init_banksize(void) if (i > 0) ret = 0; -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bd->bi_dram[2].size >= @@ -1402,7 +1402,7 @@ static int tfa_dram_init_banksize(void) board_reserve_ram_top(gd->bd->bi_dram[0].size); } } -#endif /* CONFIG_FSL_MC_ENET */ +#endif /* CONFIG_RESV_RAM */ return ret; } @@ -1465,7 +1465,7 @@ int dram_init_banksize(void) } #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bd->bi_dram[2].size >= @@ -1488,7 +1488,7 @@ int dram_init_banksize(void) board_reserve_ram_top(gd->bd->bi_dram[0].size); } } -#endif /* CONFIG_FSL_MC_ENET */ +#endif /* CONFIG_RESV_RAM */ #ifdef CONFIG_SYS_DP_DDR_BASE_PHY #ifdef CONFIG_SYS_DDR_BLOCK3_BASE |