diff options
author | Ye Li <ye.li@nxp.com> | 2018-04-18 03:20:03 -0700 |
---|---|---|
committer | Ye Li <ye.li@nxp.com> | 2018-04-27 06:14:41 -0700 |
commit | e10f585e344fe0b4b8c20bd201a0941cad3452cb (patch) | |
tree | f35e1ce5ff0bda52e80e0903c7f2c66b4d9b6504 | |
parent | 0ea7a0c3075c6766b431bfb04c597665a266d0b9 (diff) |
MLK-18161-7 imx8qxp_arm2: Add i.MX8QXP ARM2 board support
Add board level codes and configs for i.MX8QXP LPDDR4 ARM2 board
and i.MX8QXP DDR3 ARM2 board.
- Enabled DM driver:
FEC, LPUART, LPI2C, GPIO, SD/MMC, FSPI, PCA953X, pinctrl, USB host(EHCI/XHCI)
Power-domain, SC thermal
- Enabled Non-DM driver:
PCIE, fuse, iomux, video(IMXDPUV1), USB device(CI-UDC)
- Disabled driver:
mailbox
- Board defconfigs:
imx8qxp_ddr3_arm2_defconfig
imx8qxp_lpddr4_arm2_fspi_defconfig
imx8qxp_ddr4_arm2_defconfig
Signed-off-by: Ye Li <ye.li@nxp.com>
-rw-r--r-- | arch/arm/mach-imx/imx8/Kconfig | 11 | ||||
-rw-r--r-- | board/freescale/imx8qxp_arm2/Kconfig | 12 | ||||
-rw-r--r-- | board/freescale/imx8qxp_arm2/Makefile | 7 | ||||
-rw-r--r-- | board/freescale/imx8qxp_arm2/imx8qxp_arm2.c | 520 | ||||
-rw-r--r-- | configs/imx8qxp_ddr3_arm2_defconfig | 75 | ||||
-rw-r--r-- | configs/imx8qxp_lpddr4_arm2_defconfig | 75 | ||||
-rw-r--r-- | configs/imx8qxp_lpddr4_arm2_fspi_defconfig | 76 | ||||
-rw-r--r-- | include/configs/imx8qxp_arm2.h | 301 |
8 files changed, 1077 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 9a93342ba56..b1d5676e9e9 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -39,6 +39,17 @@ config TARGET_IMX8QM_DDR4_ARM2 select BOARD_LATE_INIT select IMX8QM +config TARGET_IMX8QXP_LPDDR4_ARM2 + bool "Support i.MX8QXP lpddr4 validation board" + select BOARD_LATE_INIT + select IMX8QXP + +config TARGET_IMX8QXP_DDR3_ARM2 + bool "Support i.MX8QXP ddr3 validation board" + select BOARD_LATE_INIT + select IMX8QXP + endchoice source "board/freescale/imx8qm_arm2/Kconfig" +source "board/freescale/imx8qxp_arm2/Kconfig" endif diff --git a/board/freescale/imx8qxp_arm2/Kconfig b/board/freescale/imx8qxp_arm2/Kconfig new file mode 100644 index 00000000000..64a93c487fe --- /dev/null +++ b/board/freescale/imx8qxp_arm2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8QXP_LPDDR4_ARM2 || TARGET_IMX8QXP_DDR3_ARM2 + +config SYS_BOARD + default "imx8qxp_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qxp_arm2" + +endif diff --git a/board/freescale/imx8qxp_arm2/Makefile b/board/freescale/imx8qxp_arm2/Makefile new file mode 100644 index 00000000000..d947c6bfa53 --- /dev/null +++ b/board/freescale/imx8qxp_arm2/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qxp_arm2.o diff --git a/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c new file mode 100644 index 00000000000..967fc5a7ca5 --- /dev/null +++ b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c @@ -0,0 +1,520 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <fsl_ifc.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <environment.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include "pca953x.h" + +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/mach-imx/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <dm.h> +#include <imx8_hsio.h> +#include <usb.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/video.h> +#include <asm/arch/video_common.h> +#include <power-domain.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_ipc_t ipcHndl = 0; + sc_err_t sciErr = 0; + + ipcHndl = gd->arch.ipc_channel_handle; + + /* Power up UART0 */ + sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_0, 2, &rate); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Enable UART0 clock root */ + sciErr = sc_pm_clock_enable(ipcHndl, SC_R_UART_0, 2, true, false); + if (sciErr != SC_ERR_NONE) + return 0; + + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 22) + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc1_sd[] = { + SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for WP */ + SC_P_USDHC1_CD_B | MUX_MODE_ALT(4) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for CD, GPIO4 IO22 */ + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + struct power_domain pd; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + if (!power_domain_lookup_name("conn_sdhc0", &pd)) + power_domain_on(&pd); + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + if (!power_domain_lookup_name("conn_sdhc1", &pd)) + power_domain_on(&pd); + imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd)); + init_clk_usdhc(1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC1_CD_GPIO, "sd1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; /* eMMC */ + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC */ + + +#ifdef CONFIG_FEC_MXC +#include <miiphy.h> + +static iomux_cfg_t pad_enet1[] = { + SC_P_SPDIF0_TX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_SPDIF0_RX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX3_RX2 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX2_RX3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_SCKR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_SCKT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_FSR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + if (0 == CONFIG_FEC_ENET_DEV) + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); + else + imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1)); +} + +static void enet_device_phy_reset(void) +{ + struct gpio_desc desc_enet0; + struct gpio_desc desc_enet1; + int ret; + + ret = dm_gpio_lookup_name("gpio@18_1", &desc_enet0); + if (ret) + return; + + ret = dm_gpio_request(&desc_enet0, "enet0_reset"); + if (ret) + return; + + ret = dm_gpio_lookup_name("gpio@18_4", &desc_enet1); + if (ret) + return; + + ret = dm_gpio_request(&desc_enet1, "enet1_reset"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc_enet0, GPIOD_IS_OUT); + dm_gpio_set_value(&desc_enet0, 0); + udelay(50); + dm_gpio_set_value(&desc_enet0, 1); + + dm_gpio_set_dir_flags(&desc_enet1, GPIOD_IS_OUT); + dm_gpio_set_value(&desc_enet1, 0); + udelay(50); + dm_gpio_set_value(&desc_enet1, 1); + + /* The board has a long delay for this reset to become stable */ + mdelay(200); +} + +int board_eth_init(bd_t *bis) +{ + int ret; + struct power_domain pd; + + printf("[%s] %d\n", __func__, __LINE__); + + if (CONFIG_FEC_ENET_DEV) { + if (!power_domain_lookup_name("conn_enet1", &pd)) + power_domain_on(&pd); + } else { + if (!power_domain_lookup_name("conn_enet0", &pd)) + power_domain_on(&pd); + } + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} + +int board_phy_config(struct phy_device *phydev) +{ +#ifdef CONFIG_FEC_ENABLE_MAX7322 + uint8_t value; + + /* This is needed to drive the pads to 1.8V instead of 1.5V */ + i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS); + + if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) { + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1)) + printf("MAX7322 write failed\n"); + } else { + printf("MAX7322 Not found\n"); + } + mdelay(1); +#endif + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +static int setup_fec(int ind) +{ + /* Reset ENET PHY */ + enet_device_phy_reset(); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_GPIO + +#define DEBUG_LED IMX_GPIO_NR(3, 23) +#define IOEXP_RESET IMX_GPIO_NR(0, 19) +#define BB_PWR_EN IMX_GPIO_NR(5, 9) + +static iomux_cfg_t board_gpios[] = { + SC_P_QSPI0B_SS0_B | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_MCLK_IN0 | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static void board_gpio_init(void) +{ + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios)); + + gpio_request(DEBUG_LED, "debug_led"); + gpio_direction_output(DEBUG_LED, 1); + + /* enable i2c port expander assert reset line */ + gpio_request(IOEXP_RESET, "ioexp_rst"); + gpio_direction_output(IOEXP_RESET, 1); + + /* Enable base board 1.8V power */ + gpio_request(BB_PWR_EN, "bb_pwr_en"); + gpio_direction_output(BB_PWR_EN, 1); +} +#endif + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_IMX8QXP_DDR3_ARM2 + puts("Board: iMX8QXP DDR3 ARM2\n"); +#else + puts("Board: iMX8QXP LPDDR4 ARM2\n"); +#endif + + print_bootinfo(); + + /* Note: After reloc, ipcHndl will no longer be valid. If handle + * returned by sc_ipc_open matches SC_IPC_CH, use this + * macro (valid after reloc) for subsequent SCI calls. + */ + if (gd->arch.ipc_channel_handle != SC_IPC_CH) + printf("\nSCI error! Invalid handle\n"); + + return 0; +} + +#ifdef CONFIG_FSL_HSIO + +#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT)) +static iomux_cfg_t board_pcie_pins[] = { + SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), + SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), + SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL), +}; + +static void imx8qxp_hsio_initialize(void) +{ + struct power_domain pd; + int ret; + + if (!power_domain_lookup_name("hsio_pcie1", &pd)) { + ret = power_domain_on(&pd); + if (ret) + printf("hsio_pcie1 Power up failed! (error = %d)\n", ret); + } + + imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins)); +} + +void pci_init_board(void) +{ + imx8qxp_hsio_initialize(); + + /* test the 1 lane mode of the PCIe A controller */ + mx8qxp_pcie_init(); +} + +#endif + +int board_init(void) +{ +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + puts("SCI reboot request"); + sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD); + while (1) + putc('.'); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "ARM2"); + env_set("board_rev", "iMX8QXP"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +#if defined(CONFIG_VIDEO_IMXDPUV1) +static void enable_lvds(struct display_info_t const *dev) +{ + display_controller_setup((PS2KHZ(dev->mode.pixclock) * 1000)); + lvds_soc_setup(dev->bus, (PS2KHZ(dev->mode.pixclock) * 1000)); + lvds_configure(dev->bus); + lvds2hdmi_setup(13); +} + +struct display_info_t const displays[] = {{ + .bus = 0, /* LVDS0 */ + .addr = 0, /* LVDS0 */ + .pixfmt = IMXDPUV1_PIX_FMT_BGRA32, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "IT6263", /* 720P60 */ + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = 13468, /* 74250000 */ + .left_margin = 110, + .right_margin = 220, + .upper_margin = 5, + .lower_margin = 20, + .hsync_len = 40, + .vsync_len = 5, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +#endif /* CONFIG_VIDEO_IMXDPUV1 */ diff --git a/configs/imx8qxp_ddr3_arm2_defconfig b/configs/imx8qxp_ddr3_arm2_defconfig new file mode 100644 index 00000000000..5672fcad295 --- /dev/null +++ b/configs/imx8qxp_ddr3_arm2_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" +CONFIG_TARGET_IMX8QXP_DDR3_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y diff --git a/configs/imx8qxp_lpddr4_arm2_defconfig b/configs/imx8qxp_lpddr4_arm2_defconfig new file mode 100644 index 00000000000..259ba1f4a34 --- /dev/null +++ b/configs/imx8qxp_lpddr4_arm2_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" +CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_MMC=y diff --git a/configs/imx8qxp_lpddr4_arm2_fspi_defconfig b/configs/imx8qxp_lpddr4_arm2_fspi_defconfig new file mode 100644 index 00000000000..2cacda7699d --- /dev/null +++ b/configs/imx8qxp_lpddr4_arm2_fspi_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2" +CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_CMD_IMPORTENV=n +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_CMD_CACHE=y + +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_OF_CONTROL=y +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_CMD_I2C=y + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y + +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y + +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_QSPI_BOOT=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_4BYTES_ADDR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y + +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_VIDEO=y + +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_ENV_IS_IN_SPI_FLASH=y diff --git a/include/configs/imx8qxp_arm2.h b/include/configs/imx8qxp_arm2.h new file mode 100644 index 00000000000..d15a20cdd3d --- /dev/null +++ b/include/configs/imx8qxp_arm2.h @@ -0,0 +1,301 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8QXP_ARM2_H +#define __IMX8QXP_ARM2_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_MISC_INIT + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + + +#define CONFIG_FSL_HSIO +#ifdef CONFIG_FSL_HSIO +#define CONFIG_PCIE_IMX8X +#define CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* FUSE command */ +#define CONFIG_CMD_FUSE + +/* GPIO configs */ +#define CONFIG_MXC_GPIO + +/* ENET Config */ +#define CONFIG_MII + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board and MUX with ESAI, default is ESAI */ +#define CONFIG_FEC_ENET_DEV 0 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE 0x5B040000 +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE 0x5B050000 +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_ENABLE_MAX7322 +#define CONFIG_ETHPRIME "eth1" +#endif + +/* ENET0 MDIO are shared */ +#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000 + +#define CONFIG_LIB_RAND +#define CONFIG_NET_RANDOM_ETHADDR + +/* MAX7322 */ +#ifdef CONFIG_FEC_ENABLE_MAX7322 +#define CONFIG_MAX7322_I2C_ADDR 0x68 +#define CONFIG_MAX7322_I2C_BUS 0 /* I2C1 */ +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=fsl-imx8qxp-lpddr4-arm2.dtb\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + + +/* Default environment is in SD */ +#define CONFIG_ENV_SIZE 0x1000 + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024) +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#else +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board + */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 3 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#ifdef CONFIG_TARGET_IMX8QXP_DDR3_ARM2 +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ +/* LPDDR4 board total DDR is 3GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 +#else +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +/* LPDDR4 board total DDR is 3GB */ +#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ +#endif + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#endif + +#define CONFIG_IMX_SMMU + +/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ +#ifdef CONFIG_FSL_FSPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_FSPI_FLASH_SIZE SZ_64M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x5d120000 +#define FSPI0_AMBA_BASE 0 +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +/* USB Config */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif +#endif /* CONFIG_CMD_USB */ + +#ifdef CONFIG_USB_GADGET +#define CONFIG_USBD_HS +#endif + +/* Framebuffer */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IMXDPUV1 +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +#define CONFIG_OF_SYSTEM_SETUP +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000 +#define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */ + +#endif /* __IMX8QXP_ARM2_H */ |