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authorJens Kuske <jenskuske@gmail.com>2015-12-10 11:41:02 +0100
committerHans de Goede <hdegoede@redhat.com>2015-12-10 15:45:48 +0100
commitbb3654629a6b2ab131de96489f70421f6a848c70 (patch)
tree9346a62ad1cfab5cb9566cdad9e4edaea25bfe3e
parent23baf66f2594fa4777fc9ec5f6c33d21b8151b69 (diff)
sunxi: Fix H3 DRAM DQ read delay configuration
The read delays were set incorrectly, leading to reliability issues at higher DRAM clock speeds. This commit adjusts this to match the vendor boot0 behaviour. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
-rw-r--r--arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c
index b721d6011a..2020d75fd1 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c
@@ -73,10 +73,10 @@ static void mctl_dq_delay(u32 read, u32 write)
for (i = 0; i < 4; i++) {
val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
- DATX_IOCR_READ_DELAY((read >> (i * 4)) & 0xf);
+ DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
- setbits_le32(&mctl_ctl->datx[i].iocr[j], val);
+ writel(val, &mctl_ctl->datx[i].iocr[j]);
}
clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
@@ -85,8 +85,8 @@ static void mctl_dq_delay(u32 read, u32 write)
val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
- setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQS], val);
- setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN], val);
+ writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]);
+ writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]);
}
setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
@@ -436,8 +436,8 @@ unsigned long sunxi_dram_init(void)
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
struct dram_para para = {
- .read_delays = 0x00007979,
- .write_delays = 0x6aaa0000,
+ .read_delays = 0x00007979, /* dram_tpr12 */
+ .write_delays = 0x6aaa0000, /* dram_tpr11 */
.dual_rank = 0,
.bus_width = 32,
.row_bits = 15,