Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.1 Zynq: - Add support for Syzygy and cc108 boards - Add support for mini u-boot configurations (cse) - dts updates - config/defconfig updates in connection to Kconfig changes - Fix psu_init handling ZynqMP: - SPL fixes - Remove slcr.c - Fixing r5 startup sequence - Add support for external pmufw - Add support for new ZynqMP chips - dts updates - Add support for zcu102 rev1.0 board Drivers: - nand: Support external timing setting and board init - ahci: Fix wording - axi_emac: Wait for bit, non processor mode, readl/write conversion - zynq_gem: Fix SGMII/PCS support
author: Tom Rini <trini@konsulko.com> 2017-11-29 08:26:07 -0500
committer: Tom Rini <trini@konsulko.com> 2017-11-29 08:26:07 -0500
commit: b06c46de632c55f4c39d404c6f0f65e414b31050 (patch)
tree: dea1702529c8d33c5e70eb5eb6ecf7d08eed23b9
parent: fcc8250c2f7c982f3593a8eecf737f8e2c95f222 (diff)
parent: a04a5daae25a74ad2ac90b66667dac126242baa0 (diff)
104 files changed, 3013 insertions, 2358 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ca386decfe..e50ba930a1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -738,7 +738,7 @@ config ARCH_VF610
 	imply NAND
 
 config ARCH_ZYNQ
-	bool "Xilinx Zynq Platform"
+	bool "Xilinx Zynq based platform"
 	select BOARD_LATE_INIT
 	select CPU_V7
 	select SUPPORT_SPL
@@ -764,7 +764,7 @@ config ARCH_ZYNQ
 	imply CMD_SPL
 
 config ARCH_ZYNQMP
-	bool "Support Xilinx ZynqMP Platform"
+	bool "Xilinx ZynqMP based platform"
 	select ARM64
 	select BOARD_LATE_INIT
 	select DM
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 5ffc9f6c86..3f922b4097 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -42,6 +42,13 @@ config SYS_CONFIG_NAME
 	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
 	  will be used for board configuration.
 
+config SYS_MEM_RSVD_FOR_MMU
+	bool "Reserve memory for MMU Table"
+	help
+	  If defined this option is used to setup different space for
+	  MMU table than the one which will be allocated during
+	  relocation.
+
 config BOOT_INIT_FILE
 	string "boot.bin init register filename"
 	depends on SPL
@@ -50,6 +57,14 @@ config BOOT_INIT_FILE
 	  Add register writes to boot.bin format (max 256 pairs).
 	  Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
 
+config PMUFW_INIT_FILE
+	string "PMU firmware"
+	depends on SPL
+	default ""
+	help
+	  Include external PMUFW (Platform Management Unit FirmWare) to
+	  a Xilinx bootable image (boot.bin).
+
 config ZYNQMP_USB
 	bool "Configure ZynqMP USB"
 
@@ -58,6 +73,7 @@ config SYS_MALLOC_F_LEN
 
 config DEFINE_TCM_OCM_MMAP
 	bool "Define TCM and OCM memory in MMU Table"
+	default y if MP
 	help
 	  This option if enabled defines the TCM and OCM memory and its
 	  memory attributes in MMU table entry.
@@ -86,6 +102,7 @@ config SPL_ZYNQMP_ALT_BOOTMODE
 	default 0x7 if USB_MODE
 	default 0xa if SW_USBHOST_MODE
 	default 0xb if SW_SATA_MODE
+	default 0xe if SD1_LSHFT_MODE
 
 choice
 	prompt "Boot mode"
@@ -122,6 +139,9 @@ config SW_USBHOST_MODE
 config SW_SATA_MODE
 	bool "SW SATA_MODE"
 
+config SD1_LSHFT_MODE
+	bool "SD1_LSHFT_MODE"
+
 endchoice
 
 endif
diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile
index 013f136707..72dee3ded4 100644
--- a/arch/arm/cpu/armv8/zynqmp/Makefile
+++ b/arch/arm/cpu/armv8/zynqmp/Makefile
@@ -8,5 +8,4 @@
 obj-y	+= clk.o
 obj-y	+= cpu.o
 obj-$(CONFIG_MP)	+= mp.o
-obj-y	+= slcr.o
 obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 1b5066a826..f026cb4511 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -77,6 +77,18 @@ u64 get_page_table_size(void)
 	return 0x14000;
 }
 
+#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
+int reserve_mmu(void)
+{
+	initialize_tcm(TCM_LOCK);
+	memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
+	gd->arch.tlb_size = PGTABLE_SIZE;
+	gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
+
+	return 0;
+}
+#endif
+
 static unsigned int zynqmp_get_silicon_version_secure(void)
 {
 	u32 ver;
@@ -198,7 +210,7 @@ int zynqmp_mmio_write(const u32 address,
 {
 	if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
 		return zynqmp_mmio_rawwrite(address, mask, value);
-	else if (!IS_ENABLED(CONFIG_SPL_BUILD))
+	else
 		return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask,
 				  value, 0, NULL);
 
@@ -215,7 +227,7 @@ int zynqmp_mmio_read(const u32 address, u32 *value)
 
 	if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 		ret = zynqmp_mmio_rawread(address, value);
-	} else if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+	} else {
 		ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0,
 				 0, ret_payload);
 		*value = ret_payload[1];
diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c
index 76f889ba7d..3ea24b4763 100644
--- a/arch/arm/cpu/armv8/zynqmp/mp.c
+++ b/arch/arm/cpu/armv8/zynqmp/mp.c
@@ -257,22 +257,36 @@ int cpu_release(int nr, int argc, char * const argv[])
 			boot_addr = ZYNQMP_R5_LOVEC_ADDR;
 		}
 
+		/*
+		 * Since we don't know where the user may have loaded the image
+		 * for an R5 we have to flush all the data cache to ensure
+		 * the R5 sees it.
+		 */
+		flush_dcache_all();
+
 		if (!strncmp(argv[1], "lockstep", 8)) {
 			printf("R5 lockstep mode\n");
+			set_r5_reset(LOCK);
 			set_r5_tcm_mode(LOCK);
 			set_r5_halt_mode(HALT, LOCK);
 			set_r5_start(boot_addr);
 			enable_clock_r5();
 			release_r5_reset(LOCK);
+			dcache_disable();
 			write_tcm_boot_trampoline(boot_addr_uniq);
+			dcache_enable();
 			set_r5_halt_mode(RELEASE, LOCK);
 		} else if (!strncmp(argv[1], "split", 5)) {
 			printf("R5 split mode\n");
+			set_r5_reset(SPLIT);
 			set_r5_tcm_mode(SPLIT);
 			set_r5_halt_mode(HALT, SPLIT);
+			set_r5_start(boot_addr);
 			enable_clock_r5();
 			release_r5_reset(SPLIT);
+			dcache_disable();
 			write_tcm_boot_trampoline(boot_addr_uniq);
+			dcache_enable();
 			set_r5_halt_mode(RELEASE, SPLIT);
 		} else {
 			printf("Unsupported mode\n");
diff --git a/arch/arm/cpu/armv8/zynqmp/slcr.c b/arch/arm/cpu/armv8/zynqmp/slcr.c
deleted file mode 100644
index 713e9a62c0..0000000000
--- a/arch/arm/cpu/armv8/zynqmp/slcr.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clk.h>
-
-/*
- * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
- *
- * @peri_name: Name of the peripheral for checking MIO status
- * @get_pins: Pointer to array of get pin for this peripheral
- * @num_pins: Number of pins for this peripheral
- * @mask: Mask value
- * @check_val: Required check value to get the status of  periph
- */
-struct zynq_slcr_mio_get_status {
-	const char *peri_name;
-	const int *get_pins;
-	int num_pins;
-	u32 mask;
-	u32 check_val;
-};
-
-static const struct zynq_slcr_mio_get_status mio_periphs[] = {
-};
-
-/*
- * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
- *
- * @periph: Name of the peripheral
- *
- * Returns count to indicate the number of pins configured for the
- * given @periph.
- */
-int zynq_slcr_get_mio_pin_status(const char *periph)
-{
-	const struct zynq_slcr_mio_get_status *mio_ptr;
-	int val, i, j;
-	int mio = 0;
-
-	for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
-		if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
-			mio_ptr = &mio_periphs[i];
-			for (j = 0; j < mio_ptr->num_pins; j++) {
-				val = readl(&slcr_base->mio_pin
-						[mio_ptr->get_pins[j]]);
-				if ((val & mio_ptr->mask) == mio_ptr->check_val)
-					mio++;
-			}
-			break;
-		}
-	}
-
-	return mio;
-}
diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c
index 468dc1dc4d..41b0070a5e 100644
--- a/arch/arm/cpu/armv8/zynqmp/spl.c
+++ b/arch/arm/cpu/armv8/zynqmp/spl.c
@@ -102,6 +102,11 @@ u32 spl_boot_device(void)
 	case SW_SATA_MODE:
 		return BOOT_DEVICE_SATA;
 #endif
+#ifdef CONFIG_SPL_SPI_SUPPORT
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		return BOOT_DEVICE_SPI;
+#endif
 	default:
 		printf("Invalid Boot Mode:0x%x\n", bootmode);
 		break;
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cd540e99ea..0d055e3abb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -124,24 +124,29 @@ dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \
 dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
 	uniphier-sld8-ref.dtb
 
-dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
-	zynq-zc706.dtb \
-	zynq-zed.dtb \
-	zynq-zybo.dtb \
+dtb-$(CONFIG_ARCH_ZYNQ) += \
+	zynq-cc108.dtb \
+	zynq-cse-qspi-single.dtb \
 	zynq-microzed.dtb \
 	zynq-picozed.dtb \
+	zynq-syzygy-hub.dtb \
 	zynq-topic-miami.dtb \
 	zynq-topic-miamilite.dtb \
 	zynq-topic-miamiplus.dtb \
-	zynq-zturn-myir.dtb \
+	zynq-zc702.dtb \
+	zynq-zc706.dtb \
 	zynq-zc770-xm010.dtb \
 	zynq-zc770-xm011.dtb \
 	zynq-zc770-xm012.dtb \
-	zynq-zc770-xm013.dtb
+	zynq-zc770-xm013.dtb \
+	zynq-zed.dtb \
+	zynq-zturn-myir.dtb \
+	zynq-zybo.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-ep108.dtb			\
 	zynqmp-zcu102-revA.dtb			\
 	zynqmp-zcu102-revB.dtb			\
+	zynqmp-zcu102-rev1.0.dtb		\
 	zynqmp-zc1751-xm015-dc1.dtb		\
 	zynqmp-zc1751-xm016-dc2.dtb		\
 	zynqmp-zc1751-xm018-dc4.dtb		\
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index f993e19ef2..d9774d85d1 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -105,10 +105,10 @@
 		gpio0: gpio@e000a000 {
 			compatible = "xlnx,zynq-gpio-1.0";
 			#gpio-cells = <2>;
-			#interrupt-cells = <2>;
 			clocks = <&clkc 42>;
 			gpio-controller;
 			interrupt-controller;
+			#interrupt-cells = <2>;
 			interrupt-parent = <&intc>;
 			interrupts = <0 20 4>;
 			reg = <0xe000a000 0x1000>;
diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts
new file mode 100644
index 0000000000..a55e82b210
--- /dev/null
+++ b/arch/arm/dts/zynq-cc108.dts
@@ -0,0 +1,116 @@
+/*
+ * Xilinx CC108 board DTS
+ *
+ * (C) Copyright 2007-2013 Xilinx, Inc.
+ * (C) Copyright 2007-2013 Michal Simek
+ * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+	compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
+	model = "Xilinx Zynq";
+
+	aliases {
+		ethernet0 = &gem0;
+		serial0 = &uart0;
+		spi0 = &qspi;
+	};
+
+	chosen {
+		bootargs = "";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x20000000>;
+	};
+
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+
+	usb_phy1: phy1 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@1 {
+		reg = <1>;
+		device_type = "ethernet-phy";
+	};
+};
+
+&qspi {
+	status = "okay";
+	is-dual = <0>;
+	num-cs = <1>;
+	flash@0 { /* 16 MB */
+		compatible = "n25q128a11";
+		reg = <0x0>;
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 {
+			label = "qspi-fsbl-uboot-bs";
+			reg = <0x0 0x400000>; /* 4MB */
+		};
+		partition@0x400000 {
+			label = "qspi-linux";
+			reg = <0x400000 0x400000>; /* 4MB */
+		};
+		partition@0x800000 {
+			label = "qspi-rootfs";
+			reg = <0x800000 0x400000>; /* 4MB */
+		};
+		partition@0xc00000 {
+			label = "qspi-devicetree";
+			reg = <0xc00000 0x100000>; /* 1MB */
+		};
+		partition@0xd00000 {
+			label = "qspi-scratch";
+			reg = <0xd00000 0x200000>; /* 2MB */
+		};
+		partition@0xf00000 {
+			label = "qspi-uboot-env";
+			reg = <0xf00000 0x100000>; /* 1MB */
+		};
+	};
+};
+
+&sdhci1 {
+	status = "okay";
+	broken-cd ;
+	wp-inverted ;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};
+
+&usb1 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy1>;
+};
diff --git a/arch/arm/dts/zynq-cse-qspi-single.dts b/arch/arm/dts/zynq-cse-qspi-single.dts
new file mode 100644
index 0000000000..bc08303d7a
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-single.dts
@@ -0,0 +1,13 @@
+/*
+ * Xilinx CSE QSPI single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+&qspi {
+	spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/zynq-cse-qspi.dtsi b/arch/arm/dts/zynq-cse-qspi.dtsi
new file mode 100644
index 0000000000..1c3736f1cd
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi.dtsi
@@ -0,0 +1,126 @@
+/*
+ * Xilinx CSE QSPI board DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Zynq CSE QSPI Board";
+	compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000";
+
+	aliases {
+		spi0 = &qspi;
+		serial0 = &dcc;
+	};
+
+	memory@fffc0000 {
+		device_type = "memory";
+		reg = <0xFFFC0000 0x40000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	dcc: dcc {
+		compatible = "arm,dcc";
+		status = "disabled";
+		u-boot,dm-pre-reloc;
+	};
+
+	amba: amba {
+		u-boot,dm-pre-reloc;
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&intc>;
+		ranges;
+
+		intc: interrupt-controller@f8f01000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0xF8F01000 0x1000>,
+			      <0xF8F00100 0x100>;
+		};
+
+		qspi: spi@e000d000 {
+			clock-names = "ref_clk", "pclk";
+			clocks = <&clkc 10>, <&clkc 43>;
+			compatible = "xlnx,zynq-qspi-1.0";
+			status = "okay";
+			interrupt-parent = <&intc>;
+			interrupts = <0 19 4>;
+			reg = <0xe000d000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			num-cs = <1>;
+			flash@0 {
+				compatible = "n25q128a11";
+				reg = <0x0>;
+				spi-tx-bus-width = <1>;
+				spi-rx-bus-width = <4>;
+				spi-max-frequency = <50000000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				partition@qspi-fsbl-uboot {
+					label = "qspi-fsbl-uboot";
+					reg = <0x0 0x100000>;
+				};
+				partition@qspi-linux {
+					label = "qspi-linux";
+					reg = <0x100000 0x500000>;
+				};
+				partition@qspi-device-tree {
+					label = "qspi-device-tree";
+					reg = <0x600000 0x20000>;
+				};
+				partition@qspi-rootfs {
+					label = "qspi-rootfs";
+					reg = <0x620000 0x5E0000>;
+				};
+				partition@qspi-bitstream {
+					label = "qspi-bitstream";
+					reg = <0xC00000 0x400000>;
+				};
+			};
+		};
+
+		slcr: slcr@f8000000 {
+			u-boot,dm-pre-reloc;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+			reg = <0xF8000000 0x1000>;
+			ranges;
+			clkc: clkc@100 {
+				#clock-cells = <1>;
+				compatible = "xlnx,ps7-clkc";
+				fclk-enable = <0xf>;
+				u-boot,dm-pre-reloc;
+				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+						"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+						"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+						"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+						"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+						"dma", "usb0_aper", "usb1_aper", "gem0_aper",
+						"gem1_aper", "sdio0_aper", "sdio1_aper",
+						"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+						"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+						"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+						"dbg_trc", "dbg_apb";
+				reg = <0x100 0x100>;
+			};
+		};
+	};
+
+};
+
+&dcc {
+	status = "okay";
+};
diff --git a/arch/arm/dts/zynq-syzygy-hub.dts b/arch/arm/dts/zynq-syzygy-hub.dts
new file mode 100644
index 0000000000..ebd08b4f40
--- /dev/null
+++ b/arch/arm/dts/zynq-syzygy-hub.dts
@@ -0,0 +1,72 @@
+/*
+ * SYZYGY Hub DTS
+ *
+ *  Copyright (C) 2011 - 2015 Xilinx
+ *  Copyright (C) 2017 Opal Kelly Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+	model = "SYZYGY Hub";
+	compatible = "opalkelly,syzygy-hub", "xlnx,zynq-7000";
+
+	aliases {
+		ethernet0 = &gem0;
+		serial0 = &uart0;
+		mmc0 = &sdhci0;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "";
+		stdout-path = "serial0:115200n8";
+	};
+
+	usb_phy0: phy0 {
+		#phy-cells = <0>;
+		compatible = "usb-nop-xceiv";
+		reset-gpios = <&gpio0 47 1>;
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <50000000>;
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@0 {
+		reg = <0>;
+		device_type = "ethernet-phy";
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&sdhci0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "otg";
+	usb-phy = <&usb_phy0>;
+};
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 2696e70a89..da698a19cc 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -96,6 +96,7 @@
 
 	ethernet_phy: ethernet-phy@7 {
 		reg = <7>;
+		device_type = "ethernet-phy";
 	};
 };
 
@@ -107,8 +108,11 @@
 &i2c0 {
 	status = "okay";
 	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c0_default>;
+	pinctrl-1 = <&pinctrl_i2c0_gpio>;
+	scl-gpios = <&gpio0 50 0>;
+	sda-gpios = <&gpio0 51 0>;
 
 	i2cswitch@74 {
 		compatible = "nxp,pca9548";
@@ -299,6 +303,19 @@
 		};
 	};
 
+	pinctrl_i2c0_gpio: i2c0-gpio {
+		mux {
+			groups = "gpio0_50_grp", "gpio0_51_grp";
+			function = "gpio0";
+		};
+
+		conf {
+			groups = "gpio0_50_grp", "gpio0_51_grp";
+			slew-rate = <0>;
+			io-standard = <1>;
+		};
+	};
+
 	pinctrl_sdhci0_default: sdhci0-default {
 		mux {
 			groups = "sdio0_2_grp";
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index 8b0177bc51..d342306293 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -50,6 +50,7 @@
 
 	ethernet_phy: ethernet-phy@7 {
 		reg = <7>;
+		device_type = "ethernet-phy";
 	};
 };
 
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index 42af313c13..cc5ba98d6b 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -47,6 +47,7 @@
 
 	ethernet_phy: ethernet-phy@7 {
 		reg = <7>;
+		device_type = "ethernet-phy";
 	};
 };
 
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
index 07e92b88fb..81a6aa562a 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -42,6 +42,7 @@
 
 	ethernet_phy: ethernet-phy@7 {
 		reg = <7>;
+		device_type = "ethernet-phy";
 	};
 };
 
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 0ac7532300..a9ff0e6fa8 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -47,6 +47,7 @@
 
 	ethernet_phy: ethernet-phy@0 {
 		reg = <0>;
+		device_type = "ethernet-phy";
 	};
 };
 
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
index d59a383135..52ec5a4566 100644
--- a/arch/arm/dts/zynq-zybo.dts
+++ b/arch/arm/dts/zynq-zybo.dts
@@ -31,8 +31,8 @@
 	};
 
 	usb_phy0: phy0 {
-		compatible = "usb-nop-xceiv";
 		#phy-cells = <0>;
+		compatible = "usb-nop-xceiv";
 		reset-gpios = <&gpio0 46 1>;
 	};
 };
@@ -48,6 +48,7 @@
 
 	ethernet_phy: ethernet-phy@0 {
 		reg = <0>;
+		device_type = "ethernet-phy";
 	};
 };
 
diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi
index b64a0a6f6b..f6e83e1513 100644
--- a/arch/arm/dts/zynqmp-clk.dtsi
+++ b/arch/arm/dts/zynqmp-clk.dtsi
@@ -8,7 +8,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-&amba {
+/ {
 	clk100: clk100 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi
index 1c2efe459d..12d9fe1498 100644
--- a/arch/arm/dts/zynqmp-ep108-clk.dtsi
+++ b/arch/arm/dts/zynqmp-ep108-clk.dtsi
@@ -8,7 +8,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-&amba {
+/ {
 	misc_clk: misc_clk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
index 9f6b11180e..b0096f14b4 100644
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ b/arch/arm/dts/zynqmp-ep108.dts
@@ -17,6 +17,7 @@
 	model = "ZynqMP EP108";
 
 	aliases {
+		ethernet0 = &gem0;
 		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
 		serial0 = &uart0;
@@ -173,7 +174,7 @@
 		spi-max-frequency = <50000000>;
 		reg = <0>;
 
-		spi0_flash0@00000000 {
+		spi0_flash0@0 {
 			label = "spi0_flash0";
 			reg = <0x0 0x100000>;
 		};
@@ -190,7 +191,7 @@
 		spi-max-frequency = <50000000>;
 		reg = <0>;
 
-		spi1_flash0@00000000 {
+		spi1_flash0@0 {
 			label = "spi1_flash0";
 			reg = <0x0 0x100000>;
 		};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index c2a26c1dbb..1f3c30277a 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -84,7 +84,6 @@
 
 &gem3 {
 	status = "okay";
-	local-mac-address = [00 0a 35 00 02 90];
 	phy-handle = <&phy0>;
 	phy-mode = "rgmii-id";
 	phy0: phy@0 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 32847e1a66..87df36012e 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -94,7 +94,6 @@
 
 &gem2 {
 	status = "okay";
-	local-mac-address = [00 0a 35 00 02 90];
 	phy-handle = <&phy0>;
 	phy-mode = "rgmii-id";
 	phy0: phy@5 {
@@ -197,7 +196,7 @@
 		spi-max-frequency = <50000000>;
 		reg = <0>;
 
-		spi0_flash0@00000000 {
+		spi0_flash0@0 {
 			label = "spi0_flash0";
 			reg = <0x0 0x100000>;
 		};
@@ -214,7 +213,7 @@
 		spi-max-frequency = <20000000>;
 		reg = <0>;
 
-		spi1_flash0@00000000 {
+		spi1_flash0@0 {
 			label = "spi1_flash0";
 			reg = <0x0 0x84000>;
 		};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 1f03a94820..799b87a04c 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -5,10 +5,7 @@
  *
  * Michal Simek <michal.simek@xilinx.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /dts-v1/;
@@ -139,7 +136,6 @@
 
 &gem0 {
 	status = "okay";
-	local-mac-address = [00 0a 35 00 02 90];
 	phy-mode = "rgmii-id";
 	phy-handle = <&ethernet_phy0>;
 	ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
@@ -158,21 +154,18 @@
 
 &gem1 {
 	status = "okay";
-	local-mac-address = [00 0a 35 00 02 91];
 	phy-mode = "rgmii-id";
 	phy-handle = <&ethernet_phy7>;
 };
 
 &gem2 {
 	status = "okay";
-	local-mac-address = [00 0a 35 00 02 92];
 	phy-mode = "rgmii-id";
 	phy-handle = <&ethernet_phy3>;
 };
 
 &gem3 {
 	status = "okay";
-	local-mac-address = [00 0a 35 00 02 93];
 	phy-mode = "rgmii-id";
 	phy-handle = <&ethernet_phy8>;
 };
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 698e72e0c5..6de8296b73 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -82,7 +82,6 @@
 
 &gem1 {
 	status = "okay";
-	local-mac-address = [00 0a 35 00 02 90];
 	phy-handle = <&phy0>;
 	phy-mode = "rgmii-id";
 	phy0: phy@0 {
diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
new file mode 100644
index 0000000000..323a674e3a
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
@@ -0,0 +1,37 @@
+/*
+ * dts file for Xilinx ZynqMP ZCU102 Rev1.0
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "zynqmp-zcu102-revB.dts"
+
+/ {
+	model = "ZynqMP ZCU102 Rev1.0";
+	compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+};
+
+&eeprom  {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	board_sn: board_sn@0 {
+		reg = <0x0 0x14>;
+	};
+
+	eth_mac: eth_mac@20 {
+		reg = <0x20 0x6>;
+	};
+
+	board_name: board_name@d0 {
+		reg = <0xd0 0x6>;
+	};
+
+	board_revision: board_revision@e0 {
+		reg = <0xe0 0x3>;
+	};
+};
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index d8ac008f2b..a2128ebfd8 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -1,5 +1,5 @@
 /*
- * dts file for Xilinx ZynqMP ZCU102
+ * dts file for Xilinx ZynqMP ZCU102 RevA
  *
  * (C) Copyright 2015, Xilinx, Inc.
  *
@@ -13,6 +13,7 @@
 #include "zynqmp.dtsi"
 #include "zynqmp-clk.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 
 / {
 	model = "ZynqMP ZCU102 RevA";
@@ -60,7 +61,7 @@
 		compatible = "gpio-leds";
 		heartbeat_led {
 			label = "heartbeat";
-			gpios = <&gpio 23 0>;
+			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 	};
@@ -68,6 +69,8 @@
 
 &can1 {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can1_default>;
 };
 
 &dcc {
@@ -118,9 +121,10 @@
 
 &gem3 {
 	status = "okay";
-	local-mac-address = [00 0a 35 00 02 90];
 	phy-handle = <&phy0>;
 	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gem3_default>;
 	phy0: phy@21 {
 		reg = <21>;
 		ti,rx-internal-delay = <0x8>;
@@ -131,6 +135,8 @@
 
 &gpio {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio_default>;
 };
 
 &gpu {
@@ -140,6 +146,11 @@
 &i2c0 {
 	status = "okay";
 	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c0_default>;
+	pinctrl-1 = <&pinctrl_i2c0_gpio>;
+	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 
 	tca6416_u97: gpio@20 {
 		/*
@@ -168,7 +179,7 @@
 		gtr_sel0 {
 			gpio-hog;
 			gpios = <0 0>;
-			output-high; /* PCIE = 0, DP = 1 */
+			output-low; /* PCIE = 0, DP = 1 */
 			line-name = "sel0";
 		};
 		gtr_sel1 {
@@ -401,6 +412,12 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 &i2c1 {
 	status = "okay";
 	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1_default>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+
 	/* FIXME PL i2c via PCA9306 - u45 */
 	/* FIXME MSP430 - u41 - not detected */
 	i2cswitch@74 { /* u34 */
@@ -420,7 +437,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 			 * 512B - 768B address 0x56
 			 * 768B - 1024B address 0x57
 			 */
-			eeprom@54 { /* u23 */
+			eeprom: eeprom@54 { /* u23 */
 				compatible = "at,24c08";
 				reg = <0x54>;
 			};
@@ -468,6 +485,11 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 			si5328: clock-generator4@69 {/* SI5328 - u20 */
 				compatible = "silabs,si5328";
 				reg = <0x69>;
+				/*
+				 * Chip has interrupt present connected to PL
+				 * interrupt-parent = <&>;
+				 * interrupts = <>;
+				 */
 			};
 		};
 		/* 5 - 7 unconnected */
@@ -550,8 +572,271 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 	};
 };
 
+&pinctrl0 {
+	status = "okay";
+	pinctrl_i2c0_default: i2c0-default {
+		mux {
+			groups = "i2c0_3_grp";
+			function = "i2c0";
+		};
+
+		conf {
+			groups = "i2c0_3_grp";
+			bias-pull-up;
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+	};
+
+	pinctrl_i2c0_gpio: i2c0-gpio {
+		mux {
+			groups = "gpio0_14_grp", "gpio0_15_grp";
+			function = "gpio0";
+		};
+
+		conf {
+			groups = "gpio0_14_grp", "gpio0_15_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+	};
+
+	pinctrl_i2c1_default: i2c1-default {
+		mux {
+			groups = "i2c1_4_grp";
+			function = "i2c1";
+		};
+
+		conf {
+			groups = "i2c1_4_grp";
+			bias-pull-up;
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+	};
+
+	pinctrl_i2c1_gpio: i2c1-gpio {
+		mux {
+			groups = "gpio0_16_grp", "gpio0_17_grp";
+			function = "gpio0";
+		};
+
+		conf {
+			groups = "gpio0_16_grp", "gpio0_17_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+	};
+
+	pinctrl_uart0_default: uart0-default {
+		mux {
+			groups = "uart0_4_grp";
+			function = "uart0";
+		};
+
+		conf {
+			groups = "uart0_4_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO18";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO19";
+			bias-disable;
+		};
+	};
+
+	pinctrl_uart1_default: uart1-default {
+		mux {
+			groups = "uart1_5_grp";
+			function = "uart1";
+		};
+
+		conf {
+			groups = "uart1_5_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO21";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO20";
+			bias-disable;
+		};
+	};
+
+	pinctrl_usb0_default: usb0-default {
+		mux {
+			groups = "usb0_0_grp";
+			function = "usb0";
+		};
+
+		conf {
+			groups = "usb0_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO52", "MIO53", "MIO55";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+			       "MIO60", "MIO61", "MIO62", "MIO63";
+			bias-disable;
+		};
+	};
+
+	pinctrl_gem3_default: gem3-default {
+		mux {
+			function = "ethernet3";
+			groups = "ethernet3_0_grp";
+		};
+
+		conf {
+			groups = "ethernet3_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+									"MIO75";
+			bias-high-impedance;
+			low-power-disable;
+		};
+
+		conf-tx {
+			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+									"MIO69";
+			bias-disable;
+			low-power-enable;
+		};
+
+		mux-mdio {
+			function = "mdio3";
+			groups = "mdio3_0_grp";
+		};
+
+		conf-mdio {
+			groups = "mdio3_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+			bias-disable;
+		};
+	};
+
+	pinctrl_can1_default: can1-default {
+		mux {
+			function = "can1";
+			groups = "can1_6_grp";
+		};
+
+		conf {
+			groups = "can1_6_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO25";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO24";
+			bias-disable;
+		};
+	};
+
+	pinctrl_sdhci1_default: sdhci1-default {
+		mux {
+			groups = "sdio1_0_grp";
+			function = "sdio1";
+		};
+
+		conf {
+			groups = "sdio1_0_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+			bias-disable;
+		};
+
+		mux-cd {
+			groups = "sdio1_0_cd_grp";
+			function = "sdio1_cd";
+		};
+
+		conf-cd {
+			groups = "sdio1_0_cd_grp";
+			bias-high-impedance;
+			bias-pull-up;
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		mux-wp {
+			groups = "sdio1_0_wp_grp";
+			function = "sdio1_wp";
+		};
+
+		conf-wp {
+			groups = "sdio1_0_wp_grp";
+			bias-high-impedance;
+			bias-pull-up;
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+	};
+
+	pinctrl_gpio_default: gpio-default {
+		mux-sw {
+			function = "gpio0";
+			groups = "gpio0_22_grp", "gpio0_23_grp";
+		};
+
+		conf-sw {
+			groups = "gpio0_22_grp", "gpio0_23_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		mux-msp {
+			function = "gpio0";
+			groups = "gpio0_13_grp", "gpio0_38_grp";
+		};
+
+		conf-msp {
+			groups = "gpio0_13_grp", "gpio0_38_grp";
+			slew-rate = <SLEW_RATE_SLOW>;
+			io-standard = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-pull-up {
+			pins = "MIO22", "MIO23";
+			bias-pull-up;
+		};
+
+		conf-pull-none {
+			pins = "MIO13", "MIO38";
+			bias-disable;
+		};
+	};
+};
+
 &pcie {
-/*	status = "okay"; */
+	status = "okay";
 };
 
 &qspi {
@@ -604,21 +889,29 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 /* SD1 with level shifter */
 &sdhci1 {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci1_default>;
 	no-1-8-v;	/* for 1.0 silicon */
 	xlnx,mio_bank = <1>;
 };
 
 &uart0 {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart0_default>;
 };
 
 &uart1 {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
 /* ULPI SMSC USB3320 */
 &usb0 {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb0_default>;
 };
 
 &dwc3_0 {
@@ -626,6 +919,22 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 	dr_mode = "host";
 };
 
+&watchdog0 {
+	status = "okay";
+};
+
+&xilinx_ams {
+	status = "okay";
+};
+
+&ams_ps {
+	status = "okay";
+};
+
+&ams_pl {
+	status = "okay";
+};
+
 &xilinx_drm {
 	status = "okay";
 	clocks = <&si570_1>;
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
index 82337332f9..c771a946b2 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -12,6 +12,7 @@
 
 / {
 	model = "ZynqMP ZCU102 RevB";
+	compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
 };
 
 &gem3 {
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 1fd570bc2f..247344fcbb 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -17,40 +17,44 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			device_type = "cpu";
 			enable-method = "psci";
+			operating-points-v2 = <&cpu_opp_table>;
 			reg = <0x0>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			device_type = "cpu";
 			enable-method = "psci";
 			reg = <0x1>;
+			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			device_type = "cpu";
 			enable-method = "psci";
 			reg = <0x2>;
+			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			device_type = "cpu";
 			enable-method = "psci";
 			reg = <0x3>;
+			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
 		idle-states {
-			entry-mehod = "arm,psci";
+			entry-method = "arm,psci";
 
 			CPU_SLEEP_0: cpu-sleep-0 {
 				compatible = "arm,idle-state";
@@ -58,11 +62,36 @@
 				local-timer-stop;
 				entry-latency-us = <300>;
 				exit-latency-us = <600>;
-				min-residency-us = <800000>;
+				min-residency-us = <10000>;
 			};
 		};
 	};
 
+	cpu_opp_table: cpu_opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp00 {
+			opp-hz = /bits/ 64 <1199999988>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <500000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <599999994>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <500000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <399999996>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <500000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <299999997>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <500000>;
+		};
+	};
+
 	dcc: dcc {
 		compatible = "arm,dcc";
 		status = "disabled";
@@ -138,7 +167,6 @@
 		};
 
 		pd_dp: pd-dp {
-			/* fixme: what to attach to */
 			#power-domain-cells = <0x0>;
 			pd-id = <0x29>;
 		};
@@ -236,25 +264,97 @@
 	firmware {
 		compatible = "xlnx,zynqmp-pm";
 		method = "smc";
+		interrupt-parent = <&gic>;
+		interrupts = <0 35 4>;
 	};
 
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;
-		interrupts = <1 13 0xf01>,
-			     <1 14 0xf01>,
-			     <1 11 0xf01>,
-			     <1 10 0xf01>;
+		interrupts = <1 13 0xf08>,
+			     <1 14 0xf08>,
+			     <1 11 0xf08>,
+			     <1 10 0xf08>;
 	};
 
 	edac {
 		compatible = "arm,cortex-a53-edac";
 	};
 
-	pcap {
+	fpga_full: fpga-full {
+		compatible = "fpga-region";
+		fpga-mgr = <&pcap>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+	};
+
+	nvmem_firmware {
+		compatible = "xlnx,zynqmp-nvmem-fw";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		soc_revision: soc_revision@0 {
+			reg = <0x0 0x4>;
+		};
+	};
+
+	pcap: pcap {
 		compatible = "xlnx,zynqmp-pcap-fpga";
 	};
 
+	rst: reset-controller {
+		compatible = "xlnx,zynqmp-reset";
+		#reset-cells = <1>;
+	};
+
+	xlnx_dp_snd_card: dp_snd_card {
+		compatible = "xlnx,dp-snd-card";
+		status = "disabled";
+		xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
+		xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
+	};
+
+	xlnx_dp_snd_codec0: dp_snd_codec0 {
+		compatible = "xlnx,dp-snd-codec";
+		status = "disabled";
+		clock-names = "aud_clk";
+	};
+
+	xlnx_dp_snd_pcm0: dp_snd_pcm0 {
+		compatible = "xlnx,dp-snd-pcm";
+		status = "disabled";
+		dmas = <&xlnx_dpdma 4>;
+		dma-names = "tx";
+	};
+
+	xlnx_dp_snd_pcm1: dp_snd_pcm1 {
+		compatible = "xlnx,dp-snd-pcm";
+		status = "disabled";
+		dmas = <&xlnx_dpdma 5>;
+		dma-names = "tx";
+	};
+
+	xilinx_drm: xilinx_drm {
+		compatible = "xlnx,drm";
+		status = "disabled";
+		xlnx,encoder-slave = <&xlnx_dp>;
+		xlnx,connector-type = "DisplayPort";
+		xlnx,dp-sub = <&xlnx_dp_sub>;
+		planes {
+			xlnx,pixel-format = "rgb565";
+			plane0 {
+				dmas = <&xlnx_dpdma 3>;
+				dma-names = "dma0";
+			};
+			plane1 {
+				dmas = <&xlnx_dpdma 0>,
+					<&xlnx_dpdma 1>,
+					<&xlnx_dpdma 2>;
+				dma-names = "dma0", "dma1", "dma2";
+			};
+		};
+	};
+
 	amba_apu: amba_apu@0 {
 		compatible = "simple-bus";
 		#address-cells = <2>;
@@ -432,10 +532,11 @@
 		gpu: gpu@fd4b0000 {
 			status = "disabled";
 			compatible = "arm,mali-400", "arm,mali-utgard";
-			reg = <0x0 0xfd4b0000 0x0 0x30000>;
+			reg = <0x0 0xfd4b0000 0x0 0x10000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 			interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
+			clock-names = "gpu", "gpu_pp0", "gpu_pp1";
 			power-domains = <&pd_gpu>;
 		};
 
@@ -633,6 +734,7 @@
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			reg = <0x0 0xff0a0000 0x0 0x1000>;
+			gpio-controller;
 			power-domains = <&pd_gpio>;
 		};
 
@@ -687,6 +789,7 @@
 			reg-names = "breg", "pcireg", "cfg";
 			ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000	/* non-prefetchable memory */
 				  0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
+			bus-range = <0x00 0xff>;
 			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 			interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 					<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
@@ -723,6 +826,7 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 26 4>, <0 27 4>;
 			interrupt-names = "alarm", "sec";
+			calibration = <0x8000>;
 		};
 
 		serdes: zynqmp_phy@fd400000 {
@@ -730,10 +834,18 @@
 			status = "disabled";
 			reg = <0x0 0xfd400000 0x0 0x40000>,
 			      <0x0 0xfd3d0000 0x0 0x1000>,
-			      <0x0 0xfd1a0000 0x0 0x1000>,
 			      <0x0 0xff5e0000 0x0 0x1000>;
-			reg-names = "serdes", "siou", "fpd", "lpd";
-			xlnx,tx_termination_fix;
+			reg-names = "serdes", "siou", "lpd";
+			nvmem-cells = <&soc_revision>;
+			nvmem-cell-names = "soc_revision";
+			resets = <&rst 16>, <&rst 59>, <&rst 60>,
+				 <&rst 61>, <&rst 62>, <&rst 63>,
+				 <&rst 64>, <&rst 3>, <&rst 29>,
+				 <&rst 30>, <&rst 31>, <&rst 32>;
+			reset-names = "sata_rst", "usb0_crst", "usb1_crst",
+				      "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
+				      "usb1_apbrst", "dp_rst", "gem0_rst",
+				      "gem1_rst", "gem2_rst", "gem3_rst";
 			lane0: lane0 {
 				#phy-cells = <4>;
 			};
@@ -755,6 +867,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 133 4>;
 			power-domains = <&pd_sata>;
+			#stream-id-cells = <4>;
+			iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
+				 <&smmu 0x4c2>, <&smmu 0x4c3>;
+			/* dma-coherent; */
 		};
 
 		sdhci0: sdhci@ff160000 {
@@ -769,6 +885,8 @@
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x870>;
 			power-domains = <&pd_sd0>;
+			nvmem-cells = <&soc_revision>;
+			nvmem-cell-names = "soc_revision";
 		};
 
 		sdhci1: sdhci@ff170000 {
@@ -783,12 +901,21 @@
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x871>;
 			power-domains = <&pd_sd1>;
+			nvmem-cells = <&soc_revision>;
+			nvmem-cell-names = "soc_revision";
+		};
+
+		pinctrl0: pinctrl@ff180000 {
+			compatible = "xlnx,pinctrl-zynqmp";
+			status = "disabled";
+			reg = <0x0 0xff180000 0x0 0x1000>;
 		};
 
 		smmu: smmu@fd800000 {
 			compatible = "arm,mmu-500";
 			reg = <0x0 0xfd800000 0x0 0x20000>;
 			#iommu-cells = <1>;
+			status = "disabled";
 			#global-interrupts = <1>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 155 4>,
@@ -796,32 +923,6 @@
 				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
-			mmu-masters = < &gem0 0x874
-					&gem1 0x875
-					&gem2 0x876
-					&gem3 0x877
-					&usb0 0x860
-					&usb1 0x861
-					&qspi 0x873
-					&lpd_dma_chan1 0x868
-					&lpd_dma_chan2 0x869
-					&lpd_dma_chan3 0x86a
-					&lpd_dma_chan4 0x86b
-					&lpd_dma_chan5 0x86c
-					&lpd_dma_chan6 0x86d
-					&lpd_dma_chan7 0x86e
-					&lpd_dma_chan8 0x86f
-					&fpd_dma_chan1 0x14e8
-					&fpd_dma_chan2 0x14e9
-					&fpd_dma_chan3 0x14ea
-					&fpd_dma_chan4 0x14eb
-					&fpd_dma_chan5 0x14ec
-					&fpd_dma_chan6 0x14ed
-					&fpd_dma_chan7 0x14ee
-					&fpd_dma_chan8 0x14ef
-					&sdhci0 0x870
-					&sdhci1 0x871
-					&nand0 0x872>;
 		};
 
 		spi0: spi@ff040000 {
@@ -910,49 +1011,55 @@
 			power-domains = <&pd_uart1>;
 		};
 
-		usb0: usb0 {
+		usb0: usb0@ff9d0000 {
 			#address-cells = <2>;
 			#size-cells = <2>;
 			status = "disabled";
 			compatible = "xlnx,zynqmp-dwc3";
+			reg = <0x0 0xff9d0000 0x0 0x100>;
 			clock-names = "bus_clk", "ref_clk";
-			clocks = <&clk125>, <&clk125>;
-			#stream-id-cells = <1>;
-			iommus = <&smmu 0x860>;
 			power-domains = <&pd_usb0>;
 			ranges;
+			nvmem-cells = <&soc_revision>;
+			nvmem-cell-names = "soc_revision";
 
 			dwc3_0: dwc3@fe200000 {
 				compatible = "snps,dwc3";
 				status = "disabled";
 				reg = <0x0 0xfe200000 0x0 0x40000>;
 				interrupt-parent = <&gic>;
-				interrupts = <0 65 4>;
-				/* snps,quirk-frame-length-adjustment = <0x20>; */
+				interrupts = <0 65 4>, <0 69 4>;
+				#stream-id-cells = <1>;
+				iommus = <&smmu 0x860>;
+				snps,quirk-frame-length-adjustment = <0x20>;
 				snps,refclk_fladj;
+				/* dma-coherent; */
 			};
 		};
 
-		usb1: usb1 {
+		usb1: usb1@ff9e0000 {
 			#address-cells = <2>;
 			#size-cells = <2>;
 			status = "disabled";
 			compatible = "xlnx,zynqmp-dwc3";
+			reg = <0x0 0xff9e0000 0x0 0x100>;
 			clock-names = "bus_clk", "ref_clk";
-			clocks = <&clk125>, <&clk125>;
-			#stream-id-cells = <1>;
-			iommus = <&smmu 0x861>;
 			power-domains = <&pd_usb1>;
 			ranges;
+			nvmem-cells = <&soc_revision>;
+			nvmem-cell-names = "soc_revision";
 
 			dwc3_1: dwc3@fe300000 {
 				compatible = "snps,dwc3";
 				status = "disabled";
 				reg = <0x0 0xfe300000 0x0 0x40000>;
 				interrupt-parent = <&gic>;
-				interrupts = <0 70 4>;
-				/* snps,quirk-frame-length-adjustment = <0x20>; */
+				interrupts = <0 70 4>, <0 74 4>;
+				#stream-id-cells = <1>;
+				iommus = <&smmu 0x861>;
+				snps,quirk-frame-length-adjustment = <0x20>;
 				snps,refclk_fladj;
+				/* dma-coherent; */
 			};
 		};
 
@@ -965,24 +1072,29 @@
 			timeout-sec = <10>;
 		};
 
-		xilinx_drm: xilinx_drm {
-			compatible = "xlnx,drm";
+		xilinx_ams: ams@ffa50000 {
+			compatible = "xlnx,zynqmp-ams";
 			status = "disabled";
-			xlnx,encoder-slave = <&xlnx_dp>;
-			xlnx,connector-type = "DisplayPort";
-			xlnx,dp-sub = <&xlnx_dp_sub>;
-			planes {
-				xlnx,pixel-format = "rgb565";
-				plane0 {
-					dmas = <&xlnx_dpdma 3>;
-					dma-names = "dma0";
-				};
-				plane1 {
-					dmas = <&xlnx_dpdma 0>,
-					       <&xlnx_dpdma 1>,
-					       <&xlnx_dpdma 2>;
-					dma-names = "dma0", "dma1", "dma2";
-				};
+			interrupt-parent = <&gic>;
+			interrupts = <0 56 4>;
+			interrupt-names = "ams-irq";
+			reg = <0x0 0xffa50000 0x0 0x800>;
+			reg-names = "ams-base";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			#io-channel-cells = <1>;
+			ranges;
+
+			ams_ps: ams_ps@ffa50800 {
+				compatible = "xlnx,zynqmp-ams-ps";
+				status = "disabled";
+				reg = <0x0 0xffa50800 0x0 0x400>;
+			};
+
+			ams_pl: ams_pl@ffa50c00 {
+				compatible = "xlnx,zynqmp-ams-pl";
+				status = "disabled";
+				reg = <0x0 0xffa50c00 0x0 0x400>;
 			};
 		};
 
@@ -993,6 +1105,7 @@
 			interrupts = <0 119 4>;
 			interrupt-parent = <&gic>;
 			clock-names = "aclk", "aud_clk";
+			power-domains = <&pd_dp>;
 			xlnx,dp-version = "v1.2";
 			xlnx,max-lanes = <2>;
 			xlnx,max-link-rate = <540000>;
@@ -1005,33 +1118,6 @@
 			xlnx,max-pclock-frequency = <300000>;
 		};
 
-		xlnx_dp_snd_card: dp_snd_card {
-			compatible = "xlnx,dp-snd-card";
-			status = "disabled";
-			xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
-			xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
-		};
-
-		xlnx_dp_snd_codec0: dp_snd_codec0 {
-			compatible = "xlnx,dp-snd-codec";
-			status = "disabled";
-			clock-names = "aud_clk";
-		};
-
-		xlnx_dp_snd_pcm0: dp_snd_pcm0 {
-			compatible = "xlnx,dp-snd-pcm";
-			status = "disabled";
-			dmas = <&xlnx_dpdma 4>;
-			dma-names = "tx";
-		};
-
-		xlnx_dp_snd_pcm1: dp_snd_pcm1 {
-			compatible = "xlnx,dp-snd-pcm";
-			status = "disabled";
-			dmas = <&xlnx_dpdma 5>;
-			dma-names = "tx";
-		};
-
 		xlnx_dp_sub: dp_sub@fd4aa000 {
 			compatible = "xlnx,dp-sub";
 			status = "disabled";
@@ -1042,6 +1128,7 @@
 			xlnx,output-fmt = "rgb";
 			xlnx,vid-fmt = "yuyv";
 			xlnx,gfx-fmt = "rgb565";
+			power-domains = <&pd_dp>;
 		};
 
 		xlnx_dpdma: dma@fd4c0000 {
@@ -1051,6 +1138,7 @@
 			interrupts = <0 122 4>;
 			interrupt-parent = <&gic>;
 			clock-names = "axi_clk";
+			power-domains = <&pd_dp>;
 			dma-channels = <6>;
 			#dma-cells = <1>;
 			dma-video0channel {
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index cab29ba036..327046bf1b 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -21,6 +21,9 @@
 #define ZYNQMP_USB0_XHCI_BASEADDR	0xFE200000
 #define ZYNQMP_USB1_XHCI_BASEADDR	0xFE300000
 
+#define ZYNQMP_TCM_BASE_ADDR	0xFFE00000
+#define ZYNQMP_TCM_SIZE		0x40000
+
 #define ZYNQMP_CRL_APB_BASEADDR	0xFF5E0000
 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT	0x1000000
 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT	0
@@ -125,6 +128,8 @@ struct apu_regs {
 #define ZYNQMP_CSU_VERSION_VELOCE	0x2
 #define ZYNQMP_CSU_VERSION_QEMU		0x3
 
+#define ZYNQMP_CSU_VERSION_EMPTY_SHIFT		20
+
 #define ZYNQMP_SILICON_VER_MASK		0xF000
 #define ZYNQMP_SILICON_VER_SHIFT	12
 
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index e52abd71a5..f256c7d4a9 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -15,6 +15,7 @@
 enum {
 	IDCODE,
 	VERSION,
+	IDCODE2,
 };
 
 enum {
@@ -29,8 +30,6 @@ enum {
 	TCM_SPLIT,
 };
 
-int zynq_slcr_get_mio_pin_status(const char *periph);
-
 unsigned int zynqmp_get_silicon_version(void);
 
 void psu_init(void);
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index bf29b4d396..e3f0117da5 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -15,4 +15,4 @@ obj-y	+= slcr.o
 obj-y	+= clk.o
 obj-y	+= lowlevel_init.o
 AFLAGS_lowlevel_init.o := -mfpu=neon
-obj-$(CONFIG_SPL_BUILD)	+= spl.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o ps7_spl_init.o
diff --git a/arch/arm/mach-zynq/include/mach/nand.h b/arch/arm/mach-zynq/include/mach/nand.h
new file mode 100644
index 0000000000..61ef45f582
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/nand.h
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2017 National Instruments Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <nand.h>
+
+void zynq_nand_init(void);
diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
new file mode 100644
index 0000000000..0af4165a3e
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
@@ -0,0 +1,48 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_PS7_INIT_GPL_H
+#define _ASM_ARCH_PS7_INIT_GPL_H
+
+/* Opcode exit is 0 all the time */
+#define OPCODE_EXIT		0U
+#define OPCODE_MASKWRITE	0U
+#define OPCODE_MASKPOLL		1U
+#define OPCODE_MASKDELAY	2U
+#define OPCODE_WRITE		3U
+#define OPCODE_ADDRESS_MASK	(~3U)
+
+/* Sentinel */
+#define EMIT_EXIT()			OPCODE_EXIT
+/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
+#define EMIT_MASKWRITE(addr, mask, val)	OPCODE_MASKWRITE | addr, mask, val
+#define EMIT_MASKPOLL(addr, mask)	OPCODE_MASKPOLL | addr, mask
+#define EMIT_MASKDELAY(addr, mask)	OPCODE_MASKDELAY | addr, mask
+#define EMIT_WRITE(addr, val)		OPCODE_WRITE | addr, val
+
+/* Returns codes of ps7_init* */
+#define PS7_INIT_SUCCESS		(0)
+#define PS7_INIT_CORRUPT		(1)
+#define PS7_INIT_TIMEOUT		(2)
+#define PS7_POLL_FAILED_DDR_INIT	(3)
+#define PS7_POLL_FAILED_DMA		(4)
+#define PS7_POLL_FAILED_PLL		(5)
+
+#define PCW_SILICON_VERSION_1	0
+#define PCW_SILICON_VERSION_2	1
+#define PCW_SILICON_VERSION_3	2
+
+/* Called by spl.c */
+int ps7_init(void);
+int ps7_post_config(void);
+
+/* Defined in ps7_init_common.c */
+int ps7_config(unsigned long *ps7_config_init);
+
+unsigned long ps7GetSiliconVersion(void);
+
+#endif /* _ASM_ARCH_PS7_INIT_GPL_H */
diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h
index 67238e7fbc..af61352dd1 100644
--- a/arch/arm/mach-zynq/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynq/include/mach/sys_proto.h
@@ -20,7 +20,4 @@ extern unsigned int zynq_get_silicon_version(void);
 
 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
 
-/* Driver extern functions */
-extern void ps7_init(void);
-
 #endif /* _SYS_PROTO_H_ */
diff --git a/board/topic/zynq/ps7_init_common.c b/arch/arm/mach-zynq/ps7_spl_init.c
index b1d45c242f..6dc4e0364d 100644
--- a/board/topic/zynq/ps7_init_common.c
+++ b/arch/arm/mach-zynq/ps7_spl_init.c
@@ -1,12 +1,32 @@
 /*
- * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.
  * (c) Copyright 2016 Topic Embedded Products.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "ps7_init_gpl.h"
 #include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/ps7_init_gpl.h>
+
+__weak int ps7_init(void)
+{
+	/*
+	 * This function is overridden by the one in
+	 * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
+	 */
+	return 0;
+}
+
+__weak int ps7_post_config(void)
+{
+	/*
+	 * This function is overridden by the one in
+	 * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
+	 */
+	return 0;
+}
 
 /* For delay calculation using global registers*/
 #define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
@@ -63,7 +83,7 @@ static void perf_reset_and_start_timer(void)
 	perf_start_clock();
 }
 
-int ps7_config(unsigned long *ps7_config_init)
+int __weak ps7_config(unsigned long *ps7_config_init)
 {
 	unsigned long *ptr = ps7_config_init;
 	unsigned long opcode;
@@ -88,6 +108,12 @@ int ps7_config(unsigned long *ps7_config_init)
 			iowrite((ioread(addr) & ~mask) | (val & mask), addr);
 			break;
 
+		case OPCODE_WRITE:
+			numargs = 2;
+			val = ptr[1];
+			iowrite(val, addr);
+			break;
+
 		case OPCODE_MASKPOLL:
 			numargs = 2;
 			mask = ptr[1];
@@ -115,3 +141,8 @@ int ps7_config(unsigned long *ps7_config_init)
 		ptr += numargs;
 	}
 }
+
+unsigned long __weak __maybe_unused ps7GetSiliconVersion(void)
+{
+	return zynq_get_silicon_version();
+}
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 2a207ae46c..ba453a7024 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -179,8 +179,9 @@ u32 zynq_slcr_get_idcode(void)
 int zynq_slcr_get_mio_pin_status(const char *periph)
 {
 	const struct zynq_slcr_mio_get_status *mio_ptr;
-	int val, i, j;
+	int val, j;
 	int mio = 0;
+	u32 i;
 
 	for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
 		if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index e8added155..1672fa05c2 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -11,6 +11,7 @@
 #include <asm/spl.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/ps7_init_gpl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -83,23 +84,6 @@ int spl_start_uboot(void)
 }
 #endif
 
-__weak void ps7_init(void)
-{
-	/*
-	 * This function is overridden by the one in
-	 * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
-	 */
-}
-
-__weak int ps7_post_config(void)
-{
-	/*
-	 * This function is overridden by the one in
-	 * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
-	 */
-	return 0;
-}
-
 void spl_board_prepare_for_boot(void)
 {
 	ps7_post_config();
diff --git a/board/opalkelly/zynq/MAINTAINERS b/board/opalkelly/zynq/MAINTAINERS
new file mode 100644
index 0000000000..df4b9b6da4
--- /dev/null
+++ b/board/opalkelly/zynq/MAINTAINERS
@@ -0,0 +1,6 @@
+ZYNQ BOARD
+M:	Tom McLeod <tom.mcleod@opalkelly.com>
+S:	Maintained
+F:	board/opalkelly/zynq/
+F:	include/configs/syzygy_hub.h
+F:	configs/syzygy_hub_defconfig
diff --git a/board/opalkelly/zynq/Makefile b/board/opalkelly/zynq/Makefile
new file mode 100644
index 0000000000..09fc788e8d
--- /dev/null
+++ b/board/opalkelly/zynq/Makefile
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= board.o
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
diff --git a/board/opalkelly/zynq/board.c b/board/opalkelly/zynq/board.c
new file mode 100644
index 0000000000..a95c9d1eff
--- /dev/null
+++ b/board/opalkelly/zynq/board.c
@@ -0,0 +1 @@
+#include "../../xilinx/zynq/board.c"
diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
new file mode 100644
index 0000000000..3bd02f3c83
--- /dev/null
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
@@ -0,0 +1,297 @@
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+* (c) Copyright 2017 Opal Kelly Inc.
+*
+* SPDX-License-Identifier: GPL-2.0+
+ *****************************************************************************/
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC044DU),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003F01U, 0x00001201U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002E0037U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0x7FFF8000U),
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00088000U),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0x7FFF0000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0x7FFF8000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U),
+	EMIT_MASKWRITE(0XE000A00C, 0x003F003FU, 0x00370008U),
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00088000U),
+	EMIT_MASKWRITE(0XE000A00C, 0x003F003FU, 0x00370000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKWRITE(0XE000A00C, 0x003F003FU, 0x00370008U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_reset_apu_3_0[] = {
+	EMIT_MASKWRITE(0xF8000244, 0x00000022U, 0x00000022U),
+	EMIT_EXIT(),
+};
+
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_reset_apu_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
+
diff --git a/board/topic/zynq/Makefile b/board/topic/zynq/Makefile
index eaf59cd55c..7893482075 100644
--- a/board/topic/zynq/Makefile
+++ b/board/topic/zynq/Makefile
@@ -7,4 +7,4 @@ obj-y	:= board.o
 # Remove quotes
 hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
 
-obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o ps7_init_common.o
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
diff --git a/board/topic/zynq/ps7_init_gpl.h b/board/topic/zynq/ps7_init_gpl.h
deleted file mode 100644
index ef719acaba..0000000000
--- a/board/topic/zynq/ps7_init_gpl.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
- * (c) Copyright 2016 Topic Embedded Products.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define OPCODE_EXIT       0U
-#define OPCODE_MASKWRITE  0U
-#define OPCODE_MASKPOLL   1U
-#define OPCODE_MASKDELAY  2U
-#define OPCODE_ADDRESS_MASK (~3U)
-
-/* Sentinel */
-#define EMIT_EXIT()                     OPCODE_EXIT
-/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
-#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val
-#define EMIT_MASKPOLL(addr, mask)       OPCODE_MASKPOLL | addr, mask
-#define EMIT_MASKDELAY(addr, mask)      OPCODE_MASKDELAY | addr, mask
-
-/* Returns codes of ps7_init* */
-#define PS7_INIT_SUCCESS   (0)
-#define PS7_INIT_CORRUPT   (1)
-#define PS7_INIT_TIMEOUT   (2)
-#define PS7_POLL_FAILED_DDR_INIT (3)
-#define PS7_POLL_FAILED_DMA      (4)
-#define PS7_POLL_FAILED_PLL      (5)
-
-/* Called by spl.c */
-int ps7_init(void);
-int ps7_post_config(void);
-
-/* Defined in ps7_init_common.c */
-int ps7_config(unsigned long *ps7_config_init);
diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
index b195d7a25b..ceed04383f 100644
--- a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "../ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
 
 static unsigned long ps7_pll_init_data_3_0[] = {
 	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
index ec0cc7d19d..1205d19d9a 100644
--- a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "../ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
 
 static unsigned long ps7_pll_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
index 5a923366eb..f42632b7fa 100644
--- a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "../ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
 
 static unsigned long ps7_pll_init_data_3_0[] = {
 	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 90ef542458..e59038106a 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -11,6 +11,7 @@
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/ps7_init_gpl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -111,7 +112,15 @@ int board_late_init(void)
 #ifdef CONFIG_DISPLAY_BOARDINFO
 int checkboard(void)
 {
+	u32 version = zynq_get_silicon_version();
+
+	version <<= 1;
+	if (version > (PCW_SILICON_VERSION_3 << 1))
+		version += 1;
+
 	puts("Board: Xilinx Zynq\n");
+	printf("Silicon: v%d.%d\n", version >> 1, version & 1);
+
 	return 0;
 }
 #endif
@@ -132,9 +141,7 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 int dram_init_banksize(void)
 {
-	fdtdec_setup_memory_banksize();
-
-	return 0;
+	return fdtdec_setup_memory_banksize();
 }
 
 int dram_init(void)
diff --git a/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
new file mode 100644
index 0000000000..9a65a27f0e
--- /dev/null
+++ b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
@@ -0,0 +1,815 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74,  0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054,  0x00000007U),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74,  0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054,  0x00000007U),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74,  0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054,  0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	unsigned long *ps7_mio_init_data;
+	unsigned long *ps7_pll_init_data;
+	unsigned long *ps7_clock_init_data;
+	unsigned long *ps7_ddr_init_data;
+	unsigned long *ps7_peripherals_init_data;
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
diff --git a/board/xilinx/zynq/zynq-cse-qspi-single b/board/xilinx/zynq/zynq-cse-qspi-single
new file mode 120000
index 0000000000..764d141171
--- /dev/null
+++ b/board/xilinx/zynq/zynq-cse-qspi-single
@@ -0,0 +1 @@
+zynq-zc706
+\ No newline at end of file
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
index eb290023a1..5cf627d223 100644
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -14,7 +14,7 @@
 *
 *****************************************************************************/
 
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
 
 unsigned long ps7_pll_init_data_3_0[] = {
     // START: top
@@ -4121,37 +4121,6 @@ unsigned long ps7_post_config_3_0[] = {
     //
 };
 
-unsigned long ps7_debug_3_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
 
 unsigned long ps7_pll_init_data_2_0[] = {
     // START: top
@@ -8419,37 +8388,6 @@ unsigned long ps7_post_config_2_0[] = {
     //
 };
 
-unsigned long ps7_debug_2_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
 
 unsigned long ps7_pll_init_data_1_0[] = {
     // START: top
@@ -12650,173 +12588,9 @@ unsigned long ps7_post_config_1_0[] = {
     //
 };
 
-unsigned long ps7_debug_1_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
 
 
 #include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
-  char* err_msg = "";
-  switch (key) {
-    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
-    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
-    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
-    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
-    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
-    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
-    default:                                err_msg = "Undefined error status"; break;
-  }
-
-  return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
-  // Read PS version from MCTRL register [31:28]
-  unsigned long mask = 0xF0000000;
-  unsigned long *addr = (unsigned long*) 0XF8007080;
-  unsigned long ps_version = (*addr & mask) >> 28;
-  return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
-        *addr = ( val & mask ) | ( *addr & ~mask);
-        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
-        volatile unsigned long *addr = (volatile unsigned long*) add;
-        int i = 0;
-        while (!(*addr & mask)) {
-          if (i == PS7_MASK_POLL_TIME) {
-            return -1;
-          }
-          i++;
-        }
-     return 1;
-        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
-        unsigned long val = (*addr & mask);
-        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
-        return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
-    unsigned long *ptr = ps7_config_init;
-
-    unsigned long  opcode;            // current instruction ..
-    unsigned long  args[16];           // no opcode has so many args ...
-    int  numargs;           // number of arguments of this instruction
-    int  j;                 // general purpose index
-
-    volatile unsigned long *addr;         // some variable to make code readable
-    unsigned long  val,mask;              // some variable to make code readable
-
-    int finish = -1 ;           // loop while this is negative !
-    int i = 0;                  // Timeout variable
-
-    while( finish < 0 ) {
-        numargs = ptr[0] & 0xF;
-        opcode = ptr[0] >> 4;
-
-        for( j = 0 ; j < numargs ; j ++ )
-            args[j] = ptr[j+1];
-        ptr += numargs + 1;
-
-
-        switch ( opcode ) {
-
-        case OPCODE_EXIT:
-            finish = PS7_INIT_SUCCESS;
-            break;
-
-        case OPCODE_CLEAR:
-            addr = (unsigned long*) args[0];
-            *addr = 0;
-            break;
-
-        case OPCODE_WRITE:
-            addr = (unsigned long*) args[0];
-            val = args[1];
-            *addr = val;
-            break;
-
-        case OPCODE_MASKWRITE:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            val = args[2];
-            *addr = ( val & mask ) | ( *addr & ~mask);
-            break;
-
-        case OPCODE_MASKPOLL:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            i = 0;
-            while (!(*addr & mask)) {
-                if (i == PS7_MASK_POLL_TIME) {
-                    finish = PS7_INIT_TIMEOUT;
-                    break;
-                }
-                i++;
-            }
-            break;
-        case OPCODE_MASKDELAY:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            int delay = get_number_of_cycles_for_delay(mask);
-            perf_reset_and_start_timer();
-            while ((*addr < delay)) {
-            }
-            break;
-        default:
-            finish = PS7_INIT_CORRUPT;
-            break;
-        }
-    }
-    return finish;
-}
 
 unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
 unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -12844,25 +12618,6 @@ ps7_post_config()
 }
 
 int
-ps7_debug()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_debug_1_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_debug_2_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_debug_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
 ps7_init()
 {
   // Get the PS_VERSION on run time
@@ -12923,41 +12678,3 @@ ps7_init()
 
 
 
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
-						      (1 << 3) | // Auto-increment
-						      (0 << 8) // Pre-scale
-	);
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
-	perf_disable_clock();
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
-  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
-  return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
-	    perf_reset_clock();
-	    perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
deleted file mode 100644
index bdea5a0443..0000000000
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
+++ /dev/null
@@ -1,117 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier:	GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int  u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long  * ps7_ddr_init_data;
-extern unsigned long  * ps7_mio_init_data;
-extern unsigned long  * ps7_pll_init_data;
-extern unsigned long  * ps7_clock_init_data;
-extern unsigned long  * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT       0U
-#define OPCODE_CLEAR      1U
-#define OPCODE_WRITE      2U
-#define OPCODE_MASKWRITE  3U
-#define OPCODE_MASKPOLL   4U
-#define OPCODE_MASKDELAY  5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
-#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes  of PS7_Init */
-#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
-#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ  666666687
-#define DDR_FREQ  533333374
-#define DCI_FREQ  10158731
-#define QSPI_FREQ  200000000
-#define SMC_FREQ  10000000
-#define ENET0_FREQ  125000000
-#define ENET1_FREQ  10000000
-#define USB0_FREQ  60000000
-#define USB1_FREQ  60000000
-#define SDIO_FREQ  50000000
-#define UART_FREQ  50000000
-#define SPI_FREQ  10000000
-#define I2C_FREQ  111111115
-#define WDT_FREQ  111111115
-#define TTC_FREQ  50000000
-#define CAN_FREQ  10000000
-#define PCAP_FREQ  200000000
-#define TPIU_FREQ  200000000
-#define FPGA0_FREQ  100000000
-#define FPGA1_FREQ  100000000
-#define FPGA2_FREQ  33333336
-#define FPGA3_FREQ  50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
index abfd91187d..fc325a6b02 100644
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
@@ -14,7 +14,7 @@
 *
 *****************************************************************************/
 
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
 
 unsigned long ps7_pll_init_data_3_0[] = {
     // START: top
@@ -4228,37 +4228,6 @@ unsigned long ps7_post_config_3_0[] = {
     //
 };
 
-unsigned long ps7_debug_3_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
 
 unsigned long ps7_pll_init_data_2_0[] = {
     // START: top
@@ -8639,37 +8608,6 @@ unsigned long ps7_post_config_2_0[] = {
     //
 };
 
-unsigned long ps7_debug_2_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
 
 unsigned long ps7_pll_init_data_1_0[] = {
     // START: top
@@ -12983,173 +12921,9 @@ unsigned long ps7_post_config_1_0[] = {
     //
 };
 
-unsigned long ps7_debug_1_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
 
 
 #include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
-  char* err_msg = "";
-  switch (key) {
-    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
-    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
-    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
-    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
-    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
-    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
-    default:                                err_msg = "Undefined error status"; break;
-  }
-
-  return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
-  // Read PS version from MCTRL register [31:28]
-  unsigned long mask = 0xF0000000;
-  unsigned long *addr = (unsigned long*) 0XF8007080;
-  unsigned long ps_version = (*addr & mask) >> 28;
-  return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
-        *addr = ( val & mask ) | ( *addr & ~mask);
-        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
-        volatile unsigned long *addr = (volatile unsigned long*) add;
-        int i = 0;
-        while (!(*addr & mask)) {
-          if (i == PS7_MASK_POLL_TIME) {
-            return -1;
-          }
-          i++;
-        }
-     return 1;
-        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
-        unsigned long val = (*addr & mask);
-        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
-        return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
-    unsigned long *ptr = ps7_config_init;
-
-    unsigned long  opcode;            // current instruction ..
-    unsigned long  args[16];           // no opcode has so many args ...
-    int  numargs;           // number of arguments of this instruction
-    int  j;                 // general purpose index
-
-    volatile unsigned long *addr;         // some variable to make code readable
-    unsigned long  val,mask;              // some variable to make code readable
-
-    int finish = -1 ;           // loop while this is negative !
-    int i = 0;                  // Timeout variable
-
-    while( finish < 0 ) {
-        numargs = ptr[0] & 0xF;
-        opcode = ptr[0] >> 4;
-
-        for( j = 0 ; j < numargs ; j ++ )
-            args[j] = ptr[j+1];
-        ptr += numargs + 1;
-
-
-        switch ( opcode ) {
-
-        case OPCODE_EXIT:
-            finish = PS7_INIT_SUCCESS;
-            break;
-
-        case OPCODE_CLEAR:
-            addr = (unsigned long*) args[0];
-            *addr = 0;
-            break;
-
-        case OPCODE_WRITE:
-            addr = (unsigned long*) args[0];
-            val = args[1];
-            *addr = val;
-            break;
-
-        case OPCODE_MASKWRITE:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            val = args[2];
-            *addr = ( val & mask ) | ( *addr & ~mask);
-            break;
-
-        case OPCODE_MASKPOLL:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            i = 0;
-            while (!(*addr & mask)) {
-                if (i == PS7_MASK_POLL_TIME) {
-                    finish = PS7_INIT_TIMEOUT;
-                    break;
-                }
-                i++;
-            }
-            break;
-        case OPCODE_MASKDELAY:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            int delay = get_number_of_cycles_for_delay(mask);
-            perf_reset_and_start_timer();
-            while ((*addr < delay)) {
-            }
-            break;
-        default:
-            finish = PS7_INIT_CORRUPT;
-            break;
-        }
-    }
-    return finish;
-}
 
 unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
 unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -13177,25 +12951,6 @@ ps7_post_config()
 }
 
 int
-ps7_debug()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_debug_1_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_debug_2_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_debug_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
 ps7_init()
 {
   // Get the PS_VERSION on run time
@@ -13252,45 +13007,3 @@ ps7_init()
   //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
   return PS7_INIT_SUCCESS;
 }
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
-						      (1 << 3) | // Auto-increment
-						      (0 << 8) // Pre-scale
-	);
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
-	perf_disable_clock();
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
-  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
-  return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
-	    perf_reset_clock();
-	    perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
deleted file mode 100644
index 16fa8104a4..0000000000
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
+++ /dev/null
@@ -1,117 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier:	GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int  u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long  * ps7_ddr_init_data;
-extern unsigned long  * ps7_mio_init_data;
-extern unsigned long  * ps7_pll_init_data;
-extern unsigned long  * ps7_clock_init_data;
-extern unsigned long  * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT       0U
-#define OPCODE_CLEAR      1U
-#define OPCODE_WRITE      2U
-#define OPCODE_MASKWRITE  3U
-#define OPCODE_MASKPOLL   4U
-#define OPCODE_MASKDELAY  5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
-#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes  of PS7_Init */
-#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
-#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ  666666687
-#define DDR_FREQ  533333374
-#define DCI_FREQ  10158731
-#define QSPI_FREQ  200000000
-#define SMC_FREQ  10000000
-#define ENET0_FREQ  25000000
-#define ENET1_FREQ  10000000
-#define USB0_FREQ  60000000
-#define USB1_FREQ  60000000
-#define SDIO_FREQ  50000000
-#define UART_FREQ  50000000
-#define SPI_FREQ  10000000
-#define I2C_FREQ  111111115
-#define WDT_FREQ  111111115
-#define TTC_FREQ  50000000
-#define CAN_FREQ  23809523
-#define PCAP_FREQ  200000000
-#define TPIU_FREQ  200000000
-#define FPGA0_FREQ  50000000
-#define FPGA1_FREQ  50000000
-#define FPGA2_FREQ  50000000
-#define FPGA3_FREQ  50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
index 77fd9499df..ca5490f0b0 100644
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
@@ -14,7 +14,7 @@
 *
 *****************************************************************************/
 
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
 
 unsigned long ps7_pll_init_data_3_0[] = {
     // START: top
@@ -4197,37 +4197,6 @@ unsigned long ps7_post_config_3_0[] = {
     //
 };
 
-unsigned long ps7_debug_3_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
 
 unsigned long ps7_pll_init_data_2_0[] = {
     // START: top
@@ -8577,37 +8546,6 @@ unsigned long ps7_post_config_2_0[] = {
     //
 };
 
-unsigned long ps7_debug_2_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
 
 unsigned long ps7_pll_init_data_1_0[] = {
     // START: top
@@ -12890,173 +12828,9 @@ unsigned long ps7_post_config_1_0[] = {
     //
 };
 
-unsigned long ps7_debug_1_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
 
 
 #include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
-  char* err_msg = "";
-  switch (key) {
-    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
-    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
-    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
-    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
-    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
-    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
-    default:                                err_msg = "Undefined error status"; break;
-  }
-
-  return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
-  // Read PS version from MCTRL register [31:28]
-  unsigned long mask = 0xF0000000;
-  unsigned long *addr = (unsigned long*) 0XF8007080;
-  unsigned long ps_version = (*addr & mask) >> 28;
-  return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
-        *addr = ( val & mask ) | ( *addr & ~mask);
-        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
-        volatile unsigned long *addr = (volatile unsigned long*) add;
-        int i = 0;
-        while (!(*addr & mask)) {
-          if (i == PS7_MASK_POLL_TIME) {
-            return -1;
-          }
-          i++;
-        }
-     return 1;
-        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
-        unsigned long val = (*addr & mask);
-        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
-        return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
-    unsigned long *ptr = ps7_config_init;
-
-    unsigned long  opcode;            // current instruction ..
-    unsigned long  args[16];           // no opcode has so many args ...
-    int  numargs;           // number of arguments of this instruction
-    int  j;                 // general purpose index
-
-    volatile unsigned long *addr;         // some variable to make code readable
-    unsigned long  val,mask;              // some variable to make code readable
-
-    int finish = -1 ;           // loop while this is negative !
-    int i = 0;                  // Timeout variable
-
-    while( finish < 0 ) {
-        numargs = ptr[0] & 0xF;
-        opcode = ptr[0] >> 4;
-
-        for( j = 0 ; j < numargs ; j ++ )
-            args[j] = ptr[j+1];
-        ptr += numargs + 1;
-
-
-        switch ( opcode ) {
-
-        case OPCODE_EXIT:
-            finish = PS7_INIT_SUCCESS;
-            break;
-
-        case OPCODE_CLEAR:
-            addr = (unsigned long*) args[0];
-            *addr = 0;
-            break;
-
-        case OPCODE_WRITE:
-            addr = (unsigned long*) args[0];
-            val = args[1];
-            *addr = val;
-            break;
-
-        case OPCODE_MASKWRITE:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            val = args[2];
-            *addr = ( val & mask ) | ( *addr & ~mask);
-            break;
-
-        case OPCODE_MASKPOLL:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            i = 0;
-            while (!(*addr & mask)) {
-                if (i == PS7_MASK_POLL_TIME) {
-                    finish = PS7_INIT_TIMEOUT;
-                    break;
-                }
-                i++;
-            }
-            break;
-        case OPCODE_MASKDELAY:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            int delay = get_number_of_cycles_for_delay(mask);
-            perf_reset_and_start_timer();
-            while ((*addr < delay)) {
-            }
-            break;
-        default:
-            finish = PS7_INIT_CORRUPT;
-            break;
-        }
-    }
-    return finish;
-}
 
 unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
 unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -13084,25 +12858,6 @@ ps7_post_config()
 }
 
 int
-ps7_debug()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_debug_1_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_debug_2_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_debug_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
 ps7_init()
 {
   // Get the PS_VERSION on run time
@@ -13163,41 +12918,3 @@ ps7_init()
 
 
 
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
-						      (1 << 3) | // Auto-increment
-						      (0 << 8) // Pre-scale
-	);
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
-	perf_disable_clock();
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
-  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
-  return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
-	    perf_reset_clock();
-	    perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
deleted file mode 100644
index 8527eef447..0000000000
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
+++ /dev/null
@@ -1,117 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier:	GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int  u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long  * ps7_ddr_init_data;
-extern unsigned long  * ps7_mio_init_data;
-extern unsigned long  * ps7_pll_init_data;
-extern unsigned long  * ps7_clock_init_data;
-extern unsigned long  * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT       0U
-#define OPCODE_CLEAR      1U
-#define OPCODE_WRITE      2U
-#define OPCODE_MASKWRITE  3U
-#define OPCODE_MASKPOLL   4U
-#define OPCODE_MASKDELAY  5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
-#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes  of PS7_Init */
-#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
-#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ  666666687
-#define DDR_FREQ  533333374
-#define DCI_FREQ  10158731
-#define QSPI_FREQ  200000000
-#define SMC_FREQ  10000000
-#define ENET0_FREQ  25000000
-#define ENET1_FREQ  10000000
-#define USB0_FREQ  60000000
-#define USB1_FREQ  60000000
-#define SDIO_FREQ  50000000
-#define UART_FREQ  50000000
-#define SPI_FREQ  10000000
-#define I2C_FREQ  111111115
-#define WDT_FREQ  111111115
-#define TTC_FREQ  50000000
-#define CAN_FREQ  10000000
-#define PCAP_FREQ  200000000
-#define TPIU_FREQ  200000000
-#define FPGA0_FREQ  50000000
-#define FPGA1_FREQ  50000000
-#define FPGA2_FREQ  50000000
-#define FPGA3_FREQ  50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
index f4f45becd6..54c803cfa6 100644
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
@@ -14,7 +14,7 @@
 *
 *****************************************************************************/
 
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
 
 unsigned long ps7_pll_init_data_3_0[] = {
     // START: top
@@ -4087,37 +4087,6 @@ unsigned long ps7_post_config_3_0[] = {
     //
 };
 
-unsigned long ps7_debug_3_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
 
 unsigned long ps7_pll_init_data_2_0[] = {
     // START: top
@@ -8351,37 +8320,6 @@ unsigned long ps7_post_config_2_0[] = {
     //
 };
 
-unsigned long ps7_debug_2_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
 
 unsigned long ps7_pll_init_data_1_0[] = {
     // START: top
@@ -12548,173 +12486,9 @@ unsigned long ps7_post_config_1_0[] = {
     //
 };
 
-unsigned long ps7_debug_1_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
 
 
 #include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
-  char* err_msg = "";
-  switch (key) {
-    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
-    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
-    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
-    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
-    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
-    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
-    default:                                err_msg = "Undefined error status"; break;
-  }
-
-  return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
-  // Read PS version from MCTRL register [31:28]
-  unsigned long mask = 0xF0000000;
-  unsigned long *addr = (unsigned long*) 0XF8007080;
-  unsigned long ps_version = (*addr & mask) >> 28;
-  return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
-        *addr = ( val & mask ) | ( *addr & ~mask);
-        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
-        volatile unsigned long *addr = (volatile unsigned long*) add;
-        int i = 0;
-        while (!(*addr & mask)) {
-          if (i == PS7_MASK_POLL_TIME) {
-            return -1;
-          }
-          i++;
-        }
-     return 1;
-        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
-        unsigned long val = (*addr & mask);
-        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
-        return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
-    unsigned long *ptr = ps7_config_init;
-
-    unsigned long  opcode;            // current instruction ..
-    unsigned long  args[16];           // no opcode has so many args ...
-    int  numargs;           // number of arguments of this instruction
-    int  j;                 // general purpose index
-
-    volatile unsigned long *addr;         // some variable to make code readable
-    unsigned long  val,mask;              // some variable to make code readable
-
-    int finish = -1 ;           // loop while this is negative !
-    int i = 0;                  // Timeout variable
-
-    while( finish < 0 ) {
-        numargs = ptr[0] & 0xF;
-        opcode = ptr[0] >> 4;
-
-        for( j = 0 ; j < numargs ; j ++ )
-            args[j] = ptr[j+1];
-        ptr += numargs + 1;
-
-
-        switch ( opcode ) {
-
-        case OPCODE_EXIT:
-            finish = PS7_INIT_SUCCESS;
-            break;
-
-        case OPCODE_CLEAR:
-            addr = (unsigned long*) args[0];
-            *addr = 0;
-            break;
-
-        case OPCODE_WRITE:
-            addr = (unsigned long*) args[0];
-            val = args[1];
-            *addr = val;
-            break;
-
-        case OPCODE_MASKWRITE:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            val = args[2];
-            *addr = ( val & mask ) | ( *addr & ~mask);
-            break;
-
-        case OPCODE_MASKPOLL:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            i = 0;
-            while (!(*addr & mask)) {
-                if (i == PS7_MASK_POLL_TIME) {
-                    finish = PS7_INIT_TIMEOUT;
-                    break;
-                }
-                i++;
-            }
-            break;
-        case OPCODE_MASKDELAY:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            int delay = get_number_of_cycles_for_delay(mask);
-            perf_reset_and_start_timer();
-            while ((*addr < delay)) {
-            }
-            break;
-        default:
-            finish = PS7_INIT_CORRUPT;
-            break;
-        }
-    }
-    return finish;
-}
 
 unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
 unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -12742,25 +12516,6 @@ ps7_post_config()
 }
 
 int
-ps7_debug()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_debug_1_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_debug_2_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_debug_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
 ps7_init()
 {
   // Get the PS_VERSION on run time
@@ -12821,41 +12576,3 @@ ps7_init()
 
 
 
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
-						      (1 << 3) | // Auto-increment
-						      (0 << 8) // Pre-scale
-	);
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
-	perf_disable_clock();
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
-  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
-  return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
-	    perf_reset_clock();
-	    perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
deleted file mode 100644
index 9b41e28697..0000000000
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
+++ /dev/null
@@ -1,117 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier:	GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int  u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long  * ps7_ddr_init_data;
-extern unsigned long  * ps7_mio_init_data;
-extern unsigned long  * ps7_pll_init_data;
-extern unsigned long  * ps7_clock_init_data;
-extern unsigned long  * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT       0U
-#define OPCODE_CLEAR      1U
-#define OPCODE_WRITE      2U
-#define OPCODE_MASKWRITE  3U
-#define OPCODE_MASKPOLL   4U
-#define OPCODE_MASKDELAY  5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
-#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes  of PS7_Init */
-#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
-#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ  666666687
-#define DDR_FREQ  533333374
-#define DCI_FREQ  10158731
-#define QSPI_FREQ  200000000
-#define SMC_FREQ  10000000
-#define ENET0_FREQ  125000000
-#define ENET1_FREQ  10000000
-#define USB0_FREQ  60000000
-#define USB1_FREQ  60000000
-#define SDIO_FREQ  50000000
-#define UART_FREQ  50000000
-#define SPI_FREQ  10000000
-#define I2C_FREQ  111111115
-#define WDT_FREQ  111111115
-#define TTC_FREQ  50000000
-#define CAN_FREQ  10000000
-#define PCAP_FREQ  200000000
-#define TPIU_FREQ  200000000
-#define FPGA0_FREQ  100000000
-#define FPGA1_FREQ  142857132
-#define FPGA2_FREQ  50000000
-#define FPGA3_FREQ  50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
index 83daf7bf15..84625f0746 100644
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
 
 unsigned long ps7_pll_init_data_3_0[] = {
 	/* START: top */
@@ -4141,37 +4141,6 @@ unsigned long ps7_post_config_3_0[] = {
 	/* */
 };
 
-unsigned long ps7_debug_3_0[] = {
-	/* START: top */
-	/* .. START: CROSS TRIGGER CONFIGURATIONS */
-	/* .. .. START: UNLOCKING CTI REGISTERS */
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. FINISH: UNLOCKING CTI REGISTERS */
-	/* .. .. START: ENABLING CTI MODULES AND CHANNELS */
-	/* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
-	/* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
-	/* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
-	/* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
 
 unsigned long ps7_pll_init_data_2_0[] = {
 	/* START: top */
@@ -8467,37 +8436,6 @@ unsigned long ps7_post_config_2_0[] = {
 	/* */
 };
 
-unsigned long ps7_debug_2_0[] = {
-	/* START: top */
-	/* .. START: CROSS TRIGGER CONFIGURATIONS */
-	/* .. .. START: UNLOCKING CTI REGISTERS */
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. FINISH: UNLOCKING CTI REGISTERS */
-	/* .. .. START: ENABLING CTI MODULES AND CHANNELS */
-	/* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
-	/* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
-	/* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
-	/* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
 
 unsigned long ps7_pll_init_data_1_0[] = {
 	/* START: top */
@@ -12726,178 +12664,8 @@ unsigned long ps7_post_config_1_0[] = {
 	/* */
 };
 
-unsigned long ps7_debug_1_0[] = {
-	/* START: top */
-	/* .. START: CROSS TRIGGER CONFIGURATIONS */
-	/* .. .. START: UNLOCKING CTI REGISTERS */
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. FINISH: UNLOCKING CTI REGISTERS */
-	/* .. .. START: ENABLING CTI MODULES AND CHANNELS */
-	/* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
-	/* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
-	/* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
-	/* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
 
 #include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char *getPS7MessageInfo(unsigned key)
-{
-	char *err_msg = "";
-	switch (key) {
-	case PS7_INIT_SUCCESS:
-		err_msg = "PS7 initialization successful";
-		break;
-	case PS7_INIT_CORRUPT:
-		err_msg = "PS7 init Data Corrupted";
-		break;
-	case PS7_INIT_TIMEOUT:
-		err_msg = "PS7 init mask poll timeout";
-		break;
-	case PS7_POLL_FAILED_DDR_INIT:
-		err_msg = "Mask Poll failed for DDR Init";
-		break;
-	case PS7_POLL_FAILED_DMA:
-		err_msg = "Mask Poll failed for PLL Init";
-		break;
-	case PS7_POLL_FAILED_PLL:
-		err_msg = "Mask Poll failed for DMA done bit";
-		break;
-	default:
-		err_msg = "Undefined error status";
-		break;
-	}
-
-	return err_msg;
-}
-
-unsigned long ps7GetSiliconVersion(void)
-{
-	/* Read PS version from MCTRL register [31:28] */
-	unsigned long mask = 0xF0000000;
-	unsigned long *addr = (unsigned long *)0XF8007080;
-	unsigned long ps_version = (*addr & mask) >> 28;
-	return ps_version;
-}
-
-void mask_write(unsigned long add, unsigned long mask, unsigned long val)
-{
-	unsigned long *addr = (unsigned long *)add;
-	*addr = (val & mask) | (*addr & ~mask);
-}
-
-int mask_poll(unsigned long add, unsigned long mask)
-{
-	volatile unsigned long *addr = (volatile unsigned long *)add;
-	int i = 0;
-	while (!(*addr & mask)) {
-		if (i == PS7_MASK_POLL_TIME)
-			return -1;
-		i++;
-	}
-	return 1;
-}
-
-unsigned long mask_read(unsigned long add, unsigned long mask)
-{
-	unsigned long *addr = (unsigned long *)add;
-	unsigned long val = (*addr & mask);
-	return val;
-}
-
-int ps7_config(unsigned long *ps7_config_init)
-{
-	unsigned long *ptr = ps7_config_init;
-
-	unsigned long opcode;	/* current instruction .. */
-	unsigned long args[16];	/* no opcode has so many args ... */
-	int numargs;		/* number of arguments of this instruction */
-	int j;			/* general purpose index */
-
-	volatile unsigned long *addr;	/* some variable to make code readable */
-	unsigned long val, mask;	/* some variable to make code readable */
-
-	int finish = -1;	/* loop while this is negative ! */
-	int i = 0;		/* Timeout variable */
-
-	while (finish < 0) {
-		numargs = ptr[0] & 0xF;
-		opcode = ptr[0] >> 4;
-
-		for (j = 0; j < numargs; j++)
-			args[j] = ptr[j + 1];
-		ptr += numargs + 1;
-
-		switch (opcode) {
-		case OPCODE_EXIT:
-			finish = PS7_INIT_SUCCESS;
-			break;
-
-		case OPCODE_CLEAR:
-			addr = (unsigned long *)args[0];
-			*addr = 0;
-			break;
-
-		case OPCODE_WRITE:
-			addr = (unsigned long *)args[0];
-			val = args[1];
-			*addr = val;
-			break;
-
-		case OPCODE_MASKWRITE:
-			addr = (unsigned long *)args[0];
-			mask = args[1];
-			val = args[2];
-			*addr = (val & mask) | (*addr & ~mask);
-			break;
-
-		case OPCODE_MASKPOLL:
-			addr = (unsigned long *)args[0];
-			mask = args[1];
-			i = 0;
-			while (!(*addr & mask)) {
-				if (i == PS7_MASK_POLL_TIME) {
-					finish = PS7_INIT_TIMEOUT;
-					break;
-				}
-				i++;
-			}
-			break;
-		case OPCODE_MASKDELAY:
-			addr = (unsigned long *)args[0];
-			mask = args[1];
-			int delay = get_number_of_cycles_for_delay(mask);
-			perf_reset_and_start_timer();
-			while ((*addr < delay))
-				;
-			break;
-		default:
-			finish = PS7_INIT_CORRUPT;
-			break;
-		}
-	}
-	return finish;
-}
 
 unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
 unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -12926,27 +12694,6 @@ int ps7_post_config(void)
 	return PS7_INIT_SUCCESS;
 }
 
-int ps7_debug(void)
-{
-	/* Get the PS_VERSION on run time */
-	unsigned long si_ver = ps7GetSiliconVersion();
-	int ret = -1;
-	if (si_ver == PCW_SILICON_VERSION_1) {
-		ret = ps7_config(ps7_debug_1_0);
-		if (ret != PS7_INIT_SUCCESS)
-			return ret;
-	} else if (si_ver == PCW_SILICON_VERSION_2) {
-		ret = ps7_config(ps7_debug_2_0);
-		if (ret != PS7_INIT_SUCCESS)
-			return ret;
-	} else {
-		ret = ps7_config(ps7_debug_3_0);
-		if (ret != PS7_INIT_SUCCESS)
-			return ret;
-	}
-	return PS7_INIT_SUCCESS;
-}
-
 int ps7_init(void)
 {
 	/* Get the PS_VERSION on run time */
@@ -13006,40 +12753,3 @@ int ps7_init(void)
 	return PS7_INIT_SUCCESS;
 }
 
-/* For delay calculation using global timer */
-
-/* start timer */
-void perf_start_clock(void)
-{
-	*(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) |	/* Timer Enable */
-							      (1 << 3) |	/* Auto-increment */
-							      (0 << 8)	/* Pre-scale */
-	    );
-}
-
-/* stop timer and reset timer count regs */
-void perf_reset_clock(void)
-{
-	perf_disable_clock();
-	*(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
-	*(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
-	/* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */
-	return APU_FREQ * delay / (2 * 1000);
-}
-
-/* stop timer */
-void perf_disable_clock(void)
-{
-	*(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer(void)
-{
-	perf_reset_clock();
-	perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
deleted file mode 100644
index 22d9fd9250..0000000000
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) Xilinx, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*typedef unsigned int  u32; */
-
-/** do we need to make this name more unique ? **/
-/*extern u32 ps7_init_data[]; */
-extern unsigned long *ps7_ddr_init_data;
-extern unsigned long *ps7_mio_init_data;
-extern unsigned long *ps7_pll_init_data;
-extern unsigned long *ps7_clock_init_data;
-extern unsigned long *ps7_peripherals_init_data;
-
-#define OPCODE_EXIT       0U
-#define OPCODE_CLEAR      1U
-#define OPCODE_WRITE      2U
-#define OPCODE_MASKWRITE  3U
-#define OPCODE_MASKPOLL   4U
-#define OPCODE_MASKDELAY  5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT()                   ((OPCODE_EXIT      << 4) | 0)
-#define EMIT_CLEAR(addr)              ((OPCODE_CLEAR     << 4) | 1) , addr
-#define EMIT_WRITE(addr, val)          ((OPCODE_WRITE     << 4) | 2) , addr, val
-#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
-#define EMIT_MASKPOLL(addr, mask)      ((OPCODE_MASKPOLL  << 4) | 2) , addr, mask
-#define EMIT_MASKDELAY(addr, mask)      ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
-
-/* Returns codes  of PS7_Init */
-#define PS7_INIT_SUCCESS   (0)	/* 0 is success in good old C */
-#define PS7_INIT_CORRUPT   (1)	/* 1 the data is corrupted, and slcr reg are in corrupted state now */
-#define PS7_INIT_TIMEOUT   (2)	/* 2 when a poll operation timed out */
-#define PS7_POLL_FAILED_DDR_INIT (3)	/* 3 when a poll operation timed out for ddr init */
-#define PS7_POLL_FAILED_DMA      (4)	/* 4 when a poll operation timed out for dma done bit */
-#define PS7_POLL_FAILED_PLL      (5)	/* 5 when a poll operation timed out for pll sequence init */
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ  650000000
-#define DDR_FREQ  525000000
-#define DCI_FREQ  10096154
-#define QSPI_FREQ  200000000
-#define SMC_FREQ  10000000
-#define ENET0_FREQ  125000000
-#define ENET1_FREQ  10000000
-#define USB0_FREQ  60000000
-#define USB1_FREQ  60000000
-#define SDIO_FREQ  50000000
-#define UART_FREQ  100000000
-#define SPI_FREQ  10000000
-#define I2C_FREQ  108333336
-#define WDT_FREQ  108333336
-#define TTC_FREQ  50000000
-#define CAN_FREQ  10000000
-#define PCAP_FREQ  200000000
-#define TPIU_FREQ  200000000
-#define FPGA0_FREQ  100000000
-#define FPGA1_FREQ  142857132
-#define FPGA2_FREQ  200000000
-#define FPGA3_FREQ  50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
-
-int ps7_config(unsigned long *);
-int ps7_init(void);
-int ps7_post_config(void);
-int ps7_debug(void);
-char *getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer(void);
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index d17868b0c2..f769db7e81 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -27,7 +27,8 @@ DECLARE_GLOBAL_DATA_PTR;
 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
 
 static const struct {
-	uint32_t id;
+	u32 id;
+	u32 ver;
 	char *name;
 } zynqmp_devices[] = {
 	{
@@ -35,33 +36,88 @@ static const struct {
 		.name = "3eg",
 	},
 	{
+		.id = 0x10,
+		.ver = 0x2c,
+		.name = "3cg",
+	},
+	{
 		.id = 0x11,
 		.name = "2eg",
 	},
 	{
+		.id = 0x11,
+		.ver = 0x2c,
+		.name = "2cg",
+	},
+	{
 		.id = 0x20,
 		.name = "5ev",
 	},
 	{
+		.id = 0x20,
+		.ver = 0x100,
+		.name = "5eg",
+	},
+	{
+		.id = 0x20,
+		.ver = 0x12c,
+		.name = "5cg",
+	},
+	{
 		.id = 0x21,
 		.name = "4ev",
 	},
 	{
+		.id = 0x21,
+		.ver = 0x100,
+		.name = "4eg",
+	},
+	{
+		.id = 0x21,
+		.ver = 0x12c,
+		.name = "4cg",
+	},
+	{
 		.id = 0x30,
 		.name = "7ev",
 	},
 	{
+		.id = 0x30,
+		.ver = 0x100,
+		.name = "7eg",
+	},
+	{
+		.id = 0x30,
+		.ver = 0x12c,
+		.name = "7cg",
+	},
+	{
 		.id = 0x38,
 		.name = "9eg",
 	},
 	{
+		.id = 0x38,
+		.ver = 0x2c,
+		.name = "9cg",
+	},
+	{
 		.id = 0x39,
 		.name = "6eg",
 	},
 	{
+		.id = 0x39,
+		.ver = 0x2c,
+		.name = "6cg",
+	},
+	{
 		.id = 0x40,
 		.name = "11eg",
 	},
+	{ /* For testing purpose only */
+		.id = 0x50,
+		.ver = 0x2c,
+		.name = "15cg",
+	},
 	{
 		.id = 0x50,
 		.name = "15eg",
@@ -74,6 +130,30 @@ static const struct {
 		.id = 0x59,
 		.name = "17eg",
 	},
+	{
+		.id = 0x61,
+		.name = "21dr",
+	},
+	{
+		.id = 0x63,
+		.name = "23dr",
+	},
+	{
+		.id = 0x65,
+		.name = "25dr",
+	},
+	{
+		.id = 0x64,
+		.name = "27dr",
+	},
+	{
+		.id = 0x60,
+		.name = "28dr",
+	},
+	{
+		.id = 0x62,
+		.name = "29dr",
+	},
 };
 #endif
 
@@ -95,6 +175,7 @@ int chip_id(unsigned char id)
 		 * regs[0][31:0]  = status of the operation
 		 * regs[0][63:32] = CSU.IDCODE register
 		 * regs[1][31:0]  = CSU.version register
+		 * regs[1][63:32] = CSU.IDCODE2 register
 		 */
 		switch (id) {
 		case IDCODE:
@@ -109,6 +190,11 @@ int chip_id(unsigned char id)
 			regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 			val = regs.regs[1];
 			break;
+		case IDCODE2:
+			regs.regs[1] = lower_32_bits(regs.regs[1]);
+			regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
+			val = regs.regs[1];
+			break;
 		default:
 			printf("%s, Invalid Req:0x%x\n", __func__, id);
 		}
@@ -136,11 +222,13 @@ int chip_id(unsigned char id)
 	!defined(CONFIG_SPL_BUILD)
 static char *zynqmp_get_silicon_idcode_name(void)
 {
-	uint32_t i, id;
+	u32 i, id, ver;
 
 	id = chip_id(IDCODE);
+	ver = chip_id(IDCODE2);
+
 	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
-		if (zynqmp_devices[i].id == id)
+		if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
 			return zynqmp_devices[i].name;
 	}
 	return "unknown";
@@ -226,9 +314,7 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 int dram_init_banksize(void)
 {
-	fdtdec_setup_memory_banksize();
-
-	return 0;
+	return fdtdec_setup_memory_banksize();
 }
 
 int dram_init(void)
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
new file mode 100644
index 0000000000..1cc86b862c
--- /dev/null
+++ b/configs/syzygy_hub_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="opalkelly"
+CONFIG_SYS_CONFIG_NAME="syzygy_hub"
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_EEPROM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0000000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index fc06dc93c5..38f2e4e5cc 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
@@ -38,6 +39,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xe0000000
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 6a5348ed50..a1e98b7bc3 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
@@ -39,6 +40,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xe0000000
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index d8f6fcf782..b51107725a 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
@@ -38,6 +39,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xe0000000
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 95665ecd2a..ff865f1bdc 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -72,6 +72,7 @@ CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=25000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 15f4cb7c6b..beb24346ba 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -62,6 +62,7 @@ CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 37b0185e4c..8c8201dfbb 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -60,6 +60,7 @@ CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 07be751882..34365c8cfe 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -45,3 +45,4 @@ CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index 4d0d394532..a9e7a879de 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
+CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -38,4 +39,9 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_DM_ETH=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
new file mode 100644
index 0000000000..bf27ca48db
--- /dev/null
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 rev1.0"
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_ISO_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SATA_CEVA=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_PCA953X=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index d8c79e03b3..80c5e49348 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -3,7 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102"
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revA"
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
 CONFIG_DEBUG_UART=y
@@ -65,6 +65,7 @@ CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 9dd8cc94a0..232532c995 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -3,7 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102"
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revB"
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
 CONFIG_DEBUG_UART=y
@@ -65,6 +65,7 @@ CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig
new file mode 100644
index 0000000000..fcf4635e3d
--- /dev/null
+++ b/configs/zynq_cc108_defconfig
@@ -0,0 +1,56 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0000000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
new file mode 100644
index 0000000000..86c5d4452e
--- /dev/null
+++ b/configs/zynq_cse_qspi_defconfig
@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0xFFFC0000
+# CONFIG_ZYNQ_DDRC_INIT is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
+CONFIG_DEBUG_UART=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_PROMPT="Zynq> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_SPL is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_CLK is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+# CONFIG_PARTITIONS is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_SPL_BLK is not set
+# CONFIG_ZYNQ_GPIO is not set
+# CONFIG_MMC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DEBUG_UART_ARM_DCC=y
+CONFIG_DEBUG_UART_BASE=0x0
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_ZYNQ_QSPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index ad0ecc65b0..a713314343 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -37,6 +37,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
@@ -45,6 +46,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index d4344d96dc..bbccfa5dce 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -32,9 +32,11 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig
index af959275fe..396c63f35c 100644
--- a/configs/zynq_z_turn_defconfig
+++ b/configs/zynq_z_turn_defconfig
@@ -33,6 +33,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
@@ -44,6 +45,7 @@ CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 5fd1ff093e..ee6462f21a 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_EEPROM=y
 CONFIG_CMD_DFU=y
@@ -41,10 +42,12 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
@@ -52,6 +55,7 @@ CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 8964f57e1d..52999debc1 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
+CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
@@ -11,6 +12,7 @@ CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_EEPROM=y
 CONFIG_CMD_DFU=y
@@ -40,14 +42,21 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index dbca4a62ef..bf334677c5 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
+CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
@@ -11,6 +12,7 @@ CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_FPGA_LOADBP=y
 CONFIG_CMD_FPGA_LOADFS=y
@@ -33,14 +35,20 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_SPI=y
 CONFIG_ZYNQ_QSPI=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index b1511d81f7..357b92b5fd 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_FPGA_LOADBP=y
 CONFIG_CMD_FPGA_LOADFS=y
@@ -27,7 +28,9 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
 # CONFIG_MMC is not set
 CONFIG_NAND=y
 CONFIG_NAND_ZYNQ=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 71b379add3..cce24b97a8 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_FPGA_LOADBP=y
 CONFIG_CMD_FPGA_LOADFS=y
@@ -27,6 +28,8 @@ CONFIG_CMD_CACHE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index 4ffb2f9718..869975c0df 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_FPGA_LOADBP=y
 CONFIG_CMD_FPGA_LOADFS=y
@@ -26,7 +27,14 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 17a8809dd2..d1d59e8e2f 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -10,6 +10,7 @@ CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
@@ -37,6 +38,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
@@ -45,6 +47,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 9157d0cb80..412646086f 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -41,6 +41,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
@@ -50,6 +51,7 @@ CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 5e4df19386..690d35c890 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1026,7 +1026,7 @@ void scsi_low_level_init(int busdevfunc)
 
 #ifndef CONFIG_SCSI_AHCI_PLAT
 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
-int achi_init_one_dm(struct udevice *dev)
+int ahci_init_one_dm(struct udevice *dev)
 {
 	struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 
@@ -1035,7 +1035,7 @@ int achi_init_one_dm(struct udevice *dev)
 #endif
 #endif
 
-int achi_start_ports_dm(struct udevice *dev)
+int ahci_start_ports_dm(struct udevice *dev)
 {
 	struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 
diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c
index b16304baed..029b7784f6 100644
--- a/drivers/ata/dwc_ahci.c
+++ b/drivers/ata/dwc_ahci.c
@@ -85,7 +85,7 @@ static int dwc_ahci_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
-	return achi_start_ports_dm(dev);
+	return ahci_start_ports_dm(dev);
 }
 
 static const struct udevice_id dwc_ahci_ids[] = {
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index 3ef7b49215..bae26898ba 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -118,11 +118,11 @@ static int sata_ceva_probe(struct udevice *dev)
 
 	ceva_init_sata(plat->base);
 
-	ret = achi_init_one_dm(dev);
+	ret = ahci_init_one_dm(dev);
 	if (ret)
 		return ret;
 
-	return achi_start_ports_dm(dev);
+	return ahci_start_ports_dm(dev);
 }
 
 static const struct udevice_id sata_ceva_ids[] = {
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index cbdbd2f973..47ec43500c 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -154,6 +154,13 @@ config NAND_ZYNQ
 	  This enables Nand driver support for Nand flash controller
 	  found on Zynq SoC.
 
+config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
+	bool "Enable use of 1st stage bootloader timing for NAND"
+	depends on NAND_ZYNQ
+	help
+	  This flag prevent U-boot reconfigure NAND flash controller and reuse
+	  the NAND timing from 1st stage bootloader.
+
 comment "Generic NAND options"
 
 # Enhance depends when converting drivers to Kconfig which use this config
diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c
index 948f05984c..076b878244 100644
--- a/drivers/mtd/nand/zynq_nand.c
+++ b/drivers/mtd/nand/zynq_nand.c
@@ -35,6 +35,8 @@
 				(0x1 << 4)   |	/* Clear interrupt */ \
 				(0x1 << 6))	/* Disable ECC interrupt */
 
+#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
+
 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
 #define ZYNQ_NAND_SET_CYCLES	((0x2 << 20) |	/* t_rr from nand_cycles */ \
 				(0x2 << 17)  |	/* t_ar from nand_cycles */ \
@@ -43,6 +45,7 @@
 				(0x2 << 8)   |	/* t_rea from nand_cycles */ \
 				(0x5 << 4)   |	/* t_wc from nand_cycles */ \
 				(0x5 << 0))	/* t_rc from nand_cycles */
+#endif
 
 
 #define ZYNQ_NAND_DIRECT_CMD	((0x4 << 23) |	/* Chip 0 from interface 1 */ \
@@ -81,6 +84,13 @@
 #define ZYNQ_NAND_ECC_BUSY	(1 << 6)	/* ECC block is busy */
 #define ZYNQ_NAND_ECC_MASK	0x00FFFFFF	/* ECC value mask */
 
+#ifndef NAND_CMD_LOCK_TIGHT
+#define NAND_CMD_LOCK_TIGHT 0x2c
+#endif
+
+#ifndef NAND_CMD_LOCK_STATUS
+#define NAND_CMD_LOCK_STATUS 0x7a
+#endif
 
 /* SMC register set */
 struct zynq_nand_smc_regs {
@@ -141,6 +151,11 @@ static const struct zynq_nand_command_format zynq_nand_commands[] = {
 	{NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
 	{NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
 	{NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
+	{NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
+	{NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
+	{NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
+	{NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
+	{NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
 	{NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
 	/* Add all the flash commands supported by the flash device */
 };
@@ -245,8 +260,10 @@ static int zynq_nand_init_nand_flash(int option)
 
 	/* disable interrupts */
 	writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
+#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
 	/* Initialize the NAND interface by setting cycles and operation mode */
 	writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
+#endif
 	if (option & NAND_BUSWIDTH_16)
 		writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
 	else
@@ -989,7 +1006,7 @@ static int zynq_nand_device_ready(struct mtd_info *mtd)
 	return 0;
 }
 
-static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
+int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
 {
 	struct zynq_nand_info *xnand;
 	struct mtd_info *mtd;
@@ -1175,12 +1192,14 @@ fail:
 	return err;
 }
 
+#ifdef CONFIG_SYS_NAND_SELF_INIT
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
-void board_nand_init(void)
+void __weak board_nand_init(void)
 {
 	struct nand_chip *nand = &nand_chip[0];
 
 	if (zynq_nand_init(nand, 0))
 		puts("ZYNQ NAND init failed\n");
 }
+#endif
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 25c66c6098..9a2a578ff9 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -14,6 +14,7 @@
 #include <asm/io.h>
 #include <phy.h>
 #include <miiphy.h>
+#include <wait_bit.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -50,6 +51,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define XAE_MDIO_DIV_DFT	29	/* Default MDIO clock divisor */
 
+#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK	0x007FFFFF /* Actual len */
+
 /* DMA macros */
 /* Bitmasks of XAXIDMA_CR_OFFSET register */
 #define XAXIDMA_CR_RUNSTOP_MASK	0x00000001 /* Start/stop DMA channel */
@@ -89,6 +92,7 @@ struct axidma_priv {
 	phy_interface_t interface;
 	struct phy_device *phydev;
 	struct mii_dev *bus;
+	u8 eth_hasnobuf;
 };
 
 /* BD descriptors */
@@ -152,7 +156,7 @@ static inline int mdio_wait(struct axi_regs *regs)
 	u32 timeout = 200;
 
 	/* Wait till MDIO interface is ready to accept a new transaction. */
-	while (timeout && (!(in_be32(&regs->mdio_mcr)
+	while (timeout && (!(readl(&regs->mdio_mcr)
 						& XAE_MDIO_MCR_READY_MASK))) {
 		timeout--;
 		udelay(1);
@@ -180,13 +184,13 @@ static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
 			XAE_MDIO_MCR_INITIATE_MASK |
 			XAE_MDIO_MCR_OP_READ_MASK;
 
-	out_be32(&regs->mdio_mcr, mdioctrlreg);
+	writel(mdioctrlreg, &regs->mdio_mcr);
 
 	if (mdio_wait(regs))
 		return 1;
 
 	/* Read data */
-	*val = in_be32(&regs->mdio_mrd);
+	*val = readl(&regs->mdio_mrd);
 	return 0;
 }
 
@@ -207,9 +211,9 @@ static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
 			XAE_MDIO_MCR_OP_WRITE_MASK;
 
 	/* Write data */
-	out_be32(&regs->mdio_mwd, data);
+	writel(data, &regs->mdio_mwd);
 
-	out_be32(&regs->mdio_mcr, mdioctrlreg);
+	writel(mdioctrlreg, &regs->mdio_mcr);
 
 	if (mdio_wait(regs))
 		return 1;
@@ -233,7 +237,7 @@ static int axiemac_phy_init(struct udevice *dev)
 			SUPPORTED_1000baseT_Full;
 
 	/* Set default MDIO divisor */
-	out_be32(&regs->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
+	writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
 
 	if (priv->phyaddr == -1) {
 		/* Detect the PHY address */
@@ -312,12 +316,12 @@ static int setup_phy(struct udevice *dev)
 	}
 
 	/* Setup the emac for the phy speed */
-	emmc_reg = in_be32(&regs->emmc);
+	emmc_reg = readl(&regs->emmc);
 	emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
 	emmc_reg |= speed;
 
 	/* Write new speed setting out to Axi Ethernet */
-	out_be32(&regs->emmc, emmc_reg);
+	writel(emmc_reg, &regs->emmc);
 
 	/*
 	* Setting the operating speed of the MAC needs a delay. There
@@ -336,13 +340,13 @@ static void axiemac_stop(struct udevice *dev)
 	u32 temp;
 
 	/* Stop the hardware */
-	temp = in_be32(&priv->dmatx->control);
+	temp = readl(&priv->dmatx->control);
 	temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
-	out_be32(&priv->dmatx->control, temp);
+	writel(temp, &priv->dmatx->control);
 
-	temp = in_be32(&priv->dmarx->control);
+	temp = readl(&priv->dmarx->control);
 	temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
-	out_be32(&priv->dmarx->control, temp);
+	writel(temp, &priv->dmarx->control);
 
 	debug("axiemac: Halted\n");
 }
@@ -350,7 +354,7 @@ static void axiemac_stop(struct udevice *dev)
 static int axi_ethernet_init(struct axidma_priv *priv)
 {
 	struct axi_regs *regs = priv->iobase;
-	u32 timeout = 200;
+	int err;
 
 	/*
 	 * Check the status of the MgtRdy bit in the interrupt status
@@ -358,33 +362,39 @@ static int axi_ethernet_init(struct axidma_priv *priv)
 	 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
 	 * will be valid until this bit is valid.
 	 * The bit is always a 1 for all other PHY interfaces.
+	 * Interrupt status and enable registers are not available in non
+	 * processor mode and hence bypass in this mode
 	 */
-	while (timeout && (!(in_be32(&regs->is) & XAE_INT_MGTRDY_MASK))) {
-		timeout--;
-		udelay(1);
-	}
-	if (!timeout) {
-		printf("%s: Timeout\n", __func__);
-		return 1;
-	}
+	if (!priv->eth_hasnobuf) {
+		err = wait_for_bit(__func__, (const u32 *)&regs->is,
+				   XAE_INT_MGTRDY_MASK, true, 200, false);
+		if (err) {
+			printf("%s: Timeout\n", __func__);
+			return 1;
+		}
 
-	/* Stop the device and reset HW */
-	/* Disable interrupts */
-	out_be32(&regs->ie, 0);
+		/*
+		 * Stop the device and reset HW
+		 * Disable interrupts
+		 */
+		writel(0, &regs->ie);
+	}
 
 	/* Disable the receiver */
-	out_be32(&regs->rcw1, in_be32(&regs->rcw1) & ~XAE_RCW1_RX_MASK);
+	writel(readl(&regs->rcw1) & ~XAE_RCW1_RX_MASK, &regs->rcw1);
 
 	/*
 	 * Stopping the receiver in mid-packet causes a dropped packet
 	 * indication from HW. Clear it.
 	 */
-	/* Set the interrupt status register to clear the interrupt */
-	out_be32(&regs->is, XAE_INT_RXRJECT_MASK);
+	if (!priv->eth_hasnobuf) {
+		/* Set the interrupt status register to clear the interrupt */
+		writel(XAE_INT_RXRJECT_MASK, &regs->is);
+	}
 
 	/* Setup HW */
 	/* Set default MDIO divisor */
-	out_be32(&regs->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
+	writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
 
 	debug("axiemac: InitHw done\n");
 	return 0;
@@ -399,11 +409,11 @@ static int axiemac_write_hwaddr(struct udevice *dev)
 	/* Set the MAC address */
 	int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
 		(pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
-	out_be32(&regs->uaw0, val);
+	writel(val, &regs->uaw0);
 
 	val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
-	val |= in_be32(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
-	out_be32(&regs->uaw1, val);
+	val |= readl(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
+	writel(val, &regs->uaw1);
 	return 0;
 }
 
@@ -413,15 +423,15 @@ static void axi_dma_init(struct axidma_priv *priv)
 	u32 timeout = 500;
 
 	/* Reset the engine so the hardware starts from a known state */
-	out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
-	out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
+	writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
+	writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
 
 	/* At the initialization time, hardware should finish reset quickly */
 	while (timeout--) {
 		/* Check transmit/receive channel */
 		/* Reset is done when the reset bit is low */
-		if (!((in_be32(&priv->dmatx->control) |
-				in_be32(&priv->dmarx->control))
+		if (!((readl(&priv->dmatx->control) |
+				readl(&priv->dmarx->control))
 						& XAXIDMA_CR_RESET_MASK)) {
 			break;
 		}
@@ -450,12 +460,12 @@ static int axiemac_start(struct udevice *dev)
 		return -1;
 
 	/* Disable all RX interrupts before RxBD space setup */
-	temp = in_be32(&priv->dmarx->control);
+	temp = readl(&priv->dmarx->control);
 	temp &= ~XAXIDMA_IRQ_ALL_MASK;
-	out_be32(&priv->dmarx->control, temp);
+	writel(temp, &priv->dmarx->control);
 
 	/* Start DMA RX channel. Now it's ready to receive data.*/
-	out_be32(&priv->dmarx->current, (u32)&rx_bd);
+	writel((u32)&rx_bd, &priv->dmarx->current);
 
 	/* Setup the BD. */
 	memset(&rx_bd, 0, sizeof(rx_bd));
@@ -470,17 +480,17 @@ static int axiemac_start(struct udevice *dev)
 	flush_cache((u32)&rxframe, sizeof(rxframe));
 
 	/* Start the hardware */
-	temp = in_be32(&priv->dmarx->control);
+	temp = readl(&priv->dmarx->control);
 	temp |= XAXIDMA_CR_RUNSTOP_MASK;
-	out_be32(&priv->dmarx->control, temp);
+	writel(temp, &priv->dmarx->control);
 
 	/* Rx BD is ready - start */
-	out_be32(&priv->dmarx->tail, (u32)&rx_bd);
+	writel((u32)&rx_bd, &priv->dmarx->tail);
 
 	/* Enable TX */
-	out_be32(&regs->tc, XAE_TC_TX_MASK);
+	writel(XAE_TC_TX_MASK, &regs->tc);
 	/* Enable RX */
-	out_be32(&regs->rcw1, XAE_RCW1_RX_MASK);
+	writel(XAE_RCW1_RX_MASK, &regs->rcw1);
 
 	/* PHY setup */
 	if (!setup_phy(dev)) {
@@ -515,22 +525,22 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len)
 	/* Flush the last BD so DMA core could see the updates */
 	flush_cache((u32)&tx_bd, sizeof(tx_bd));
 
-	if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
+	if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
 		u32 temp;
-		out_be32(&priv->dmatx->current, (u32)&tx_bd);
+		writel((u32)&tx_bd, &priv->dmatx->current);
 		/* Start the hardware */
-		temp = in_be32(&priv->dmatx->control);
+		temp = readl(&priv->dmatx->control);
 		temp |= XAXIDMA_CR_RUNSTOP_MASK;
-		out_be32(&priv->dmatx->control, temp);
+		writel(temp, &priv->dmatx->control);
 	}
 
 	/* Start transfer */
-	out_be32(&priv->dmatx->tail, (u32)&tx_bd);
+	writel((u32)&tx_bd, &priv->dmatx->tail);
 
 	/* Wait for transmission to complete */
 	debug("axiemac: Waiting for tx to be done\n");
 	timeout = 200;
-	while (timeout && (!(in_be32(&priv->dmatx->status) &
+	while (timeout && (!(readl(&priv->dmatx->status) &
 			(XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
 		timeout--;
 		udelay(1);
@@ -549,10 +559,10 @@ static int isrxready(struct axidma_priv *priv)
 	u32 status;
 
 	/* Read pending interrupts */
-	status = in_be32(&priv->dmarx->status);
+	status = readl(&priv->dmarx->status);
 
 	/* Acknowledge pending interrupts */
-	out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
+	writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
 
 	/*
 	 * If Reception done interrupt is asserted, call RX call back function
@@ -577,11 +587,14 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
 	debug("axiemac: RX data ready\n");
 
 	/* Disable IRQ for a moment till packet is handled */
-	temp = in_be32(&priv->dmarx->control);
+	temp = readl(&priv->dmarx->control);
 	temp &= ~XAXIDMA_IRQ_ALL_MASK;
-	out_be32(&priv->dmarx->control, temp);
+	writel(temp, &priv->dmarx->control);
+	if (!priv->eth_hasnobuf)
+		length = rx_bd.app4 & 0xFFFF; /* max length mask */
+	else
+		length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
 
-	length = rx_bd.app4 & 0xFFFF; /* max length mask */
 #ifdef DEBUG
 	print_buffer(&rxframe, &rxframe[0], 1, length, 16);
 #endif
@@ -613,7 +626,7 @@ static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
 	flush_cache((u32)&rxframe, sizeof(rxframe));
 
 	/* Rx BD is ready - start again */
-	out_be32(&priv->dmarx->tail, (u32)&rx_bd);
+	writel((u32)&rx_bd, &priv->dmarx->tail);
 
 	debug("axiemac: RX completed, framelength = %d\n", length);
 
@@ -695,8 +708,8 @@ static int axi_emac_ofdata_to_platdata(struct udevice *dev)
 		printf("%s: axistream is not found\n", __func__);
 		return -EINVAL;
 	}
-	priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob,
-							  offset, "reg", 0);
+	priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
+							  offset, "reg");
 	if (!priv->dmatx) {
 		printf("%s: axi_dma register space not found\n", __func__);
 		return -EINVAL;
@@ -719,6 +732,9 @@ static int axi_emac_ofdata_to_platdata(struct udevice *dev)
 	}
 	priv->interface = pdata->phy_interface;
 
+	priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
+					     "xlnx,eth-hasnobuf");
+
 	printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
 	       priv->phyaddr, phy_string_for_interface(priv->interface));
 
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index f6bbcdc48e..1dfd631e1a 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -182,6 +182,7 @@ struct zynq_gem_priv {
 	int phy_of_handle;
 	struct mii_dev *bus;
 	struct clk clk;
+	bool int_pcs;
 };
 
 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
@@ -425,7 +426,12 @@ static int zynq_gem_init(struct udevice *dev)
 
 	nwconfig = ZYNQ_GEM_NWCFG_INIT;
 
-	if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
+	/*
+	 * Set SGMII enable PCS selection only if internal PCS/PMA
+	 * core is used and interface is SGMII.
+	 */
+	if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
+	    priv->int_pcs) {
 		nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
 			    ZYNQ_GEM_NWCFG_PCS_SEL;
 #ifdef CONFIG_ARM64
@@ -697,6 +703,9 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 	}
 	priv->interface = pdata->phy_interface;
 
+	priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
+					"is-internal-pcspma");
+
 	printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
 	       priv->phyaddr, phy_string_for_interface(priv->interface));
 
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 7c54a49bb3..122b8e786a 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -537,6 +537,13 @@ config STM32X7_SERIAL
 	  enable its onboard serial ports, say Y to this option.
 	  If unsure, say N.
 
+config ZYNQ_SERIAL
+	bool "Cadence (Xilinx Zynq) UART support"
+	depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+	help
+	  This driver supports the Cadence UART. It is found e.g. in Xilinx
+	  Zynq/ZynqMP.
+
 config MPC8XX_CONS
 	bool "Console driver for MPC8XX"
 	depends on 8xx
diff --git a/include/ahci.h b/include/ahci.h
index 33171b7ffd..cc36d81f98 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -234,18 +234,18 @@ int ahci_init(void __iomem *base);
 int ahci_reset(void __iomem *base);
 
 /**
- * achi_init_one_dm() - set up a single AHCI port
+ * ahci_init_one_dm() - set up a single AHCI port
  *
  * @dev: Controller to init
  */
-int achi_init_one_dm(struct udevice *dev);
+int ahci_init_one_dm(struct udevice *dev);
 
 /**
- * achi_start_ports_dm() - start all AHCI ports for a controller
+ * ahci_start_ports_dm() - start all AHCI ports for a controller
  *
  * @dev: Controller containing ports to start
  */
-int achi_start_ports_dm(struct udevice *dev);
+int ahci_start_ports_dm(struct udevice *dev);
 
 /**
  * ahci_init_dm() - init AHCI for a controller, finding all ports
diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h
new file mode 100644
index 0000000000..4147b45ef0
--- /dev/null
+++ b/include/configs/syzygy_hub.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2012 Xilinx
+ * (C) Copyright 2017 Opal Kelly Inc.
+ *
+ * Configuration settings for the SYZYGY Hub development board
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_SYZYGY_HUB_H
+#define __CONFIG_SYZYGY_HUB_H
+
+#define CONFIG_ZYNQ_I2C1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_ZYNQ_GEM_EEPROM_ADDR    0x57
+#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA
+
+#define CONFIG_EXTRA_ENV_SETTINGS       \
+	"fit_image=fit.itb\0"		\
+	"bitstream_image=download.bit\0"    \
+	"loadbit_addr=0x1000000\0"      \
+	"load_addr=0x2000000\0"		\
+	"fit_size=0x800000\0"		\
+	"flash_off=0x100000\0"		\
+	"nor_flash_off=0xE2100000\0"	\
+	"fdt_high=0x20000000\0"		\
+	"initrd_high=0x20000000\0"	\
+	"loadbootenv_addr=0x2000000\0"  \
+	"fdt_addr_r=0x1f00000\0"        \
+	"pxefile_addr_r=0x2000000\0"    \
+	"kernel_addr_r=0x2000000\0"     \
+	"scriptaddr=0x3000000\0"        \
+	"ramdisk_addr_r=0x3100000\0"    \
+	"bootenv=uEnv.txt\0" \
+	"bootenv_dev=mmc\0" \
+	"loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from ${bootenv_dev} ...; " \
+		"env import -t ${loadbootenv_addr} $filesize\0" \
+	"bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \
+	"setbootenv=if env run bootenv_existence_test; then " \
+			"if env run loadbootenv; then " \
+				"env run importbootenv; " \
+			"fi; " \
+		"fi; \0" \
+	"sd_loadbootenv=set bootenv_dev mmc && " \
+			"run setbootenv \0" \
+	"usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv\0" \
+	"preboot=if test $modeboot = sdboot; then " \
+			"run sd_loadbootenv; " \
+			"echo Checking if uenvcmd is set ...; " \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...; " \
+				"run uenvcmd; " \
+			"fi; " \
+		"fi; \0" \
+	"sdboot=echo Copying FPGA Bitstream from SD to RAM... && " \
+		"load mmc 0 ${loadbit_addr} ${bitstream_image} && " \
+		"echo Programming FPGA... && " \
+		"fpga loadb 0 ${loadbit_addr} ${filesize} && " \
+		"echo Copying FIT from SD to RAM... && " \
+		"load mmc 0 ${load_addr} ${fit_image} && " \
+		"bootm ${load_addr}\0" \
+	"jtagboot=echo TFTPing FIT to RAM... && " \
+		"tftpboot ${load_addr} ${fit_image} && " \
+		"bootm ${load_addr}\0" \
+		DFU_ALT_INFO \
+		BOOTENV
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_SYZYGY_HUB_H */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 8526ba0e88..14604eb4e8 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -42,7 +42,6 @@
 /* Serial setup */
 #define CONFIG_ARM_DCC
 #define CONFIG_CPU_ARMV8
-#define CONFIG_ZYNQ_SERIAL
 
 #define CONFIG_CONS_INDEX		0
 #define CONFIG_SYS_BAUDRATE_TABLE \
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index b9599c73a6..7247c90307 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -33,7 +33,6 @@
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
 #define CONFIG_ARM_DCC
-#define CONFIG_ZYNQ_SERIAL
 
 /* Ethernet driver */
 #if defined(CONFIG_ZYNQ_GEM)
@@ -157,12 +156,6 @@
 
 /* Environment */
 #ifndef CONFIG_ENV_IS_NOWHERE
-# ifdef CONFIG_MTD_NOR_FLASH
-/* Environment in NOR flash */
-# elif defined(CONFIG_ZYNQ_QSPI)
-/* Environment in Serial Flash */
-# endif
-
 # define CONFIG_ENV_SECT_SIZE		CONFIG_ENV_SIZE
 # define CONFIG_ENV_OFFSET		0xE0000
 #endif
@@ -293,16 +286,11 @@
 					GENERATED_GBL_DATA_SIZE)
 
 /* Enable the PL to be downloaded */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_ZYNQPL
 
 /* FIT support */
 #define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
 
-/* FDT support */
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
 /* Extend size of kernel image for uncompression */
 #define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
 
@@ -325,7 +313,6 @@
 /* Disable dcache for SPL just for sure */
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_DCACHE_OFF
-#undef CONFIG_FPGA
 #endif
 
 /* Address in RAM where the parameters must be copied by SPL. */
diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h
new file mode 100644
index 0000000000..dd65b52343
--- /dev/null
+++ b/include/configs/zynq_cse.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2013 - 2017 Xilinx.
+ *
+ * Configuration settings for the Xilinx Zynq CSE board.
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_CSE_H
+#define __CONFIG_ZYNQ_CSE_H
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF
+
+#include <configs/zynq-common.h>
+
+/* Undef unneeded configs */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_BOOTCOMMAND
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_CMDLINE_EDITING
+#undef CONFIG_AUTO_COMPLETE
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+
+#undef CONFIG_SYS_LONGHELP
+
+#undef CONFIG_SYS_CBSIZE
+#undef CONFIG_BOOTM_VXWORKS
+#undef CONFIG_BOOTM_LINUX
+
+#define CONFIG_SYS_CBSIZE	1024
+
+#define CONFIG_ENV_SIZE		400
+#undef CONFIG_SYS_INIT_RAM_ADDR
+#undef CONFIG_SYS_INIT_RAM_SIZE
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFDE000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#undef CONFIG_SPL_BSS_START_ADDR
+#undef CONFIG_SPL_BSS_MAX_SIZE
+#define CONFIG_SPL_BSS_START_ADDR	0x20000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN	0x1000
+
+#define CONFIG_SYS_SDRAM_BASE	0xfffc0000
+#define CONFIG_SYS_SDRAM_SIZE	0x40000
+
+#endif /* __CONFIG_ZYNQ_CSE_H */
diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
new file mode 100644
index 0000000000..e1b81fe5ef
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
@@ -0,0 +1,30 @@
+/*
+ * MIO pin configuration defines for Xilinx ZynqMP
+ *
+ * Copyright (C) 2017 Xilinx, Inc.
+ * Author: Chirag Parekh <chirag.parekh@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
+#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
+
+/* Bit value for IO standards */
+#define IO_STANDARD_LVCMOS33      0
+#define IO_STANDARD_LVCMOS18      1
+
+/* Bit values for Slew Rates */
+#define SLEW_RATE_FAST            0
+#define SLEW_RATE_SLOW            1
+
+/* Bit values for Pin inputs */
+#define PIN_INPUT_TYPE_CMOS       0
+#define PIN_INPUT_TYPE_SCHMITT    1
+
+#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index ca044767a0..b5e7019ea3 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -167,7 +167,8 @@ ifdef CONFIG_ARCH_ZYNQ
 MKIMAGEFLAGS_boot.bin = -T zynqimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE)
 endif
 ifdef CONFIG_ARCH_ZYNQMP
-MKIMAGEFLAGS_boot.bin = -T zynqmpimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE)
+MKIMAGEFLAGS_boot.bin = -T zynqmpimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE) \
+	-n $(srctree)/$(CONFIG_PMUFW_INIT_FILE)
 endif
 
 spl/boot.bin: $(obj)/u-boot-spl.bin FORCE
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 8a0c95b7ee..4ce87484c3 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -5109,5 +5109,4 @@ CONFIG_ZYNQ_SDHCI0
 CONFIG_ZYNQ_SDHCI1
 CONFIG_ZYNQ_SDHCI_MAX_FREQ
 CONFIG_ZYNQ_SDHCI_MIN_FREQ
-CONFIG_ZYNQ_SERIAL
 CONFIG_eTSEC_MDIO_BUS
diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c
index 0c9a3daddd..9667b11b2f 100644
--- a/tools/zynqmpimage.c
+++ b/tools/zynqmpimage.c
@@ -6,7 +6,7 @@
  *
  * The following Boot Header format/structures and values are defined in the
  * following documents:
- *   * ug1085 ZynqMP TRM (Chapter 9, Table 9-3)
+ *   * ug1085 ZynqMP TRM doc v1.4 (Chapter 11, Table 11-4)
  *
  * Expected Header Size = 0x9C0
  * Forced as 'little' endian, 32-bit words
@@ -99,6 +99,8 @@ struct zynqmp_header {
 };
 
 static struct zynqmp_header zynqmpimage_header;
+static void *dynamic_header;
+static FILE *fpmu;
 
 static uint32_t zynqmpimage_checksum(struct zynqmp_header *ptr)
 {
@@ -181,6 +183,13 @@ static void zynqmpimage_print_header(const void *ptr)
 	printf("Image Size   : %lu bytes (%lu bytes packed)\n",
 	       (unsigned long)le32_to_cpu(zynqhdr->image_size),
 	       (unsigned long)le32_to_cpu(zynqhdr->image_stored_size));
+
+	if (zynqhdr->pfw_image_length)
+		printf("PMUFW Size   : %lu bytes (%lu bytes packed)\n",
+		       (unsigned long)le32_to_cpu(zynqhdr->pfw_image_length),
+		       (unsigned long)le32_to_cpu(
+				zynqhdr->total_pfw_image_length));
+
 	printf("Image Load   : 0x%08x\n", le32_to_cpu(zynqhdr->image_load));
 	printf("Checksum     : 0x%08x\n", le32_to_cpu(zynqhdr->checksum));
 
@@ -203,6 +212,8 @@ static void zynqmpimage_print_header(const void *ptr)
 		       le32_to_cpu(zynqhdr->register_init[i].address),
 		       le32_to_cpu(zynqhdr->register_init[i].data));
 	}
+
+	free(dynamic_header);
 }
 
 static int zynqmpimage_check_params(struct image_tool_params *params)
@@ -234,6 +245,44 @@ static int zynqmpimage_check_image_types(uint8_t type)
 	return EXIT_FAILURE;
 }
 
+static int fsize(FILE *fp)
+{
+	int size;
+	int origin = ftell(fp);
+
+	fseek(fp, 0L, SEEK_END);
+	size = ftell(fp);
+
+	/* going back */
+	fseek(fp, origin, SEEK_SET);
+
+	return size;
+}
+
+static void zynqmpimage_pmufw(struct zynqmp_header *zynqhdr,
+			      const char *filename)
+{
+	uint32_t size;
+
+	/* Setup PMU fw size */
+	zynqhdr->pfw_image_length = fsize(fpmu);
+	zynqhdr->total_pfw_image_length = zynqhdr->pfw_image_length;
+
+	zynqhdr->image_size -= zynqhdr->pfw_image_length;
+	zynqhdr->image_stored_size -= zynqhdr->total_pfw_image_length;
+
+	/* Read the whole PMUFW to the header */
+	size = fread(&zynqhdr->__reserved4[66], 1,
+		     zynqhdr->pfw_image_length, fpmu);
+	if (size != zynqhdr->pfw_image_length) {
+		fprintf(stderr, "Cannot read PMUFW file: %s\n", filename);
+		fclose(fpmu);
+		exit(1);
+	}
+
+	fclose(fpmu);
+}
+
 static void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr,
 	const char *filename)
 {
@@ -288,6 +337,10 @@ static void zynqmpimage_set_header(void *ptr, struct stat *sbuf, int ifd,
 	if (params->eflag)
 		zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);
 
+	/* PMUFW */
+	if (fpmu)
+		zynqmpimage_pmufw(zynqhdr, params->imagename);
+
 	/* User can pass in text file with init list */
 	if (strlen(params->imagename2))
 		zynqmpimage_parse_initparams(zynqhdr, params->imagename2);
@@ -295,6 +348,50 @@ static void zynqmpimage_set_header(void *ptr, struct stat *sbuf, int ifd,
 	zynqhdr->checksum = zynqmpimage_checksum(zynqhdr);
 }
 
+static int zynqmpimage_vrec_header(struct image_tool_params *params,
+				   struct image_type_params *tparams)
+{
+	struct stat path_stat;
+	char *filename = params->imagename;
+	int err;
+
+	/* Handle static case without PMUFW */
+	tparams->header_size = sizeof(struct zynqmp_header);
+	tparams->hdr = (void *)&zynqmpimage_header;
+
+	/* PMUFW name is passed via params->imagename */
+	if (strlen(filename) == 0)
+		return EXIT_SUCCESS;
+
+	fpmu = fopen(filename, "r");
+	if (!fpmu) {
+		fprintf(stderr, "Cannot open PMUFW file: %s\n", filename);
+		return EXIT_FAILURE;
+	}
+
+	err = fstat(fileno(fpmu), &path_stat);
+	if (err) {
+		fclose(fpmu);
+		fpmu = NULL;
+		return EXIT_FAILURE;
+	}
+
+	if (!S_ISREG(path_stat.st_mode)) {
+		fclose(fpmu);
+		fpmu = NULL;
+		return EXIT_FAILURE;
+	}
+
+	/* Increase header size by PMUFW file size */
+	tparams->header_size += fsize(fpmu);
+
+	/* Allocate buffer with space for PMUFW */
+	dynamic_header = calloc(1, tparams->header_size);
+	tparams->hdr = dynamic_header;
+
+	return EXIT_SUCCESS;
+}
+
 U_BOOT_IMAGE_TYPE(
 	zynqmpimage,
 	"Xilinx ZynqMP Boot Image support",
@@ -307,5 +404,5 @@ U_BOOT_IMAGE_TYPE(
 	NULL,
 	zynqmpimage_check_image_types,
 	NULL,
-	NULL
+	zynqmpimage_vrec_header
 );
author	Tom Rini <trini@konsulko.com>	2017-11-29 08:26:07 -0500
committer	Tom Rini <trini@konsulko.com>	2017-11-29 08:26:07 -0500
commit	b06c46de632c55f4c39d404c6f0f65e414b31050 (patch)
tree	dea1702529c8d33c5e70eb5eb6ecf7d08eed23b9
parent	fcc8250c2f7c982f3593a8eecf737f8e2c95f222 (diff)
parent	a04a5daae25a74ad2ac90b66667dac126242baa0 (diff)