Merge branch 'master' of git://git.denx.de/u-boot-socfpga

84 files changed, 4392 insertions, 1952 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0bc4322c51..76365ef313 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -907,7 +907,7 @@ config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
 	select ARCH_EARLY_INIT_R
 	select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
-	select ARM64 if TARGET_SOCFPGA_STRATIX10
+	select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
 	select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select DM
 	select DM_SERIAL
@@ -919,7 +919,7 @@ config ARCH_SOCFPGA
 	select SPL_LIBGENERIC_SUPPORT
 	select SPL_NAND_SUPPORT if SPL_NAND_DENALI
 	select SPL_OF_CONTROL
-	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
+	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
 	select SPL_SERIAL_SUPPORT
 	select SPL_SYSRESET
 	select SPL_WATCHDOG_SUPPORT
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 25dbda9dfc..08c5967b3a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -330,6 +330,7 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
+	socfpga_agilex_socdk.dtb			\
 	socfpga_arria5_socdk.dtb			\
 	socfpga_arria10_socdk_sdmmc.dtb			\
 	socfpga_cyclone5_mcvevk.dtb			\
diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
index 322c858c4b..d55460755f 100644
--- a/arch/arm/dts/socfpga-common-u-boot.dtsi
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -10,6 +10,10 @@
 	};
 };
 
+&clkmgr {
+	u-boot,dm-pre-reloc;
+};
+
 &rst {
 	u-boot,dm-pre-reloc;
 };
@@ -17,3 +21,7 @@
 &sdr {
 	u-boot,dm-pre-reloc;
 };
+
+&sysmgr {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 51a6a51b53..eda558f2fe 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -114,7 +114,7 @@
 			status = "disabled";
 		};
 
-		clkmgr@ffd04000 {
+		clkmgr: clkmgr@ffd04000 {
 				compatible = "altr,clk-mgr";
 				reg = <0xffd04000 0x1000>;
 
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
new file mode 100644
index 0000000000..f0528a9ad9
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+/{
+	memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+
+		ccu: cache-controller@f7000000 {
+			compatible = "arteris,ncore-ccu";
+			reg = <0xf7000000 0x100900>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
+&clkmgr {
+	u-boot,dm-pre-reloc;
+};
+
+&gmac1 {
+	altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+};
+
+&gmac2 {
+	altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+};
+
+&i2c0 {
+	reset-names = "i2c";
+};
+
+&i2c1 {
+	reset-names = "i2c";
+};
+
+&i2c2 {
+	reset-names = "i2c";
+};
+
+&i2c3 {
+	reset-names = "i2c";
+};
+
+&mmc {
+	resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+};
+
+&porta {
+	bank-name = "porta";
+};
+
+&portb {
+	bank-name = "portb";
+};
+
+&qspi {
+	u-boot,dm-pre-reloc;
+};
+
+&rst {
+	compatible = "altr,rst-mgr";
+	altr,modrst-offset = <0x20>;
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	compatible = "intel,sdr-ctl-agilex";
+	reg = <0xf8000400 0x80>,
+	      <0xf8010000 0x190>,
+	      <0xf8011000 0x500>;
+	resets = <&rst DDRSCH_RESET>;
+	u-boot,dm-pre-reloc;
+};
+
+&sysmgr {
+	compatible = "altr,sys-mgr", "syscon";
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
+
+&watchdog0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi
new file mode 100644
index 0000000000..179b4d5591
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex.dtsi
@@ -0,0 +1,622 @@
+// SPDX-License-Identifier:     GPL-2.0
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+/dts-v1/;
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/agilex-clock.h>
+
+/ {
+	compatible = "intel,socfpga-agilex";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		service_reserved: svcbuffer@0 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x0 0x0 0x1000000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x0>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x1>;
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x2>;
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x3>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <0 170 4>,
+			     <0 171 4>,
+			     <0 172 4>,
+			     <0 173 4>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>,
+				     <&cpu2>,
+				     <&cpu3>;
+		interrupt-parent = <&intc>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	intc: intc@fffc1000 {
+		compatible = "arm,gic-400", "arm,cortex-a15-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x0 0xfffc1000 0x0 0x1000>,
+		      <0x0 0xfffc2000 0x0 0x2000>,
+		      <0x0 0xfffc4000 0x0 0x2000>,
+		      <0x0 0xfffc6000 0x0 0x2000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		device_type = "soc";
+		interrupt-parent = <&intc>;
+		ranges = <0 0 0 0xffffffff>;
+
+		base_fpga_region {
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+			compatible = "fpga-region";
+			fpga-mgr = <&fpga_mgr>;
+		};
+
+		clkmgr: clock-controller@ffd10000 {
+			compatible = "intel,agilex-clkmgr";
+			reg = <0xffd10000 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		clocks {
+			cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
+				#clock-cells = <0>;
+				compatible = "fixed-clock";
+			};
+
+			cb_intosc_ls_clk: cb-intosc-ls-clk {
+				#clock-cells = <0>;
+				compatible = "fixed-clock";
+			};
+
+			f2s_free_clk: f2s-free-clk {
+				#clock-cells = <0>;
+				compatible = "fixed-clock";
+			};
+
+			osc1: osc1 {
+				#clock-cells = <0>;
+				compatible = "fixed-clock";
+			};
+
+			qspi_clk: qspi-clk {
+				#clock-cells = <0>;
+				compatible = "fixed-clock";
+				clock-frequency = <200000000>;
+			};
+		};
+		gmac0: ethernet@ff800000 {
+			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+			reg = <0xff800000 0x2000>;
+			interrupts = <0 90 4>;
+			interrupt-names = "macirq";
+			mac-address = [00 00 00 00 00 00];
+			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
+			reset-names = "stmmaceth", "stmmaceth-ocp";
+			tx-fifo-depth = <16384>;
+			rx-fifo-depth = <16384>;
+			snps,multicast-filter-bins = <256>;
+			iommus = <&smmu 1>;
+			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
+			clocks = <&clkmgr AGILEX_EMAC0_CLK>;
+			clock-names = "stmmaceth";
+			status = "disabled";
+		};
+
+		gmac1: ethernet@ff802000 {
+			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+			reg = <0xff802000 0x2000>;
+			interrupts = <0 91 4>;
+			interrupt-names = "macirq";
+			mac-address = [00 00 00 00 00 00];
+			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
+			reset-names = "stmmaceth", "stmmaceth-ocp";
+			tx-fifo-depth = <16384>;
+			rx-fifo-depth = <16384>;
+			snps,multicast-filter-bins = <256>;
+			iommus = <&smmu 2>;
+			altr,sysmgr-syscon = <&sysmgr 0x48 8>;
+			clocks = <&clkmgr AGILEX_EMAC1_CLK>;
+			clock-names = "stmmaceth";
+			status = "disabled";
+		};
+
+		gmac2: ethernet@ff804000 {
+			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+			reg = <0xff804000 0x2000>;
+			interrupts = <0 92 4>;
+			interrupt-names = "macirq";
+			mac-address = [00 00 00 00 00 00];
+			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
+			reset-names = "stmmaceth", "stmmaceth-ocp";
+			tx-fifo-depth = <16384>;
+			rx-fifo-depth = <16384>;
+			snps,multicast-filter-bins = <256>;
+			iommus = <&smmu 3>;
+			altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
+			clocks = <&clkmgr AGILEX_EMAC2_CLK>;
+			clock-names = "stmmaceth";
+			status = "disabled";
+		};
+
+		gpio0: gpio@ffc03200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xffc03200 0x100>;
+			resets = <&rst GPIO0_RESET>;
+			status = "disabled";
+
+			porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <24>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <0 110 4>;
+			};
+		};
+
+		gpio1: gpio@ffc03300 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xffc03300 0x100>;
+			resets = <&rst GPIO1_RESET>;
+			status = "disabled";
+
+			portb: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <24>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <0 111 4>;
+			};
+		};
+
+		i2c0: i2c@ffc02800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc02800 0x100>;
+			interrupts = <0 103 4>;
+			resets = <&rst I2C0_RESET>;
+			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@ffc02900 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc02900 0x100>;
+			interrupts = <0 104 4>;
+			resets = <&rst I2C1_RESET>;
+			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@ffc02a00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc02a00 0x100>;
+			interrupts = <0 105 4>;
+			resets = <&rst I2C2_RESET>;
+			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@ffc02b00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc02b00 0x100>;
+			interrupts = <0 106 4>;
+			resets = <&rst I2C3_RESET>;
+			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@ffc02c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc02c00 0x100>;
+			interrupts = <0 107 4>;
+			resets = <&rst I2C4_RESET>;
+			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+			status = "disabled";
+		};
+
+		mmc: dwmmc0@ff808000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "altr,socfpga-dw-mshc";
+			reg = <0xff808000 0x1000>;
+			interrupts = <0 96 4>;
+			fifo-depth = <0x400>;
+			resets = <&rst SDMMC_RESET>;
+			reset-names = "reset";
+			clocks = <&clkmgr AGILEX_L4_MP_CLK>,
+				 <&clkmgr AGILEX_SDMMC_CLK>;
+			clock-names = "biu", "ciu";
+			iommus = <&smmu 5>;
+			status = "disabled";
+		};
+
+		nand: nand@ffb90000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "altr,socfpga-denali-nand";
+			reg = <0xffb90000 0x10000>,
+			      <0xffb80000 0x1000>;
+			reg-names = "nand_data", "denali_reg";
+			interrupts = <0 97 4>;
+			resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
+			status = "disabled";
+		};
+
+		ocram: sram@ffe00000 {
+			compatible = "mmio-sram";
+			reg = <0xffe00000 0x40000>;
+		};
+
+		pdma: pdma@ffda0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0xffda0000 0x1000>;
+			interrupts = <0 81 4>,
+				     <0 82 4>,
+				     <0 83 4>,
+				     <0 84 4>,
+				     <0 85 4>,
+				     <0 86 4>,
+				     <0 87 4>,
+				     <0 88 4>,
+				     <0 89 4>;
+			#dma-cells = <1>;
+			#dma-channels = <8>;
+			#dma-requests = <32>;
+			resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
+			reset-names = "dma", "dma-ocp";
+			clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
+			clock-names = "apb_pclk";
+		};
+
+		rst: rstmgr@ffd11000 {
+			#reset-cells = <1>;
+			compatible = "altr,stratix10-rst-mgr";
+			reg = <0xffd11000 0x100>;
+		};
+
+		smmu: iommu@fa000000 {
+			compatible = "arm,mmu-500", "arm,smmu-v2";
+			reg = <0xfa000000 0x40000>;
+			#global-interrupts = <2>;
+			#iommu-cells = <1>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 128 4>,	/* Global Secure Fault */
+				<0 129 4>, /* Global Non-secure Fault */
+				/* Non-secure Context Interrupts (32) */
+				<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
+				<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
+				<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
+				<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
+				<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
+				<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
+				<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
+				<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
+			stream-match-mask = <0x7ff0>;
+			status = "disabled";
+		};
+
+		spi0: spi@ffda4000 {
+			compatible = "snps,dw-apb-ssi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xffda4000 0x1000>;
+			interrupts = <0 99 4>;
+			resets = <&rst SPIM0_RESET>;
+			reg-io-width = <4>;
+			num-cs = <4>;
+			clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
+			status = "disabled";
+		};
+
+		spi1: spi@ffda5000 {
+			compatible = "snps,dw-apb-ssi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xffda5000 0x1000>;
+			interrupts = <0 100 4>;
+			resets = <&rst SPIM1_RESET>;
+			reg-io-width = <4>;
+			num-cs = <4>;
+			clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
+			status = "disabled";
+		};
+
+		sysmgr: sysmgr@ffd12000 {
+			compatible = "altr,sys-mgr-s10","altr,sys-mgr";
+			reg = <0xffd12000 0x500>;
+		};
+
+		/* Local timer */
+		timer {
+			compatible = "arm,armv8-timer";
+			interrupts = <1 13 0xf08>,
+				     <1 14 0xf08>,
+				     <1 11 0xf08>,
+				     <1 10 0xf08>;
+		};
+
+		timer0: timer0@ffc03000 {
+			compatible = "snps,dw-apb-timer";
+			interrupts = <0 113 4>;
+			reg = <0xffc03000 0x100>;
+			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+			clock-names = "timer";
+		};
+
+		timer1: timer1@ffc03100 {
+			compatible = "snps,dw-apb-timer";
+			interrupts = <0 114 4>;
+			reg = <0xffc03100 0x100>;
+			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+			clock-names = "timer";
+		};
+
+		timer2: timer2@ffd00000 {
+			compatible = "snps,dw-apb-timer";
+			interrupts = <0 115 4>;
+			reg = <0xffd00000 0x100>;
+			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+			clock-names = "timer";
+		};
+
+		timer3: timer3@ffd00100 {
+			compatible = "snps,dw-apb-timer";
+			interrupts = <0 116 4>;
+			reg = <0xffd00100 0x100>;
+			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+			clock-names = "timer";
+		};
+
+		uart0: serial0@ffc02000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xffc02000 0x100>;
+			interrupts = <0 108 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			resets = <&rst UART0_RESET>;
+			status = "disabled";
+			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+			clock-frequency = <100000000>;
+		};
+
+		uart1: serial1@ffc02100 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xffc02100 0x100>;
+			interrupts = <0 109 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			resets = <&rst UART1_RESET>;
+			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
+			status = "disabled";
+		};
+
+		usbphy0: usbphy@0 {
+			#phy-cells = <0>;
+			compatible = "usb-nop-xceiv";
+			status = "okay";
+		};
+
+		usb0: usb@ffb00000 {
+			compatible = "snps,dwc2";
+			reg = <0xffb00000 0x40000>;
+			interrupts = <0 93 4>;
+			phys = <&usbphy0>;
+			phy-names = "usb2-phy";
+			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
+			reset-names = "dwc2", "dwc2-ecc";
+			clocks = <&clkmgr AGILEX_USB_CLK>;
+			iommus = <&smmu 6>;
+			status = "disabled";
+		};
+
+		usb1: usb@ffb40000 {
+			compatible = "snps,dwc2";
+			reg = <0xffb40000 0x40000>;
+			interrupts = <0 94 4>;
+			phys = <&usbphy0>;
+			phy-names = "usb2-phy";
+			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+			reset-names = "dwc2", "dwc2-ecc";
+			iommus = <&smmu 7>;
+			clocks = <&clkmgr AGILEX_USB_CLK>;
+			status = "disabled";
+		};
+
+		watchdog0: watchdog@ffd00200 {
+			compatible = "snps,dw-wdt";
+			reg = <0xffd00200 0x100>;
+			interrupts = <0 117 4>;
+			resets = <&rst WATCHDOG0_RESET>;
+			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
+			status = "disabled";
+		};
+
+		watchdog1: watchdog@ffd00300 {
+			compatible = "snps,dw-wdt";
+			reg = <0xffd00300 0x100>;
+			interrupts = <0 118 4>;
+			resets = <&rst WATCHDOG1_RESET>;
+			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
+			status = "disabled";
+		};
+
+		watchdog2: watchdog@ffd00400 {
+			compatible = "snps,dw-wdt";
+			reg = <0xffd00400 0x100>;
+			interrupts = <0 125 4>;
+			resets = <&rst WATCHDOG2_RESET>;
+			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
+			status = "disabled";
+		};
+
+		watchdog3: watchdog@ffd00500 {
+			compatible = "snps,dw-wdt";
+			reg = <0xffd00500 0x100>;
+			interrupts = <0 126 4>;
+			resets = <&rst WATCHDOG3_RESET>;
+			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
+			status = "disabled";
+		};
+
+		sdr: sdr@f8011100 {
+			compatible = "altr,sdr-ctl", "syscon";
+			reg = <0xf8011100 0xc0>;
+		};
+
+		eccmgr {
+			compatible = "altr,socfpga-s10-ecc-manager",
+				     "altr,socfpga-a10-ecc-manager";
+			altr,sysmgr-syscon = <&sysmgr>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupts = <0 15 4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			ranges;
+
+			sdramedac {
+				compatible = "altr,sdram-edac-s10";
+				altr,sdr-syscon = <&sdr>;
+				interrupts = <16 4>;
+			};
+
+			ocram-ecc@ff8cc000 {
+				compatible = "altr,socfpga-s10-ocram-ecc",
+					     "altr,socfpga-a10-ocram-ecc";
+				reg = <0xff8cc000 0x100>;
+				altr,ecc-parent = <&ocram>;
+				interrupts = <1 4>;
+			};
+
+			usb0-ecc@ff8c4000 {
+				compatible = "altr,socfpga-s10-usb-ecc",
+					     "altr,socfpga-usb-ecc";
+				reg = <0xff8c4000 0x100>;
+				altr,ecc-parent = <&usb0>;
+				interrupts = <2 4>;
+			};
+
+			emac0-rx-ecc@ff8c0000 {
+				compatible = "altr,socfpga-s10-eth-mac-ecc",
+					     "altr,socfpga-eth-mac-ecc";
+				reg = <0xff8c0000 0x100>;
+				altr,ecc-parent = <&gmac0>;
+				interrupts = <4 4>;
+			};
+
+			emac0-tx-ecc@ff8c0400 {
+				compatible = "altr,socfpga-s10-eth-mac-ecc",
+					     "altr,socfpga-eth-mac-ecc";
+				reg = <0xff8c0400 0x100>;
+				altr,ecc-parent = <&gmac0>;
+				interrupts = <5 4>;
+			};
+
+			sdmmca-ecc@ff8c8c00 {
+				compatible = "altr,socfpga-s10-sdmmc-ecc",
+					     "altr,socfpga-sdmmc-ecc";
+				reg = <0xff8c8c00 0x100>;
+				altr,ecc-parent = <&mmc>;
+				interrupts = <14 4>,
+					     <15 4>;
+			};
+		};
+
+		qspi: spi@ff8d2000 {
+			compatible = "cdns,qspi-nor";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xff8d2000 0x100>,
+			      <0xff900000 0x100000>;
+			interrupts = <0 3 4>;
+			cdns,fifo-depth = <128>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x00000000>;
+			clocks = <&qspi_clk>;
+
+			status = "disabled";
+		};
+
+		firmware {
+			svc {
+				compatible = "intel,stratix10-svc";
+				method = "smc";
+				memory-region = <&service_reserved>;
+
+				fpga_mgr: fpga-mgr {
+					compatible = "intel,stratix10-soc-fpga-mgr";
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
new file mode 100644
index 0000000000..1908be4b8b
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include "socfpga_agilex-u-boot.dtsi"
+
+/{
+	aliases {
+		spi0 = &qspi;
+		i2c0 = &i2c1;
+	};
+
+	memory {
+		/* 8GB */
+		reg = <0 0x00000000 0 0x80000000>,
+		      <2 0x80000000 1 0x80000000>;
+	};
+};
+
+&flash0 {
+	compatible = "jedec,spi-nor";
+	spi-tx-bus-width = <4>;
+	spi-rx-bus-width = <4>;
+	u-boot,dm-pre-reloc;
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&mmc {
+	drvsel = <3>;
+	smplsel = <0>;
+	u-boot,dm-pre-reloc;
+};
+
diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_agilex_socdk.dts
new file mode 100644
index 0000000000..bcdeecc0e0
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex_socdk.dts
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier:     GPL-2.0
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+	model = "SoCFPGA Agilex SoCDK";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		hps0 {
+			label = "hps_led0";
+			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+		};
+
+		hps1 {
+			label = "hps_led1";
+			gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+		};
+
+		hps2 {
+			label = "hps_led2";
+			gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0 0 0 0>;
+	};
+
+	soc {
+		clocks {
+			osc1 {
+				clock-frequency = <25000000>;
+			};
+		};
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&phy0>;
+
+	max-frame-size = <9000>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy0: ethernet-phy@0 {
+			reg = <4>;
+
+			txd0-skew-ps = <0>; /* -420ps */
+			txd1-skew-ps = <0>; /* -420ps */
+			txd2-skew-ps = <0>; /* -420ps */
+			txd3-skew-ps = <0>; /* -420ps */
+			rxd0-skew-ps = <420>; /* 0ps */
+			rxd1-skew-ps = <420>; /* 0ps */
+			rxd2-skew-ps = <420>; /* 0ps */
+			rxd3-skew-ps = <420>; /* 0ps */
+			txen-skew-ps = <0>; /* -420ps */
+			txc-skew-ps = <900>; /* 0ps */
+			rxdv-skew-ps = <420>; /* 0ps */
+			rxc-skew-ps = <1680>; /* 780ps */
+		};
+	};
+};
+
+&mmc {
+	status = "okay";
+	cap-sd-highspeed;
+	broken-cd;
+	bus-width = <4>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	disable-over-current;
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&qspi {
+	flash0: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "mt25qu02g";
+		reg = <0>;
+		spi-max-frequency = <100000000>;
+
+		m25p,fast-read;
+		cdns,page-size = <256>;
+		cdns,block-size = <16>;
+		cdns,read-delay = <1>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qspi_boot: partition@0 {
+				label = "Boot and fpga data";
+				reg = <0x0 0x034B0000>;
+			};
+
+			qspi_rootfs: partition@34B0000 {
+				label = "Root Filesystem - JFFS2";
+				reg = <0x034B0000 0x0EB50000>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index c11a5c0cc1..cc529bcd11 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -96,7 +96,7 @@
 			fpga-mgr = <&fpga_mgr>;
 		};
 
-		clkmgr@ffd04000 {
+		clkmgr: clkmgr@ffd04000 {
 				compatible = "altr,clk-mgr";
 				reg = <0xffd04000 0x1000>;
 				u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index 6e5578d7bd..ef10708ee8 100644
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -180,3 +180,11 @@
 &l4_sp_clk {
 	u-boot,dm-pre-reloc;
 };
+
+&clkmgr {
+	u-boot,dm-pre-reloc;
+};
+
+&sysmgr {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
index bd68a78a37..a8e61cf728 100755
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -82,7 +82,7 @@
 		ranges = <0 0 0 0xffffffff>;
 		u-boot,dm-pre-reloc;
 
-		clkmgr@ffd1000 {
+		clkmgr: clkmgr@ffd10000 {
 			compatible = "altr,clk-mgr";
 			reg = <0xffd10000 0x1000>;
 		};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
index e1cfb522bf..38855aecd7 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -11,6 +11,10 @@
 	};
 };
 
+&clkmgr {
+	u-boot,dm-pre-reloc;
+};
+
 &qspi {
 	status = "okay";
 	u-boot,dm-pre-reloc;
@@ -23,3 +27,7 @@
 	spi-rx-bus-width = <4>;
 	u-boot,dm-pre-reloc;
 };
+
+&sysmgr {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 3770e07258..969698c83f 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -29,6 +29,15 @@ config SYS_TEXT_BASE
 	default 0x01000040 if TARGET_SOCFPGA_ARRIA10
 	default 0x01000040 if TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_AGILEX
+	bool
+	select ARMV8_MULTIENTRY
+	select ARMV8_SET_SMPEN
+	select ARMV8_SPIN_TABLE
+	select CLK
+	select NCORE_CACHE
+	select SPL_CLK if SPL
+
 config TARGET_SOCFPGA_ARRIA5
 	bool
 	select TARGET_SOCFPGA_GEN5
@@ -75,6 +84,10 @@ choice
 	prompt "Altera SOCFPGA board select"
 	optional
 
+config TARGET_SOCFPGA_AGILEX_SOCDK
+	bool "Intel SOCFPGA SoCDK (Agilex)"
+	select TARGET_SOCFPGA_AGILEX
+
 config TARGET_SOCFPGA_ARIES_MCVEVK
 	bool "Aries MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -135,6 +148,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
 endchoice
 
 config SYS_BOARD
+	default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -151,6 +165,7 @@ config SYS_BOARD
 	default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 
 config SYS_VENDOR
+	default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -168,6 +183,7 @@ config SYS_SOC
 	default "socfpga"
 
 config SYS_CONFIG_NAME
+	default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index fc1181cb27..418f543b20 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -39,6 +39,18 @@ obj-y	+= wrap_pinmux_config_s10.o
 obj-y	+= wrap_pll_config_s10.o
 endif
 
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y	+= clock_manager_agilex.o
+obj-y	+= mailbox_s10.o
+obj-y	+= misc_s10.o
+obj-y	+= mmu-arm64_s10.o
+obj-y	+= reset_manager_s10.o
+obj-y	+= system_manager_s10.o
+obj-y	+= timer_s10.o
+obj-y	+= wrap_pinmux_config_s10.o
+obj-y	+= wrap_pll_config_s10.o
+endif
+
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y	+= spl_gen5.o
@@ -51,8 +63,13 @@ ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
 obj-y	+= spl_a10.o
 endif
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y	+= firewall.o
 obj-y	+= spl_s10.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y	+= firewall.o
+obj-y	+= spl_agilex.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index 9f3c643df8..dbb10ecb68 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -10,18 +10,17 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_clock_manager *clock_manager_base =
-	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
 void cm_wait_for_lock(u32 mask)
 {
 	u32 inter_val;
 	u32 retry = 0;
 	do {
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-		inter_val = readl(&clock_manager_base->inter) & mask;
+		inter_val = readl(socfpga_get_clkmgr_addr() +
+				  CLKMGR_INTER) & mask;
 #else
-		inter_val = readl(&clock_manager_base->stat) & mask;
+		inter_val = readl(socfpga_get_clkmgr_addr() +
+				  CLKMGR_STAT) & mask;
 #endif
 		/* Wait for stable lock */
 		if (inter_val == mask)
@@ -36,8 +35,9 @@ void cm_wait_for_lock(u32 mask)
 /* function to poll in the fsm busy bit */
 int cm_wait_for_fsm(void)
 {
-	return wait_for_bit_le32(&clock_manager_base->stat,
-				 CLKMGR_STAT_BUSY, false, 20000, false);
+	return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
+				 CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
+				 false);
 }
 
 int set_cpu_clk_info(void)
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c
new file mode 100644
index 0000000000..791066d25b
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/agilex-clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong cm_get_rate_dm(u32 id)
+{
+	struct udevice *dev;
+	struct clk clk;
+	ulong rate;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_CLK,
+					  DM_GET_DRIVER(socfpga_agilex_clk),
+					  &dev);
+	if (ret)
+		return 0;
+
+	clk.id = id;
+	ret = clk_request(dev, &clk);
+	if (ret < 0)
+		return 0;
+
+	rate = clk_get_rate(&clk);
+
+	clk_free(&clk);
+
+	if ((rate == (unsigned long)-ENOSYS) ||
+	    (rate == (unsigned long)-ENXIO) ||
+	    (rate == (unsigned long)-EIO)) {
+		debug("%s id %u: clk_get_rate err: %ld\n",
+		      __func__, id, rate);
+		return 0;
+	}
+
+	return rate;
+}
+
+static u32 cm_get_rate_dm_khz(u32 id)
+{
+	return cm_get_rate_dm(id) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	return cm_get_rate_dm(AGILEX_MPU_CLK);
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+	return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
+}
+
+u32 cm_get_qspi_controller_clk_hz(void)
+{
+	return readl(socfpga_get_sysmgr_addr() +
+		     SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+}
+
+void cm_print_clock_quick_summary(void)
+{
+	printf("MPU       %10d kHz\n",
+	       cm_get_rate_dm_khz(AGILEX_MPU_CLK));
+	printf("L4 Main	    %8d kHz\n",
+	       cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
+	printf("L4 sys free %8d kHz\n",
+	       cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
+	printf("L4 MP       %8d kHz\n",
+	       cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
+	printf("L4 SP       %8d kHz\n",
+	       cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
+	printf("SDMMC       %8d kHz\n",
+	       cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
+}
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 334a79fd9c..392f2eb915 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -231,9 +231,6 @@ static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
 	return 0;
 }
 
-static const struct socfpga_clock_manager *clock_manager_base =
-	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
 /* calculate the intended main VCO frequency based on handoff */
 static unsigned int cm_calc_handoff_main_vco_clk_hz
 					(struct mainpll_cfg *main_cfg)
@@ -551,12 +548,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
 		writel((main_cfg->vco1_denom <<
 			CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 			cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
-			&clock_manager_base->main_pll.vco1);
+			socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 		mdelay(1);
 		cm_wait_for_lock(LOCKED_MASK);
 	}
 	writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
-		main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1);
+		main_cfg->vco1_numer,
+		socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 	mdelay(1);
 	cm_wait_for_lock(LOCKED_MASK);
 }
@@ -579,14 +577,18 @@ static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
 	/* execute the ramping here */
 	for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
 	     clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
-		writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
-			cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),
-			&clock_manager_base->per_pll.vco1);
+		writel((per_cfg->vco1_denom <<
+			      CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+			      cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
+						     clk_hz),
+			      socfpga_get_clkmgr_addr() +
+			      CLKMGR_A10_PERPLL_VCO1);
 		mdelay(1);
 		cm_wait_for_lock(LOCKED_MASK);
 	}
 	writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
-		per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1);
+		      per_cfg->vco1_numer,
+		      socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 	mdelay(1);
 	cm_wait_for_lock(LOCKED_MASK);
 }
@@ -638,16 +640,16 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 	/* gate off all mainpll clock excpet HW managed clock */
 	writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
 		CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
-		&clock_manager_base->main_pll.enr);
+		socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENR);
 
 	/* now we can gate off the rest of the peripheral clocks */
-	writel(0, &clock_manager_base->per_pll.en);
+	writel(0, socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EN);
 
 	/* Put all plls in external bypass */
 	writel(CLKMGR_MAINPLL_BYPASS_RESET,
-	       &clock_manager_base->main_pll.bypasss);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSS);
 	writel(CLKMGR_PERPLL_BYPASS_RESET,
-	       &clock_manager_base->per_pll.bypasss);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSS);
 
 	/*
 	 * Put all plls VCO registers back to reset value.
@@ -657,15 +659,17 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 	writel(CLKMGR_MAINPLL_VCO0_RESET |
 	       CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
 	       (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB),
-	       &clock_manager_base->main_pll.vco0);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0);
 
 	writel(CLKMGR_PERPLL_VCO0_RESET |
 	       CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
 	       (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB),
-	       &clock_manager_base->per_pll.vco0);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0);
 
-	writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1);
-	writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1);
+	writel(CLKMGR_MAINPLL_VCO1_RESET,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
+	writel(CLKMGR_PERPLL_VCO1_RESET,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 
 	/* clear the interrupt register status register */
 	writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
@@ -676,7 +680,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 		CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
 		CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
 		CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
-		&clock_manager_base->intr);
+		socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR);
 
 	/* Program VCO Numerator and Denominator for main PLL */
 	ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg);
@@ -687,14 +691,16 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 		else if (ramp_required == 2)
 			pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
 
-		writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+		writel((main_cfg->vco1_denom <<
+			CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 			cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
 					       pll_ramp_main_hz),
-			&clock_manager_base->main_pll.vco1);
+			socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 	} else
-		writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
-			main_cfg->vco1_numer,
-			&clock_manager_base->main_pll.vco1);
+		writel((main_cfg->vco1_denom <<
+		       CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+		       main_cfg->vco1_numer,
+		       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 
 	/* Program VCO Numerator and Denominator for periph PLL */
 	ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg);
@@ -707,23 +713,25 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 			pll_ramp_periph_hz =
 				CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
 
-		writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+		writel((per_cfg->vco1_denom <<
+			CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 			cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
 					       pll_ramp_periph_hz),
-			&clock_manager_base->per_pll.vco1);
+			socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 	} else
-		writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+		writel((per_cfg->vco1_denom <<
+			CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 			per_cfg->vco1_numer,
-			&clock_manager_base->per_pll.vco1);
+			socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 
 	/* Wait for at least 5 us */
 	udelay(5);
 
 	/* Now deassert BGPWRDN and PWRDN */
-	clrbits_le32(&clock_manager_base->main_pll.vco0,
+	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
 		     CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
 		     CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
-	clrbits_le32(&clock_manager_base->per_pll.vco0,
+	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
 		     CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
 		     CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
 
@@ -731,84 +739,92 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 	udelay(7);
 
 	/* enable the VCO and disable the external regulator to PLL */
-	writel((readl(&clock_manager_base->main_pll.vco0) &
+	writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
 		~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
 		CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
-		&clock_manager_base->main_pll.vco0);
-	writel((readl(&clock_manager_base->per_pll.vco0) &
+		socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0);
+	writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0) &
 		~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
 		CLKMGR_PERPLL_VCO0_EN_SET_MSK,
-		&clock_manager_base->per_pll.vco0);
+		socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0);
 
 	/* setup all the main PLL counter and clock source */
 	writel(main_cfg->nocclk,
-	       SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_NOCCLK);
 	writel(main_cfg->mpuclk,
-	       SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_MPUCLK);
 
 	/* main_emaca_clk divider */
-	writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk);
+	writel(main_cfg->cntr2clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR2CLK);
 	/* main_emacb_clk divider */
-	writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk);
+	writel(main_cfg->cntr3clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR3CLK);
 	/* main_emac_ptp_clk divider */
-	writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk);
+	writel(main_cfg->cntr4clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR4CLK);
 	/* main_gpio_db_clk divider */
-	writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk);
+	writel(main_cfg->cntr5clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR5CLK);
 	/* main_sdmmc_clk divider */
-	writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk);
+	writel(main_cfg->cntr6clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR6CLK);
 	/* main_s2f_user0_clk divider */
 	writel(main_cfg->cntr7clk_cnt |
 	       (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
-	       &clock_manager_base->main_pll.cntr7clk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR7CLK);
 	/* main_s2f_user1_clk divider */
-	writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk);
+	writel(main_cfg->cntr8clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR8CLK);
 	/* main_hmc_pll_clk divider */
 	writel(main_cfg->cntr9clk_cnt |
 	       (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
-	       &clock_manager_base->main_pll.cntr9clk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR9CLK);
 	/* main_periph_ref_clk divider */
 	writel(main_cfg->cntr15clk_cnt,
-	       &clock_manager_base->main_pll.cntr15clk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR15CLK);
 
 	/* setup all the peripheral PLL counter and clock source */
 	/* peri_emaca_clk divider */
 	writel(per_cfg->cntr2clk_cnt |
 	       (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
-	       &clock_manager_base->per_pll.cntr2clk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR2CLK);
 	/* peri_emacb_clk divider */
 	writel(per_cfg->cntr3clk_cnt |
 	       (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
-	       &clock_manager_base->per_pll.cntr3clk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR3CLK);
 	/* peri_emac_ptp_clk divider */
 	writel(per_cfg->cntr4clk_cnt |
 	       (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
-	       &clock_manager_base->per_pll.cntr4clk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR4CLK);
 	/* peri_gpio_db_clk divider */
 	writel(per_cfg->cntr5clk_cnt |
 	       (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
-	       &clock_manager_base->per_pll.cntr5clk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR5CLK);
 	/* peri_sdmmc_clk divider */
 	writel(per_cfg->cntr6clk_cnt |
 	       (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
-	       &clock_manager_base->per_pll.cntr6clk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR6CLK);
 	/* peri_s2f_user0_clk divider */
-	writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk);
+	writel(per_cfg->cntr7clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR7CLK);
 	/* peri_s2f_user1_clk divider */
 	writel(per_cfg->cntr8clk_cnt |
 	       (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
-	       &clock_manager_base->per_pll.cntr8clk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR8CLK);
 	/* peri_hmc_pll_clk divider */
-	writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk);
+	writel(per_cfg->cntr9clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR9CLK);
 
 	/* setup all the external PLL counter */
 	/* mpu wrapper / external divider */
 	writel(main_cfg->mpuclk_cnt |
 	       (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
-	       &clock_manager_base->main_pll.mpuclk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_MPUCLK);
 	/* NOC wrapper / external divider */
 	writel(main_cfg->nocclk_cnt |
 	       (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
-	       &clock_manager_base->main_pll.nocclk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCCLK);
 	/* NOC subclock divider such as l4 */
 	writel(main_cfg->nocdiv_l4mainclk |
 	       (main_cfg->nocdiv_l4mpclk <<
@@ -821,10 +837,10 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 		CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
 	       (main_cfg->nocdiv_cspdbclk <<
 		CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
-		&clock_manager_base->main_pll.nocdiv);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCDIV);
 	/* gpio_db external divider */
 	writel(per_cfg->gpiodiv_gpiodbclk,
-	       &clock_manager_base->per_pll.gpiodiv);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_GPIOFIV);
 
 	/* setup the EMAC clock mux select */
 	writel((per_cfg->emacctl_emac0sel <<
@@ -833,7 +849,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 		CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
 	       (per_cfg->emacctl_emac2sel <<
 		CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
-	       &clock_manager_base->per_pll.emacctl);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EMACCTL);
 
 	/* at this stage, check for PLL lock status */
 	cm_wait_for_lock(LOCKED_MASK);
@@ -843,33 +859,33 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 	 * assert/deassert outresetall
 	 */
 	/* assert mainpll outresetall */
-	setbits_le32(&clock_manager_base->main_pll.vco0,
+	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
 		     CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
 	/* assert perpll outresetall */
-	setbits_le32(&clock_manager_base->per_pll.vco0,
+	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
 		     CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
 	/* de-assert mainpll outresetall */
-	clrbits_le32(&clock_manager_base->main_pll.vco0,
+	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
 		     CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
 	/* de-assert perpll outresetall */
-	clrbits_le32(&clock_manager_base->per_pll.vco0,
+	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
 		     CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
 
 	/* Take all PLLs out of bypass when boot mode is cleared. */
 	/* release mainpll from bypass */
 	writel(CLKMGR_MAINPLL_BYPASS_RESET,
-	       &clock_manager_base->main_pll.bypassr);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSR);
 	/* wait till Clock Manager is not busy */
 	cm_wait_for_fsm();
 
 	/* release perpll from bypass */
 	writel(CLKMGR_PERPLL_BYPASS_RESET,
-	       &clock_manager_base->per_pll.bypassr);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSR);
 	/* wait till Clock Manager is not busy */
 	cm_wait_for_fsm();
 
 	/* clear boot mode */
-	clrbits_le32(&clock_manager_base->ctrl,
+	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
 		     CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
 	/* wait till Clock Manager is not busy */
 	cm_wait_for_fsm();
@@ -882,9 +898,10 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 
 	/* Now ungate non-hw-managed clocks */
 	writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
-		CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
-		&clock_manager_base->main_pll.ens);
-	writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens);
+	       CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENS);
+	writel(CLKMGR_PERPLL_EN_RESET,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_ENS);
 
 	/* Clear the loss lock and slip bits as they might set during
 	clock reconfiguration */
@@ -894,14 +911,14 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 	       CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
 	       CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
 	       CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
-	       &clock_manager_base->intr);
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR);
 
 	return 0;
 }
 
 static void cm_use_intosc(void)
 {
-	setbits_le32(&clock_manager_base->ctrl,
+	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
 		     CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
 }
 
diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c
index 54a821a27f..8fa2760798 100644
--- a/arch/arm/mach-socfpga/clock_manager_gen5.c
+++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
@@ -10,23 +10,20 @@
 #include <asm/arch/clock_manager.h>
 #include <wait_bit.h>
 
-static const struct socfpga_clock_manager *clock_manager_base =
-	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
 /*
  * function to write the bypass register which requires a poll of the
  * busy bit
  */
 static void cm_write_bypass(u32 val)
 {
-	writel(val, &clock_manager_base->bypass);
+	writel(val, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_BYPASS);
 	cm_wait_for_fsm();
 }
 
 /* function to write the ctrl register which requires a poll of the busy bit */
 static void cm_write_ctrl(u32 val)
 {
-	writel(val, &clock_manager_base->ctrl);
+	writel(val, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_CTRL);
 	cm_wait_for_fsm();
 }
 
@@ -80,8 +77,8 @@ int cm_basic_init(const struct cm_config * const cfg)
 	 * gatting off the rest of the periperal clocks.
 	 */
 	writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
-		readl(&clock_manager_base->per_pll.en),
-		&clock_manager_base->per_pll.en);
+		readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN),
+		socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN);
 
 	/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
 	writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
@@ -90,12 +87,12 @@ int cm_basic_init(const struct cm_config * const cfg)
 		CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
 		CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
 		CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
-		&clock_manager_base->main_pll.en);
+		socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_EN);
 
-	writel(0, &clock_manager_base->sdr_pll.en);
+	writel(0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_EN);
 
 	/* now we can gate off the rest of the peripheral clocks */
-	writel(0, &clock_manager_base->per_pll.en);
+	writel(0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN);
 
 	/* Put all plls in bypass */
 	cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
@@ -104,13 +101,13 @@ int cm_basic_init(const struct cm_config * const cfg)
 	/* Put all plls VCO registers back to reset value. */
 	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
 	       ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
-	       &clock_manager_base->main_pll.vco);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
 	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
 	       ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
-	       &clock_manager_base->per_pll.vco);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
 	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
 	       ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
-	       &clock_manager_base->sdr_pll.vco);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 
 	/*
 	 * The clocks to the flash devices and the L4_MAIN clocks can
@@ -120,23 +117,26 @@ int cm_basic_init(const struct cm_config * const cfg)
 	 * after exiting safe mode but before ungating the clocks.
 	 */
 	writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
-	       &clock_manager_base->per_pll.src);
+		      socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
 	writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
-	       &clock_manager_base->main_pll.l4src);
+		      socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC);
 
 	/* read back for the required 5 us delay. */
-	readl(&clock_manager_base->main_pll.vco);
-	readl(&clock_manager_base->per_pll.vco);
-	readl(&clock_manager_base->sdr_pll.vco);
+	readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
+	readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
+	readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 
 
 	/*
 	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
 	 * with numerator and denominator.
 	 */
-	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
-	writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
-	writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
+	writel(cfg->main_vco_base,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
+	writel(cfg->peri_vco_base,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
+	writel(cfg->sdram_vco_base,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 
 	/*
 	 * Time starts here. Must wait 7 us from
@@ -145,44 +145,55 @@ int cm_basic_init(const struct cm_config * const cfg)
 	end = timer_get_us() + 7;
 
 	/* main mpu */
-	writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
+	writel(cfg->mpuclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MPUCLK);
 
 	/* altera group mpuclk */
-	writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
+	writel(cfg->altera_grp_mpuclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_ALTR_MPUCLK);
 
 	/* main main clock */
-	writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
+	writel(cfg->mainclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINCLK);
 
 	/* main for dbg */
-	writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
+	writel(cfg->dbgatclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_DBGATCLK);
 
 	/* main for cfgs2fuser0clk */
 	writel(cfg->cfg2fuser0clk,
-	       &clock_manager_base->main_pll.cfgs2fuser0clk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK);
 
 	/* Peri emac0 50 MHz default to RMII */
-	writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
+	writel(cfg->emac0clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EMAC0CLK);
 
 	/* Peri emac1 50 MHz default to RMII */
-	writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
+	writel(cfg->emac1clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EMAC1CLK);
 
 	/* Peri QSPI */
-	writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
+	writel(cfg->mainqspiclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
 
-	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
+	writel(cfg->perqspiclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERQSPICLK);
 
 	/* Peri pernandsdmmcclk */
 	writel(cfg->mainnandsdmmcclk,
-	       &clock_manager_base->main_pll.mainnandsdmmcclk);
+	       socfpga_get_clkmgr_addr() +
+	       CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
 
 	writel(cfg->pernandsdmmcclk,
-	       &clock_manager_base->per_pll.pernandsdmmcclk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
 
 	/* Peri perbaseclk */
-	writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
+	writel(cfg->perbaseclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERBASECLK);
 
 	/* Peri s2fuser1clk */
-	writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
+	writel(cfg->s2fuser1clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_S2FUSER1CLK);
 
 	/* 7 us must have elapsed before we can enable the VCO */
 	while (timer_get_us() < end)
@@ -191,101 +202,112 @@ int cm_basic_init(const struct cm_config * const cfg)
 	/* Enable vco */
 	/* main pll vco */
 	writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-	       &clock_manager_base->main_pll.vco);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
 
 	/* periferal pll */
 	writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-	       &clock_manager_base->per_pll.vco);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
 
 	/* sdram pll vco */
 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-	       &clock_manager_base->sdr_pll.vco);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 
 	/* L3 MP and L3 SP */
-	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
+	writel(cfg->maindiv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINDIV);
 
-	writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
+	writel(cfg->dbgdiv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_DBGDIV);
 
-	writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
+	writel(cfg->tracediv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_TRACEDIV);
 
 	/* L4 MP, L4 SP, can0, and can1 */
-	writel(cfg->perdiv, &clock_manager_base->per_pll.div);
+	writel(cfg->perdiv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_DIV);
 
-	writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
+	writel(cfg->gpiodiv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_GPIODIV);
 
 	cm_wait_for_lock(LOCKED_MASK);
 
 	/* write the sdram clock counters before toggling outreset all */
 	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
-	       &clock_manager_base->sdr_pll.ddrdqsclk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
 
 	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
-	       &clock_manager_base->sdr_pll.ddr2xdqsclk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK);
 
 	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
-	       &clock_manager_base->sdr_pll.ddrdqclk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQCLK);
 
 	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
-	       &clock_manager_base->sdr_pll.s2fuser2clk);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK);
 
 	/*
 	 * after locking, but before taking out of bypass
 	 * assert/deassert outresetall
 	 */
-	u32 mainvco = readl(&clock_manager_base->main_pll.vco);
+	u32 mainvco = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_MAINPLL_VCO);
 
 	/* assert main outresetall */
 	writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
-	       &clock_manager_base->main_pll.vco);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
 
-	u32 periphvco = readl(&clock_manager_base->per_pll.vco);
+	u32 periphvco = readl(socfpga_get_clkmgr_addr() +
+			      CLKMGR_GEN5_PERPLL_VCO);
 
 	/* assert pheriph outresetall */
 	writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
-	       &clock_manager_base->per_pll.vco);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
 
 	/* assert sdram outresetall */
-	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
-		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
-		&clock_manager_base->sdr_pll.vco);
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN |
+	       CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 
 	/* deassert main outresetall */
 	writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
-	       &clock_manager_base->main_pll.vco);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
 
 	/* deassert pheriph outresetall */
 	writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
-	       &clock_manager_base->per_pll.vco);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
 
 	/* deassert sdram outresetall */
 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-	       &clock_manager_base->sdr_pll.vco);
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 
 	/*
 	 * now that we've toggled outreset all, all the clocks
 	 * are aligned nicely; so we can change any phase.
 	 */
 	ret = cm_write_with_phase(cfg->ddrdqsclk,
-				  &clock_manager_base->sdr_pll.ddrdqsclk,
+				  (const void *)(socfpga_get_clkmgr_addr() +
+				  CLKMGR_GEN5_SDRPLL_DDRDQSCLK),
 				  CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
 	if (ret)
 		return ret;
 
 	/* SDRAM DDR2XDQSCLK */
 	ret = cm_write_with_phase(cfg->ddr2xdqsclk,
-				  &clock_manager_base->sdr_pll.ddr2xdqsclk,
+				  (const void *)(socfpga_get_clkmgr_addr() +
+				  CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK),
 				  CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
 	if (ret)
 		return ret;
 
 	ret = cm_write_with_phase(cfg->ddrdqclk,
-				  &clock_manager_base->sdr_pll.ddrdqclk,
+				  (const void *)(socfpga_get_clkmgr_addr() +
+				  CLKMGR_GEN5_SDRPLL_DDRDQCLK),
 				  CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
 	if (ret)
 		return ret;
 
 	ret = cm_write_with_phase(cfg->s2fuser2clk,
-				  &clock_manager_base->sdr_pll.s2fuser2clk,
+				  (const void *)(socfpga_get_clkmgr_addr() +
+				  CLKMGR_GEN5_SDRPLL_S2FUSER2CLK),
 				  CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
 	if (ret)
 		return ret;
@@ -294,24 +316,28 @@ int cm_basic_init(const struct cm_config * const cfg)
 	cm_write_bypass(0);
 
 	/* clear safe mode */
-	cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
+	cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_CTRL) |
+		      CLKMGR_CTRL_SAFEMODE);
 
 	/*
 	 * now that safe mode is clear with clocks gated
 	 * it safe to change the source mux for the flashes the the L4_MAIN
 	 */
-	writel(cfg->persrc, &clock_manager_base->per_pll.src);
-	writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
+	writel(cfg->persrc,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
+	writel(cfg->l4src,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC);
 
 	/* Now ungate non-hw-managed clocks */
-	writel(~0, &clock_manager_base->main_pll.en);
-	writel(~0, &clock_manager_base->per_pll.en);
-	writel(~0, &clock_manager_base->sdr_pll.en);
+	writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_EN);
+	writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN);
+	writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_EN);
 
 	/* Clear the loss of lock bits (write 1 to clear) */
-	writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
-	       CLKMGR_INTER_MAINPLLLOST_MASK,
-	       &clock_manager_base->inter);
+	writel(CLKMGR_INTER_SDRPLLLOST_MASK |
+		      CLKMGR_INTER_PERPLLLOST_MASK |
+		      CLKMGR_INTER_MAINPLLLOST_MASK,
+		      socfpga_get_clkmgr_addr() + CLKMGR_GEN5_INTER);
 
 	return 0;
 }
@@ -321,7 +347,7 @@ static unsigned int cm_get_main_vco_clk_hz(void)
 	u32 reg, clock;
 
 	/* get the main VCO clock */
-	reg = readl(&clock_manager_base->main_pll.vco);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
 	clock = cm_get_osc_clk_hz(1);
 	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
 		  CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
@@ -336,7 +362,7 @@ static unsigned int cm_get_per_vco_clk_hz(void)
 	u32 reg, clock = 0;
 
 	/* identify PER PLL clock source */
-	reg = readl(&clock_manager_base->per_pll.vco);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
 	reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
 	      CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
 	if (reg == CLKMGR_VCO_SSRC_EOSC1)
@@ -347,7 +373,7 @@ static unsigned int cm_get_per_vco_clk_hz(void)
 		clock = cm_get_f2s_per_ref_clk_hz();
 
 	/* get the PER VCO clock */
-	reg = readl(&clock_manager_base->per_pll.vco);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
 	clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
 		  CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
 	clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
@@ -363,9 +389,9 @@ unsigned long cm_get_mpu_clk_hz(void)
 	clock = cm_get_main_vco_clk_hz();
 
 	/* get the MPU clock */
-	reg = readl(&clock_manager_base->altera.mpuclk);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_ALTR_MPUCLK);
 	clock /= (reg + 1);
-	reg = readl(&clock_manager_base->main_pll.mpuclk);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MPUCLK);
 	clock /= (reg + 1);
 	return clock;
 }
@@ -375,7 +401,7 @@ unsigned long cm_get_sdram_clk_hz(void)
 	u32 reg, clock = 0;
 
 	/* identify SDRAM PLL clock source */
-	reg = readl(&clock_manager_base->sdr_pll.vco);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 	reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
 	      CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
 	if (reg == CLKMGR_VCO_SSRC_EOSC1)
@@ -386,14 +412,14 @@ unsigned long cm_get_sdram_clk_hz(void)
 		clock = cm_get_f2s_sdr_ref_clk_hz();
 
 	/* get the SDRAM VCO clock */
-	reg = readl(&clock_manager_base->sdr_pll.vco);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 	clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
 		  CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
 	clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
 		  CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
 
 	/* get the SDRAM (DDR_DQS) clock */
-	reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
 	reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
 	      CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
 	clock /= (reg + 1);
@@ -406,7 +432,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
 	u32 reg, clock = 0;
 
 	/* identify the source of L4 SP clock */
-	reg = readl(&clock_manager_base->main_pll.l4src);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC);
 	reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
 	      CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
 
@@ -414,20 +440,23 @@ unsigned int cm_get_l4_sp_clk_hz(void)
 		clock = cm_get_main_vco_clk_hz();
 
 		/* get the clock prior L4 SP divider (main clk) */
-		reg = readl(&clock_manager_base->altera.mainclk);
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_ALTR_MAINCLK);
 		clock /= (reg + 1);
-		reg = readl(&clock_manager_base->main_pll.mainclk);
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_MAINPLL_MAINCLK);
 		clock /= (reg + 1);
 	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
 		clock = cm_get_per_vco_clk_hz();
 
 		/* get the clock prior L4 SP divider (periph_base_clk) */
-		reg = readl(&clock_manager_base->per_pll.perbaseclk);
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_PERPLL_PERBASECLK);
 		clock /= (reg + 1);
 	}
 
 	/* get the L4 SP clock which supplied to UART */
-	reg = readl(&clock_manager_base->main_pll.maindiv);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINDIV);
 	reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
 	      CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
 	clock = clock / (1 << reg);
@@ -440,7 +469,7 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
 	u32 reg, clock = 0;
 
 	/* identify the source of MMC clock */
-	reg = readl(&clock_manager_base->per_pll.src);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
 	reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
 	      CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
 
@@ -450,13 +479,15 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
 		clock = cm_get_main_vco_clk_hz();
 
 		/* get the SDMMC clock */
-		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
 		clock /= (reg + 1);
 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
 		clock = cm_get_per_vco_clk_hz();
 
 		/* get the SDMMC clock */
-		reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
 		clock /= (reg + 1);
 	}
 
@@ -470,7 +501,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
 	u32 reg, clock = 0;
 
 	/* identify the source of QSPI clock */
-	reg = readl(&clock_manager_base->per_pll.src);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
 	reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
 	      CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
 
@@ -480,13 +511,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
 		clock = cm_get_main_vco_clk_hz();
 
 		/* get the qspi clock */
-		reg = readl(&clock_manager_base->main_pll.mainqspiclk);
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
 		clock /= (reg + 1);
 	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
 		clock = cm_get_per_vco_clk_hz();
 
 		/* get the qspi clock */
-		reg = readl(&clock_manager_base->per_pll.perqspiclk);
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_PERPLL_PERQSPICLK);
 		clock /= (reg + 1);
 	}
 
@@ -500,7 +533,7 @@ unsigned int cm_get_spi_controller_clk_hz(void)
 	clock = cm_get_per_vco_clk_hz();
 
 	/* get the clock prior L4 SP divider (periph_base_clk) */
-	reg = readl(&clock_manager_base->per_pll.perbaseclk);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERBASECLK);
 	clock /= (reg + 1);
 
 	return clock;
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
index 3ba2a00c02..05e42127b5 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -12,31 +12,26 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_clock_manager *clock_manager_base =
-	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-static const struct socfpga_system_manager *sysmgr_regs =
-		(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 /*
  * function to write the bypass register which requires a poll of the
  * busy bit
  */
 static void cm_write_bypass_mainpll(u32 val)
 {
-	writel(val, &clock_manager_base->main_pll.bypass);
+	writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_BYPASS);
 	cm_wait_for_fsm();
 }
 
 static void cm_write_bypass_perpll(u32 val)
 {
-	writel(val, &clock_manager_base->per_pll.bypass);
+	writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_BYPASS);
 	cm_wait_for_fsm();
 }
 
 /* function to write the ctrl register which requires a poll of the busy bit */
 static void cm_write_ctrl(u32 val)
 {
-	writel(val, &clock_manager_base->ctrl);
+	writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL);
 	cm_wait_for_fsm();
 }
 
@@ -68,12 +63,17 @@ void cm_basic_init(const struct cm_config * const cfg)
 
 	writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
 		~CLKMGR_PLLGLOB_RST_MASK),
-		&clock_manager_base->main_pll.pllglob);
-	writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);
-	writel(vcocalib, &clock_manager_base->main_pll.vcocalib);
-	writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);
-	writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);
-	writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);
+		socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
+	writel(cfg->main_pll_fdbck,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
+	writel(vcocalib,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_VCOCALIB);
+	writel(cfg->main_pll_pllc0,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC0);
+	writel(cfg->main_pll_pllc1,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC1);
+	writel(cfg->main_pll_nocdiv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCDIV);
 
 	/* setup peripheral PLL dividers */
 	/* calculate the vcocalib value */
@@ -90,18 +90,24 @@ void cm_basic_init(const struct cm_config * const cfg)
 
 	writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
 		~CLKMGR_PLLGLOB_RST_MASK),
-		&clock_manager_base->per_pll.pllglob);
-	writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);
-	writel(vcocalib, &clock_manager_base->per_pll.vcocalib);
-	writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);
-	writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);
-	writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);
-	writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);
+		socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
+	writel(cfg->per_pll_fdbck,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
+	writel(vcocalib,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_VCOCALIB);
+	writel(cfg->per_pll_pllc0,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC0);
+	writel(cfg->per_pll_pllc1,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC1);
+	writel(cfg->per_pll_emacctl,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EMACCTL);
+	writel(cfg->per_pll_gpiodiv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_GPIODIV);
 
 	/* Take both PLL out of reset and power up */
-	setbits_le32(&clock_manager_base->main_pll.pllglob,
+	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB,
 		     CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
-	setbits_le32(&clock_manager_base->per_pll.pllglob,
+	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB,
 		     CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
 
 #define LOCKED_MASK \
@@ -115,66 +121,85 @@ void cm_basic_init(const struct cm_config * const cfg)
 	 * only take effect upon value change, we shall set a maximum value as
 	 * default value.
 	 */
-	writel(0xff, &clock_manager_base->main_pll.mpuclk);
-	writel(0xff, &clock_manager_base->main_pll.nocclk);
-	writel(0xff, &clock_manager_base->main_pll.cntr2clk);
-	writel(0xff, &clock_manager_base->main_pll.cntr3clk);
-	writel(0xff, &clock_manager_base->main_pll.cntr4clk);
-	writel(0xff, &clock_manager_base->main_pll.cntr5clk);
-	writel(0xff, &clock_manager_base->main_pll.cntr6clk);
-	writel(0xff, &clock_manager_base->main_pll.cntr7clk);
-	writel(0xff, &clock_manager_base->main_pll.cntr8clk);
-	writel(0xff, &clock_manager_base->main_pll.cntr9clk);
-	writel(0xff, &clock_manager_base->per_pll.cntr2clk);
-	writel(0xff, &clock_manager_base->per_pll.cntr3clk);
-	writel(0xff, &clock_manager_base->per_pll.cntr4clk);
-	writel(0xff, &clock_manager_base->per_pll.cntr5clk);
-	writel(0xff, &clock_manager_base->per_pll.cntr6clk);
-	writel(0xff, &clock_manager_base->per_pll.cntr7clk);
-	writel(0xff, &clock_manager_base->per_pll.cntr8clk);
-	writel(0xff, &clock_manager_base->per_pll.cntr9clk);
-
-	writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);
-	writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);
-	writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);
-	writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);
-	writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);
-	writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);
-	writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);
-	writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);
-	writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);
-	writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);
-	writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);
-	writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);
-	writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);
-	writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);
-	writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);
-	writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);
-	writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);
-	writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
+
+	writel(cfg->main_pll_mpuclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
+	writel(cfg->main_pll_nocclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
+	writel(cfg->main_pll_cntr2clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
+	writel(cfg->main_pll_cntr3clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
+	writel(cfg->main_pll_cntr4clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
+	writel(cfg->main_pll_cntr5clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
+	writel(cfg->main_pll_cntr6clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
+	writel(cfg->main_pll_cntr7clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
+	writel(cfg->main_pll_cntr8clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
+	writel(cfg->main_pll_cntr9clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
+	writel(cfg->per_pll_cntr2clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
+	writel(cfg->per_pll_cntr3clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
+	writel(cfg->per_pll_cntr4clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
+	writel(cfg->per_pll_cntr5clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
+	writel(cfg->per_pll_cntr6clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
+	writel(cfg->per_pll_cntr7clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
+	writel(cfg->per_pll_cntr8clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
+	writel(cfg->per_pll_cntr9clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
 
 	/* Take all PLLs out of bypass */
 	cm_write_bypass_mainpll(0);
 	cm_write_bypass_perpll(0);
 
 	/* clear safe mode / out of boot mode */
-	cm_write_ctrl(readl(&clock_manager_base->ctrl)
-			& ~(CLKMGR_CTRL_SAFEMODE));
+	cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL) &
+		      ~(CLKMGR_CTRL_SAFEMODE));
 
 	/* Now ungate non-hw-managed clocks */
-	writel(~0, &clock_manager_base->main_pll.en);
-	writel(~0, &clock_manager_base->per_pll.en);
+	writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_EN);
+	writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EN);
 
 	/* Clear the loss of lock bits (write 1 to clear) */
-	writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK,
-	       &clock_manager_base->intrclr);
+	writel(CLKMGR_INTER_PERPLLLOST_MASK |
+		      CLKMGR_INTER_MAINPLLLOST_MASK,
+		      socfpga_get_clkmgr_addr() + CLKMGR_S10_INTRCLR);
 }
 
 static unsigned long cm_get_main_vco_clk_hz(void)
 {
 	 unsigned long fref, refdiv, mdiv, reg, vco;
 
-	reg = readl(&clock_manager_base->main_pll.pllglob);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
 
 	fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
 		CLKMGR_PLLGLOB_VCO_PSRC_MASK;
@@ -193,7 +218,7 @@ static unsigned long cm_get_main_vco_clk_hz(void)
 	refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
 		  CLKMGR_PLLGLOB_REFCLKDIV_MASK;
 
-	reg = readl(&clock_manager_base->main_pll.fdbck);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
 	mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
 
 	vco = fref / refdiv;
@@ -205,7 +230,7 @@ static unsigned long cm_get_per_vco_clk_hz(void)
 {
 	unsigned long fref, refdiv, mdiv, reg, vco;
 
-	reg = readl(&clock_manager_base->per_pll.pllglob);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
 
 	fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
 		CLKMGR_PLLGLOB_VCO_PSRC_MASK;
@@ -224,7 +249,7 @@ static unsigned long cm_get_per_vco_clk_hz(void)
 	refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
 		  CLKMGR_PLLGLOB_REFCLKDIV_MASK;
 
-	reg = readl(&clock_manager_base->per_pll.fdbck);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
 	mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
 
 	vco = fref / refdiv;
@@ -234,20 +259,23 @@ static unsigned long cm_get_per_vco_clk_hz(void)
 
 unsigned long cm_get_mpu_clk_hz(void)
 {
-	unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);
+	unsigned long clock = readl(socfpga_get_clkmgr_addr() +
+				    CLKMGR_S10_MAINPLL_MPUCLK);
 
 	clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
 
 	switch (clock) {
 	case CLKMGR_CLKSRC_MAIN:
 		clock = cm_get_main_vco_clk_hz();
-		clock /= (readl(&clock_manager_base->main_pll.pllc0) &
+		clock /= (readl(socfpga_get_clkmgr_addr() +
+				CLKMGR_S10_MAINPLL_PLLC0) &
 			  CLKMGR_PLLC0_DIV_MASK);
 		break;
 
 	case CLKMGR_CLKSRC_PER:
 		clock = cm_get_per_vco_clk_hz();
-		clock /= (readl(&clock_manager_base->per_pll.pllc0) &
+		clock /= (readl(socfpga_get_clkmgr_addr() +
+				CLKMGR_S10_PERPLL_PLLC0) &
 			  CLKMGR_CLKCNT_MSK);
 		break;
 
@@ -264,28 +292,30 @@ unsigned long cm_get_mpu_clk_hz(void)
 		break;
 	}
 
-	clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &
-		CLKMGR_CLKCNT_MSK);
+	clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_S10_MAINPLL_MPUCLK) & CLKMGR_CLKCNT_MSK);
 	return clock;
 }
 
 unsigned int cm_get_l3_main_clk_hz(void)
 {
-	u32 clock = readl(&clock_manager_base->main_pll.nocclk);
+	u32 clock = readl(socfpga_get_clkmgr_addr() +
+			  CLKMGR_S10_MAINPLL_NOCCLK);
 
 	clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
 
 	switch (clock) {
 	case CLKMGR_CLKSRC_MAIN:
 		clock = cm_get_main_vco_clk_hz();
-		clock /= (readl(&clock_manager_base->main_pll.pllc1) &
+		clock /= (readl(socfpga_get_clkmgr_addr() +
+				CLKMGR_S10_MAINPLL_PLLC1) &
 			  CLKMGR_PLLC0_DIV_MASK);
 		break;
 
 	case CLKMGR_CLKSRC_PER:
 		clock = cm_get_per_vco_clk_hz();
-		clock /= (readl(&clock_manager_base->per_pll.pllc1) &
-			  CLKMGR_CLKCNT_MSK);
+		clock /= (readl(socfpga_get_clkmgr_addr() +
+			  CLKMGR_S10_PERPLL_PLLC1) & CLKMGR_CLKCNT_MSK);
 		break;
 
 	case CLKMGR_CLKSRC_OSC1:
@@ -301,28 +331,31 @@ unsigned int cm_get_l3_main_clk_hz(void)
 		break;
 	}
 
-	clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &
-		CLKMGR_CLKCNT_MSK);
+	clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
+		      CLKMGR_S10_MAINPLL_NOCCLK) & CLKMGR_CLKCNT_MSK);
 	return clock;
 }
 
 unsigned int cm_get_mmc_controller_clk_hz(void)
 {
-	u32 clock = readl(&clock_manager_base->per_pll.cntr6clk);
+	u32 clock = readl(socfpga_get_clkmgr_addr() +
+			  CLKMGR_S10_PERPLL_CNTR6CLK);
 
 	clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
 
 	switch (clock) {
 	case CLKMGR_CLKSRC_MAIN:
 		clock = cm_get_l3_main_clk_hz();
-		clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
-			CLKMGR_CLKCNT_MSK);
+		clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
+				    CLKMGR_S10_MAINPLL_CNTR6CLK) &
+			      CLKMGR_CLKCNT_MSK);
 		break;
 
 	case CLKMGR_CLKSRC_PER:
 		clock = cm_get_l3_main_clk_hz();
-		clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
-			CLKMGR_CLKCNT_MSK);
+		clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
+				    CLKMGR_S10_PERPLL_CNTR6CLK) &
+			      CLKMGR_CLKCNT_MSK);
 		break;
 
 	case CLKMGR_CLKSRC_OSC1:
@@ -344,22 +377,25 @@ unsigned int cm_get_l4_sp_clk_hz(void)
 {
 	u32 clock = cm_get_l3_main_clk_hz();
 
-	clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
-		  CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
+	clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
+			       CLKMGR_S10_MAINPLL_NOCDIV) >>
+			 CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
 	return clock;
 }
 
 unsigned int cm_get_qspi_controller_clk_hz(void)
 {
-	return readl(&sysmgr_regs->boot_scratch_cold0);
+	return readl(socfpga_get_sysmgr_addr() +
+		     SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
 }
 
 unsigned int cm_get_spi_controller_clk_hz(void)
 {
 	u32 clock = cm_get_l3_main_clk_hz();
 
-	clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
-		  CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
+	clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
+			       CLKMGR_S10_MAINPLL_NOCDIV) >>
+			 CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
 	return clock;
 }
 
diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c
new file mode 100644
index 0000000000..69229dc651
--- /dev/null
+++ b/arch/arm/mach-socfpga/firewall.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/system_manager.h>
+
+static void firewall_l4_per_disable(void)
+{
+	const struct socfpga_firwall_l4_per *firwall_l4_per_base =
+		(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
+	u32 i;
+	const u32 *addr[] = {
+			&firwall_l4_per_base->nand,
+			&firwall_l4_per_base->nand_data,
+			&firwall_l4_per_base->usb0,
+			&firwall_l4_per_base->usb1,
+			&firwall_l4_per_base->spim0,
+			&firwall_l4_per_base->spim1,
+			&firwall_l4_per_base->emac0,
+			&firwall_l4_per_base->emac1,
+			&firwall_l4_per_base->emac2,
+			&firwall_l4_per_base->sdmmc,
+			&firwall_l4_per_base->gpio0,
+			&firwall_l4_per_base->gpio1,
+			&firwall_l4_per_base->i2c0,
+			&firwall_l4_per_base->i2c1,
+			&firwall_l4_per_base->i2c2,
+			&firwall_l4_per_base->i2c3,
+			&firwall_l4_per_base->i2c4,
+			&firwall_l4_per_base->timer0,
+			&firwall_l4_per_base->timer1,
+			&firwall_l4_per_base->uart0,
+			&firwall_l4_per_base->uart1
+			};
+
+	/*
+	 * The following lines of code will enable non-secure access
+	 * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This
+	 * is needed as most OS run in non-secure mode. Thus we need to
+	 * enable non-secure access to these peripherals in order for the
+	 * OS to use these peripherals.
+	 */
+	for (i = 0; i < ARRAY_SIZE(addr); i++)
+		writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
+}
+
+static void firewall_l4_sys_disable(void)
+{
+	const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
+		(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
+	u32 i;
+	const u32 *addr[] = {
+			&firwall_l4_sys_base->dma_ecc,
+			&firwall_l4_sys_base->emac0rx_ecc,
+			&firwall_l4_sys_base->emac0tx_ecc,
+			&firwall_l4_sys_base->emac1rx_ecc,
+			&firwall_l4_sys_base->emac1tx_ecc,
+			&firwall_l4_sys_base->emac2rx_ecc,
+			&firwall_l4_sys_base->emac2tx_ecc,
+			&firwall_l4_sys_base->nand_ecc,
+			&firwall_l4_sys_base->nand_read_ecc,
+			&firwall_l4_sys_base->nand_write_ecc,
+			&firwall_l4_sys_base->ocram_ecc,
+			&firwall_l4_sys_base->sdmmc_ecc,
+			&firwall_l4_sys_base->usb0_ecc,
+			&firwall_l4_sys_base->usb1_ecc,
+			&firwall_l4_sys_base->clock_manager,
+			&firwall_l4_sys_base->io_manager,
+			&firwall_l4_sys_base->reset_manager,
+			&firwall_l4_sys_base->system_manager,
+			&firwall_l4_sys_base->watchdog0,
+			&firwall_l4_sys_base->watchdog1,
+			&firwall_l4_sys_base->watchdog2,
+			&firwall_l4_sys_base->watchdog3
+		};
+
+	for (i = 0; i < ARRAY_SIZE(addr); i++)
+		writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
+}
+
+static void firewall_bridge_disable(void)
+{
+	/* disable lwsocf2fpga and soc2fpga bridge security */
+	writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
+	writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
+}
+
+void firewall_setup(void)
+{
+	firewall_l4_per_disable();
+	firewall_l4_sys_disable();
+	firewall_bridge_disable();
+
+	/* disable SMMU security */
+	writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
+
+	/* enable non-secure interface to DMA330 DMA and peripherals */
+	writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA);
+	writel(SYSMGR_DMAPERIPH_ALL_NS,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH);
+}
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
index 1f549d7e70..d3eca65e97 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -10,7 +10,11 @@
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
 #define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
 #define SOCFPGA_SDR_ADDRESS			0xf8011000
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020200
+#else
 #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020100
+#endif
 #define SOCFPGA_SMMU_ADDRESS			0xfa000000
 #define SOCFPGA_MAILBOX_ADDRESS			0xffa30000
 #define SOCFPGA_UART0_ADDRESS			0xffc02000
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index dd80e3a767..c6830582a5 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -6,6 +6,8 @@
 #ifndef _CLOCK_MANAGER_H_
 #define _CLOCK_MANAGER_H_
 
+phys_addr_t socfpga_get_clkmgr_addr(void);
+
 #ifndef __ASSEMBLER__
 void cm_wait_for_lock(u32 mask);
 int cm_wait_for_fsm(void);
@@ -18,6 +20,8 @@ void cm_print_clock_quick_summary(void);
 #include <asm/arch/clock_manager_arria10.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 #include <asm/arch/clock_manager_s10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+#include <asm/arch/clock_manager_agilex.h>
 #endif
 
 #endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
new file mode 100644
index 0000000000..386e82a4e3
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLOCK_MANAGER_AGILEX_
+#define _CLOCK_MANAGER_AGILEX_
+
+unsigned long cm_get_mpu_clk_hz(void);
+
+#include <asm/arch/clock_manager_soc64.h>
+#include "../../../../../drivers/clk/altera/clk-agilex.h"
+
+#endif /* _CLOCK_MANAGER_AGILEX_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index de8c22540f..23f280df1b 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -8,86 +8,57 @@
 
 #ifndef __ASSEMBLER__
 
-struct socfpga_clock_manager_main_pll {
-	u32  vco0;
-	u32  vco1;
-	u32  en;
-	u32  ens;
-	u32  enr;
-	u32  bypass;
-	u32  bypasss;
-	u32  bypassr;
-	u32  mpuclk;
-	u32  nocclk;
-	u32  cntr2clk;
-	u32  cntr3clk;
-	u32  cntr4clk;
-	u32  cntr5clk;
-	u32  cntr6clk;
-	u32  cntr7clk;
-	u32  cntr8clk;
-	u32  cntr9clk;
-	u32  pad_0x48_0x5b[5];
-	u32  cntr15clk;
-	u32  outrst;
-	u32  outrststat;
-	u32  nocdiv;
-	u32  pad_0x6c_0x80[5];
-};
-
-struct socfpga_clock_manager_per_pll {
-	u32  vco0;
-	u32  vco1;
-	u32  en;
-	u32  ens;
-	u32  enr;
-	u32  bypass;
-	u32  bypasss;
-	u32  bypassr;
-	u32  pad_0x20_0x27[2];
-	u32  cntr2clk;
-	u32  cntr3clk;
-	u32  cntr4clk;
-	u32  cntr5clk;
-	u32  cntr6clk;
-	u32  cntr7clk;
-	u32  cntr8clk;
-	u32  cntr9clk;
-	u32  pad_0x48_0x5f[6];
-	u32  outrst;
-	u32  outrststat;
-	u32  emacctl;
-	u32  gpiodiv;
-	u32  pad_0x70_0x80[4];
-};
-
-struct socfpga_clock_manager_altera {
-	u32	mpuclk;
-	u32	nocclk;
-	u32	mainmisc0;
-	u32	mainmisc1;
-	u32	perimisc0;
-	u32	perimisc1;
-};
-
-struct socfpga_clock_manager {
-	/* clkmgr */
-	u32  ctrl;
-	u32  intr;
-	u32  intrs;
-	u32  intrr;
-	u32  intren;
-	u32  intrens;
-	u32  intrenr;
-	u32  stat;
-	u32  testioctrl;
-	u32  _pad_0x24_0x40[7];
-	/* mainpllgrp */
-	struct socfpga_clock_manager_main_pll main_pll;
-	/* perpllgrp */
-	struct socfpga_clock_manager_per_pll per_pll;
-	struct socfpga_clock_manager_altera altera;
-};
+/* Clock manager group */
+#define CLKMGR_A10_CTRL				0x00
+#define CLKMGR_A10_INTR				0x04
+#define CLKMGR_A10_STAT				0x1c
+/* MainPLL group */
+#define CLKMGR_A10_MAINPLL_VCO0			0x40
+#define CLKMGR_A10_MAINPLL_VCO1			0x44
+#define CLKMGR_A10_MAINPLL_EN			0x48
+#define CLKMGR_A10_MAINPLL_ENS			0x4c
+#define CLKMGR_A10_MAINPLL_ENR			0x50
+#define CLKMGR_A10_MAINPLL_BYPASS		0x54
+#define CLKMGR_A10_MAINPLL_BYPASSS		0x58
+#define CLKMGR_A10_MAINPLL_BYPASSR		0x5c
+#define CLKMGR_A10_MAINPLL_MPUCLK		0x60
+#define CLKMGR_A10_MAINPLL_NOCCLK		0x64
+#define CLKMGR_A10_MAINPLL_CNTR2CLK		0x68
+#define CLKMGR_A10_MAINPLL_CNTR3CLK		0x6c
+#define CLKMGR_A10_MAINPLL_CNTR4CLK		0x70
+#define CLKMGR_A10_MAINPLL_CNTR5CLK		0x74
+#define CLKMGR_A10_MAINPLL_CNTR6CLK		0x78
+#define CLKMGR_A10_MAINPLL_CNTR7CLK		0x7c
+#define CLKMGR_A10_MAINPLL_CNTR8CLK		0x80
+#define CLKMGR_A10_MAINPLL_CNTR9CLK		0x84
+#define CLKMGR_A10_MAINPLL_CNTR15CLK		0x9c
+#define CLKMGR_A10_MAINPLL_NOCDIV		0xa8
+/* Peripheral PLL group */
+#define CLKMGR_A10_PERPLL_VCO0			0xc0
+#define CLKMGR_A10_PERPLL_VCO1			0xc4
+#define CLKMGR_A10_PERPLL_EN			0xc8
+#define CLKMGR_A10_PERPLL_ENS			0xcc
+#define CLKMGR_A10_PERPLL_ENR			0xd0
+#define CLKMGR_A10_PERPLL_BYPASS		0xd4
+#define CLKMGR_A10_PERPLL_BYPASSS		0xd8
+#define CLKMGR_A10_PERPLL_BYPASSR		0xdc
+#define CLKMGR_A10_PERPLL_CNTR2CLK		0xe8
+#define CLKMGR_A10_PERPLL_CNTR3CLK		0xec
+#define CLKMGR_A10_PERPLL_CNTR4CLK		0xf0
+#define CLKMGR_A10_PERPLL_CNTR5CLK		0xf4
+#define CLKMGR_A10_PERPLL_CNTR6CLK		0xf8
+#define CLKMGR_A10_PERPLL_CNTR7CLK		0xfc
+#define CLKMGR_A10_PERPLL_CNTR8CLK		0x100
+#define CLKMGR_A10_PERPLL_CNTR9CLK		0x104
+#define CLKMGR_A10_PERPLL_EMACCTL		0x128
+#define CLKMGR_A10_PERPLL_GPIOFIV		0x12c
+/* Altera group */
+#define CLKMGR_A10_ALTR_MPUCLK			0x140
+#define CLKMGR_A10_ALTR_NOCCLK			0x144
+
+#define CLKMGR_STAT				CLKMGR_A10_STAT
+#define CLKMGR_INTER				CLKMGR_A10_INTER
+#define CLKMGR_PERPLL_EN			CLKMGR_A10_PERPLL_EN
 
 #ifdef CONFIG_SPL_BUILD
 int cm_basic_init(const void *blob);
@@ -100,8 +71,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 
 #endif /* __ASSEMBLER__ */
 
-#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET			0x140
-#define CLKMGR_MAINPLL_NOC_CLK_OFFSET			0x144
 #define LOCKED_MASK	(CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
 			 CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
 
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index 5bedf28cf1..08655094ca 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -45,71 +45,53 @@ struct cm_config {
 	u32 altera_grp_mpuclk;
 };
 
-struct socfpga_clock_manager_main_pll {
-	u32	vco;
-	u32	misc;
-	u32	mpuclk;
-	u32	mainclk;
-	u32	dbgatclk;
-	u32	mainqspiclk;
-	u32	mainnandsdmmcclk;
-	u32	cfgs2fuser0clk;
-	u32	en;
-	u32	maindiv;
-	u32	dbgdiv;
-	u32	tracediv;
-	u32	l4src;
-	u32	stat;
-	u32	_pad_0x38_0x40[2];
-};
-
-struct socfpga_clock_manager_per_pll {
-	u32	vco;
-	u32	misc;
-	u32	emac0clk;
-	u32	emac1clk;
-	u32	perqspiclk;
-	u32	pernandsdmmcclk;
-	u32	perbaseclk;
-	u32	s2fuser1clk;
-	u32	en;
-	u32	div;
-	u32	gpiodiv;
-	u32	src;
-	u32	stat;
-	u32	_pad_0x34_0x40[3];
-};
-
-struct socfpga_clock_manager_sdr_pll {
-	u32	vco;
-	u32	ctrl;
-	u32	ddrdqsclk;
-	u32	ddr2xdqsclk;
-	u32	ddrdqclk;
-	u32	s2fuser2clk;
-	u32	en;
-	u32	stat;
-};
-
-struct socfpga_clock_manager_altera {
-	u32	mpuclk;
-	u32	mainclk;
-};
-
-struct socfpga_clock_manager {
-	u32	ctrl;
-	u32	bypass;
-	u32	inter;
-	u32	intren;
-	u32	dbctrl;
-	u32	stat;
-	u32	_pad_0x18_0x3f[10];
-	struct socfpga_clock_manager_main_pll main_pll;
-	struct socfpga_clock_manager_per_pll per_pll;
-	struct socfpga_clock_manager_sdr_pll sdr_pll;
-	struct socfpga_clock_manager_altera altera;
-	u32	_pad_0xe8_0x200[70];
-};
+/* Clock manager group */
+#define CLKMGR_GEN5_CTRL			0x00
+#define CLKMGR_GEN5_BYPASS			0x04
+#define CLKMGR_GEN5_INTER			0x08
+#define CLKMGR_GEN5_STAT			0x14
+/* MainPLL group */
+#define CLKMGR_GEN5_MAINPLL_VCO			0x40
+#define CLKMGR_GEN5_MAINPLL_MISC		0x44
+#define CLKMGR_GEN5_MAINPLL_MPUCLK		0x48
+#define CLKMGR_GEN5_MAINPLL_MAINCLK		0x4c
+#define CLKMGR_GEN5_MAINPLL_DBGATCLK		0x50
+#define CLKMGR_GEN5_MAINPLL_MAINQSPICLK		0x54
+#define CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK	0x58
+#define CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK	0x5c
+#define CLKMGR_GEN5_MAINPLL_EN			0x60
+#define CLKMGR_GEN5_MAINPLL_MAINDIV		0x64
+#define CLKMGR_GEN5_MAINPLL_DBGDIV		0x68
+#define CLKMGR_GEN5_MAINPLL_TRACEDIV		0x6c
+#define CLKMGR_GEN5_MAINPLL_L4SRC		0x70
+/* Peripheral PLL group */
+#define CLKMGR_GEN5_PERPLL_VCO			0x80
+#define CLKMGR_GEN5_PERPLL_MISC			0x84
+#define CLKMGR_GEN5_PERPLL_EMAC0CLK		0x88
+#define CLKMGR_GEN5_PERPLL_EMAC1CLK		0x8c
+#define CLKMGR_GEN5_PERPLL_PERQSPICLK		0x90
+#define CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK	0x94
+#define CLKMGR_GEN5_PERPLL_PERBASECLK		0x98
+#define CLKMGR_GEN5_PERPLL_S2FUSER1CLK		0x9c
+#define CLKMGR_GEN5_PERPLL_EN			0xa0
+#define CLKMGR_GEN5_PERPLL_DIV			0xa4
+#define CLKMGR_GEN5_PERPLL_GPIODIV		0xa8
+#define CLKMGR_GEN5_PERPLL_SRC			0xac
+/* SDRAM PLL group */
+#define CLKMGR_GEN5_SDRPLL_VCO			0xc0
+#define CLKMGR_GEN5_SDRPLL_CTRL			0xc4
+#define CLKMGR_GEN5_SDRPLL_DDRDQSCLK		0xc8
+#define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK		0xcc
+#define CLKMGR_GEN5_SDRPLL_DDRDQCLK		0xd0
+#define CLKMGR_GEN5_SDRPLL_S2FUSER2CLK		0xd4
+#define CLKMGR_GEN5_SDRPLL_EN			0xd8
+/* Altera group */
+#define CLKMGR_GEN5_ALTR_MPUCLK			0xe0
+#define CLKMGR_GEN5_ALTR_MAINCLK		0xe4
+
+#define CLKMGR_STAT				CLKMGR_GEN5_STAT
+#define CLKMGR_INTER				CLKMGR_GEN5_INTER
+#define CLKMGR_PERPLL_EN			CLKMGR_GEN5_PERPLL_EN
 
 /* Clock speed accessors */
 unsigned long cm_get_mpu_clk_hz(void);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 24b20de011..e710aa2f94 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -1,12 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
  *
  */
 
 #ifndef	_CLOCK_MANAGER_S10_
 #define	_CLOCK_MANAGER_S10_
 
+#include <asm/arch/clock_manager_soc64.h>
+
 /* Clock speed accessors */
 unsigned long cm_get_mpu_clk_hz(void);
 unsigned long cm_get_sdram_clk_hz(void);
@@ -14,18 +16,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 unsigned int cm_get_mmc_controller_clk_hz(void);
 unsigned int cm_get_qspi_controller_clk_hz(void);
 unsigned int cm_get_spi_controller_clk_hz(void);
-const unsigned int cm_get_osc_clk_hz(void);
-const unsigned int cm_get_f2s_per_ref_clk_hz(void);
-const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
-const unsigned int cm_get_intosc_clk_hz(void);
-const unsigned int cm_get_fpga_clk_hz(void);
-
-#define CLKMGR_EOSC1_HZ		25000000
-#define CLKMGR_INTOSC_HZ	460000000
-#define CLKMGR_FPGA_CLK_HZ	50000000
-
-/* Clock configuration accessors */
-const struct cm_config * const cm_get_default_config(void);
 
 struct cm_config {
 	/* main group */
@@ -69,75 +59,54 @@ struct cm_config {
 
 void cm_basic_init(const struct cm_config * const cfg);
 
-struct socfpga_clock_manager_main_pll {
-	u32	en;
-	u32	ens;
-	u32	enr;
-	u32	bypass;
-	u32	bypasss;
-	u32	bypassr;
-	u32	mpuclk;
-	u32	nocclk;
-	u32	cntr2clk;
-	u32	cntr3clk;
-	u32	cntr4clk;
-	u32	cntr5clk;
-	u32	cntr6clk;
-	u32	cntr7clk;
-	u32	cntr8clk;
-	u32	cntr9clk;
-	u32	nocdiv;
-	u32	pllglob;
-	u32	fdbck;
-	u32	mem;
-	u32	memstat;
-	u32	pllc0;
-	u32	pllc1;
-	u32	vcocalib;
-	u32	_pad_0x90_0xA0[5];
-};
+/* Control status */
+#define CLKMGR_S10_CTRL					0x00
+#define CLKMGR_S10_STAT					0x04
+#define CLKMGR_S10_INTRCLR				0x14
+/* Mainpll group */
+#define CLKMGR_S10_MAINPLL_EN				0x30
+#define CLKMGR_S10_MAINPLL_BYPASS			0x3c
+#define CLKMGR_S10_MAINPLL_MPUCLK			0x48
+#define CLKMGR_S10_MAINPLL_NOCCLK			0x4c
+#define CLKMGR_S10_MAINPLL_CNTR2CLK			0x50
+#define CLKMGR_S10_MAINPLL_CNTR3CLK			0x54
+#define CLKMGR_S10_MAINPLL_CNTR4CLK			0x58
+#define CLKMGR_S10_MAINPLL_CNTR5CLK			0x5c
+#define CLKMGR_S10_MAINPLL_CNTR6CLK			0x60
+#define CLKMGR_S10_MAINPLL_CNTR7CLK			0x64
+#define CLKMGR_S10_MAINPLL_CNTR8CLK			0x68
+#define CLKMGR_S10_MAINPLL_CNTR9CLK			0x6c
+#define CLKMGR_S10_MAINPLL_NOCDIV			0x70
+#define CLKMGR_S10_MAINPLL_PLLGLOB			0x74
+#define CLKMGR_S10_MAINPLL_FDBCK			0x78
+#define CLKMGR_S10_MAINPLL_MEMSTAT			0x80
+#define CLKMGR_S10_MAINPLL_PLLC0			0x84
+#define CLKMGR_S10_MAINPLL_PLLC1			0x88
+#define CLKMGR_S10_MAINPLL_VCOCALIB			0x8c
+/* Periphpll group */
+#define CLKMGR_S10_PERPLL_EN				0xa4
+#define CLKMGR_S10_PERPLL_BYPASS			0xac
+#define CLKMGR_S10_PERPLL_CNTR2CLK			0xbc
+#define CLKMGR_S10_PERPLL_CNTR3CLK			0xc0
+#define CLKMGR_S10_PERPLL_CNTR4CLK			0xc4
+#define CLKMGR_S10_PERPLL_CNTR5CLK			0xc8
+#define CLKMGR_S10_PERPLL_CNTR6CLK			0xcc
+#define CLKMGR_S10_PERPLL_CNTR7CLK			0xd0
+#define CLKMGR_S10_PERPLL_CNTR8CLK			0xd4
+#define CLKMGR_S10_PERPLL_CNTR9CLK			0xd8
+#define CLKMGR_S10_PERPLL_EMACCTL			0xdc
+#define CLKMGR_S10_PERPLL_GPIODIV			0xe0
+#define CLKMGR_S10_PERPLL_PLLGLOB			0xe4
+#define CLKMGR_S10_PERPLL_FDBCK				0xe8
+#define CLKMGR_S10_PERPLL_MEMSTAT			0xf0
+#define CLKMGR_S10_PERPLL_PLLC0				0xf4
+#define CLKMGR_S10_PERPLL_PLLC1				0xf8
+#define CLKMGR_S10_PERPLL_VCOCALIB			0xfc
+
+#define CLKMGR_STAT					CLKMGR_S10_STAT
+#define CLKMGR_INTER					CLKMGR_S10_INTER
+#define CLKMGR_PERPLL_EN				CLKMGR_S10_PERPLL_EN
 
-struct socfpga_clock_manager_per_pll {
-	u32	en;
-	u32	ens;
-	u32	enr;
-	u32	bypass;
-	u32	bypasss;
-	u32	bypassr;
-	u32	cntr2clk;
-	u32	cntr3clk;
-	u32	cntr4clk;
-	u32	cntr5clk;
-	u32	cntr6clk;
-	u32	cntr7clk;
-	u32	cntr8clk;
-	u32	cntr9clk;
-	u32	emacctl;
-	u32	gpiodiv;
-	u32	pllglob;
-	u32	fdbck;
-	u32	mem;
-	u32	memstat;
-	u32	pllc0;
-	u32	pllc1;
-	u32	vcocalib;
-	u32	_pad_0x100_0x124[10];
-};
-
-struct socfpga_clock_manager {
-	u32	ctrl;
-	u32	stat;
-	u32	testioctrl;
-	u32	intrgen;
-	u32	intrmsk;
-	u32	intrclr;
-	u32	intrsts;
-	u32	intrstk;
-	u32	intrraw;
-	u32	_pad_0x24_0x2c[3];
-	struct socfpga_clock_manager_main_pll main_pll;
-	struct socfpga_clock_manager_per_pll per_pll;
-};
 
 #define CLKMGR_CTRL_SAFEMODE				BIT(0)
 #define CLKMGR_BYPASS_MAINPLL_ALL			0x00000007
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
new file mode 100644
index 0000000000..71fbaa7667
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _CLOCK_MANAGER_SOC64_
+#define _CLOCK_MANAGER_SOC64_
+
+const unsigned int cm_get_osc_clk_hz(void);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+const unsigned int cm_get_intosc_clk_hz(void);
+const unsigned int cm_get_fpga_clk_hz(void);
+
+#define CLKMGR_INTOSC_HZ	400000000
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+
+#endif /* _CLOCK_MANAGER_SOC64_ */
diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall.h
index b96f779f14..430341bea1 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
  *
  */
 
-#ifndef	_FIREWALL_S10_
-#define	_FIREWALL_S10_
+#ifndef	_FIREWALL_H_
+#define	_FIREWALL_H_
 
 struct socfpga_firwall_l4_per {
 	u32	nand;		/* 0x00 */
@@ -95,6 +95,13 @@ struct socfpga_firwall_l4_sys {
 
 #define CCU_IOM_MPRT_ADMASK_MEM_RAM0		0x18628
 
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE0		0x2c520
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A		0x2c540
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B		0x2c560
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C		0x2c580
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D		0x2c5a0
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E		0x2c5c0
+
 #define CCU_ADMASK_P_MASK			BIT(0)
 #define CCU_ADMASK_NS_MASK			BIT(1)
 
@@ -117,4 +124,6 @@ struct socfpga_firwall_l4_sys {
 #define FW_MPU_DDR_SCR_WRITEL(data, reg)		\
 	writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
 
-#endif /* _FIREWALL_S10_ */
+void firewall_setup(void);
+
+#endif /* _FIREWALL_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
index ba0f1fd1b2..3e9b606ce2 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
@@ -26,8 +26,13 @@
 #define S10_HANDOFF_OFFSET_LENGTH	0x4
 #define S10_HANDOFF_OFFSET_DATA	0x10
 
-#define S10_HANDOFF_CLOCK_OSC	(S10_HANDOFF_BASE + 0x608)
-#define S10_HANDOFF_CLOCK_FPGA	(S10_HANDOFF_BASE + 0x60C)
+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+#define HANDOFF_CLOCK_OSC	(S10_HANDOFF_BASE + 0x608)
+#define HANDOFF_CLOCK_FPGA	(S10_HANDOFF_BASE + 0x60C)
+#else
+#define HANDOFF_CLOCK_OSC	(S10_HANDOFF_BASE + 0x5fc)
+#define HANDOFF_CLOCK_FPGA	(S10_HANDOFF_BASE + 0x600)
+#endif
 
 #define S10_HANDOFF_SIZE	4096
 
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index f11f907e1c..f6de1ccb4a 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -41,5 +41,6 @@ void socfpga_sdram_remap_zero(void);
 
 void do_bridge_reset(int enable, unsigned int mask);
 void socfpga_pl310_clear(void);
+void socfpga_get_managers_addr(void);
 
 #endif /* _SOCFPGA_MISC_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6ad037e325..7844ad14cb 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -6,6 +6,8 @@
 #ifndef _RESET_MANAGER_H_
 #define _RESET_MANAGER_H_
 
+phys_addr_t socfpga_get_rstmgr_addr(void);
+
 void reset_cpu(ulong addr);
 
 void socfpga_per_reset(u32 reset, int set);
@@ -41,8 +43,9 @@ void socfpga_per_reset_all(void);
 #include <asm/arch/reset_manager_gen5.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include <asm/arch/reset_manager_arria10.h>
-#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#include <asm/arch/reset_manager_s10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+	defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+#include <asm/arch/reset_manager_soc64.h>
 #endif
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 6623ebee65..22e4eb33de 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -14,40 +14,15 @@ int socfpga_reset_deassert_bridges_handoff(void);
 void socfpga_reset_deassert_osc1wd0(void);
 int socfpga_bridges_reset(void);
 
-struct socfpga_reset_manager {
-	u32	stat;
-	u32	ramstat;
-	u32	miscstat;
-	u32	ctrl;
-	u32	hdsken;
-	u32	hdskreq;
-	u32	hdskack;
-	u32	counts;
-	u32	mpumodrst;
-	u32	per0modrst;
-	u32	per1modrst;
-	u32	brgmodrst;
-	u32	sysmodrst;
-	u32	coldmodrst;
-	u32	nrstmodrst;
-	u32	dbgmodrst;
-	u32	mpuwarmmask;
-	u32	per0warmmask;
-	u32	per1warmmask;
-	u32	brgwarmmask;
-	u32	syswarmmask;
-	u32	nrstwarmmask;
-	u32	l3warmmask;
-	u32	tststa;
-	u32	tstscratch;
-	u32	hdsktimeout;
-	u32	hmcintr;
-	u32	hmcintren;
-	u32	hmcintrens;
-	u32	hmcintrenr;
-	u32	hmcgpout;
-	u32	hmcgpin;
-};
+#define RSTMGR_A10_STATUS	0x00
+#define RSTMGR_A10_CTRL		0x0c
+#define RSTMGR_A10_MPUMODRST	0x20
+#define RSTMGR_A10_PER0MODRST	0x24
+#define RSTMGR_A10_PER1MODRST	0x28
+#define RSTMGR_A10_BRGMODRST	0x2c
+#define RSTMGR_A10_SYSMODRST	0x30
+
+#define RSTMGR_CTRL		RSTMGR_A10_CTRL
 
 /*
  * SocFPGA Arria10 reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index f4dcb14623..d108eac1e2 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -11,19 +11,15 @@
 void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
 void socfpga_bridges_reset(int enable);
 
-struct socfpga_reset_manager {
-	u32	status;
-	u32	ctrl;
-	u32	counts;
-	u32	padding1;
-	u32	mpu_mod_reset;
-	u32	per_mod_reset;
-	u32	per2_mod_reset;
-	u32	brg_mod_reset;
-	u32	misc_mod_reset;
-	u32	padding2[12];
-	u32	tstscratch;
-};
+#define RSTMGR_GEN5_STATUS	0x00
+#define RSTMGR_GEN5_CTRL	0x04
+#define RSTMGR_GEN5_MPUMODRST	0x10
+#define RSTMGR_GEN5_PERMODRST	0x14
+#define RSTMGR_GEN5_PER2MODRST	0x18
+#define RSTMGR_GEN5_BRGMODRST	0x1c
+#define RSTMGR_GEN5_MISCMODRST	0x20
+
+#define RSTMGR_CTRL		RSTMGR_GEN5_CTRL
 
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
deleted file mode 100644
index 452147b017..0000000000
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
- *
- */
-
-#ifndef	_RESET_MANAGER_S10_
-#define	_RESET_MANAGER_S10_
-
-void reset_cpu(ulong addr);
-int cpu_has_been_warmreset(void);
-
-void socfpga_bridges_reset(int enable);
-
-void socfpga_per_reset(u32 reset, int set);
-void socfpga_per_reset_all(void);
-
-struct socfpga_reset_manager {
-	u32	status;
-	u32	mpu_rst_stat;
-	u32	misc_stat;
-	u32	padding1;
-	u32	hdsk_en;
-	u32	hdsk_req;
-	u32	hdsk_ack;
-	u32	hdsk_stall;
-	u32	mpumodrst;
-	u32	per0modrst;
-	u32	per1modrst;
-	u32	brgmodrst;
-	u32	padding2;
-	u32     cold_mod_reset;
-	u32	padding3;
-	u32     dbg_mod_reset;
-	u32     tap_mod_reset;
-	u32	padding4;
-	u32	padding5;
-	u32     brg_warm_mask;
-	u32	padding6[3];
-	u32     tst_stat;
-	u32	padding7;
-	u32     hdsk_timeout;
-	u32     mpul2flushtimeout;
-	u32     dbghdsktimeout;
-};
-
-#define RSTMGR_MPUMODRST_CORE0		0
-#define RSTMGR_PER0MODRST_OCP_MASK	0x0020bf00
-#define RSTMGR_BRGMODRST_DDRSCH_MASK	0X00000040
-#define RSTMGR_BRGMODRST_FPGA2SOC_MASK	0x00000004
-
-/* Watchdogs and MPU warm reset mask */
-#define RSTMGR_L4WD_MPU_WARMRESET_MASK	0x000F0F00
-
-/*
- * Define a reset identifier, from which a permodrst bank ID
- * and reset ID can be extracted using the subsequent macros
- * RSTMGR_RESET() and RSTMGR_BANK().
- */
-#define RSTMGR_BANK_OFFSET	8
-#define RSTMGR_BANK_MASK	0x7
-#define RSTMGR_RESET_OFFSET	0
-#define RSTMGR_RESET_MASK	0x1f
-#define RSTMGR_DEFINE(_bank, _offset)		\
-	((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
-
-/* Extract reset ID from the reset identifier. */
-#define RSTMGR_RESET(_reset)			\
-	(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
-
-/* Extract bank ID from the reset identifier. */
-#define RSTMGR_BANK(_reset)			\
-	(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
-
-/*
- * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
- * 0 ... mpumodrst
- * 1 ... per0modrst
- * 2 ... per1modrst
- * 3 ... brgmodrst
- */
-#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
-#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
-#define RSTMGR_EMAC2		RSTMGR_DEFINE(1, 2)
-#define RSTMGR_USB0		RSTMGR_DEFINE(1, 3)
-#define RSTMGR_USB1		RSTMGR_DEFINE(1, 4)
-#define RSTMGR_NAND		RSTMGR_DEFINE(1, 5)
-#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 7)
-#define RSTMGR_EMAC0_OCP	RSTMGR_DEFINE(1, 8)
-#define RSTMGR_EMAC1_OCP	RSTMGR_DEFINE(1, 9)
-#define RSTMGR_EMAC2_OCP	RSTMGR_DEFINE(1, 10)
-#define RSTMGR_USB0_OCP		RSTMGR_DEFINE(1, 11)
-#define RSTMGR_USB1_OCP		RSTMGR_DEFINE(1, 12)
-#define RSTMGR_NAND_OCP		RSTMGR_DEFINE(1, 13)
-#define RSTMGR_SDMMC_OCP	RSTMGR_DEFINE(1, 15)
-#define RSTMGR_DMA		RSTMGR_DEFINE(1, 16)
-#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 17)
-#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 18)
-#define RSTMGR_L4WD0		RSTMGR_DEFINE(2, 0)
-#define RSTMGR_L4WD1		RSTMGR_DEFINE(2, 1)
-#define RSTMGR_L4WD2		RSTMGR_DEFINE(2, 2)
-#define RSTMGR_L4WD3		RSTMGR_DEFINE(2, 3)
-#define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(2, 4)
-#define RSTMGR_I2C0		RSTMGR_DEFINE(2, 8)
-#define RSTMGR_I2C1		RSTMGR_DEFINE(2, 9)
-#define RSTMGR_I2C2		RSTMGR_DEFINE(2, 10)
-#define RSTMGR_I2C3		RSTMGR_DEFINE(2, 11)
-#define RSTMGR_I2C4		RSTMGR_DEFINE(2, 12)
-#define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
-#define RSTMGR_UART1		RSTMGR_DEFINE(2, 17)
-#define RSTMGR_GPIO0		RSTMGR_DEFINE(2, 24)
-#define RSTMGR_GPIO1		RSTMGR_DEFINE(2, 25)
-#define RSTMGR_SDR		RSTMGR_DEFINE(3, 6)
-
-/* Create a human-readable reference to SoCFPGA reset. */
-#define SOCFPGA_RESET(_name)	RSTMGR_##_name
-
-#endif /* _RESET_MANAGER_S10_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
new file mode 100644
index 0000000000..3f952bcc6e
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _RESET_MANAGER_SOC64_H_
+#define _RESET_MANAGER_SOC64_H_
+
+void reset_deassert_peripherals_handoff(void);
+int cpu_has_been_warmreset(void);
+void socfpga_bridges_reset(int enable);
+
+#define RSTMGR_SOC64_STATUS	0x00
+#define RSTMGR_SOC64_MPUMODRST	0x20
+#define RSTMGR_SOC64_PER0MODRST	0x24
+#define RSTMGR_SOC64_PER1MODRST	0x28
+#define RSTMGR_SOC64_BRGMODRST	0x2c
+
+#define RSTMGR_MPUMODRST_CORE0		0
+#define RSTMGR_PER0MODRST_OCP_MASK	0x0020bf00
+#define RSTMGR_BRGMODRST_DDRSCH_MASK	0X00000040
+#define RSTMGR_BRGMODRST_FPGA2SOC_MASK	0x00000004
+
+/* Watchdogs and MPU warm reset mask */
+#define RSTMGR_L4WD_MPU_WARMRESET_MASK	0x000F0F00
+
+/*
+ * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ */
+#define RSTMGR_L4WD0		RSTMGR_DEFINE(2, 0)
+#define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(2, 4)
+#define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
+
+#endif /* _RESET_MANAGER_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 7e76df74b7..6de0a08131 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -6,8 +6,11 @@
 #ifndef _SYSTEM_MANAGER_H_
 #define _SYSTEM_MANAGER_H_
 
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#include <asm/arch/system_manager_s10.h>
+phys_addr_t socfpga_get_sysmgr_addr(void);
+
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+	defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+#include <asm/arch/system_manager_soc64.h>
 #else
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	BIT(0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	BIT(1)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
index 14052b957c..e4fc6d2e55 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
@@ -6,73 +6,33 @@
 #ifndef _SYSTEM_MANAGER_ARRIA10_H_
 #define _SYSTEM_MANAGER_ARRIA10_H_
 
-struct socfpga_system_manager {
-	u32  siliconid1;
-	u32  siliconid2;
-	u32  wddbg;
-	u32  bootinfo;
-	u32  mpu_ctrl_l2_ecc;
-	u32  _pad_0x14_0x1f[3];
-	u32  dma;
-	u32  dma_periph;
-	u32  sdmmcgrp_ctrl;
-	u32  sdmmc_l3master;
-	u32  nand_bootstrap;
-	u32  nand_l3master;
-	u32  usb0_l3master;
-	u32  usb1_l3master;
-	u32  emac_global;
-	u32  emac[3];
-	u32  _pad_0x50_0x5f[4];
-	u32  fpgaintf_en_global;
-	u32  fpgaintf_en_0;
-	u32  fpgaintf_en_1;
-	u32  fpgaintf_en_2;
-	u32  fpgaintf_en_3;
-	u32  _pad_0x74_0x7f[3];
-	u32  noc_addr_remap_value;
-	u32  noc_addr_remap_set;
-	u32  noc_addr_remap_clear;
-	u32  _pad_0x8c_0x8f;
-	u32  ecc_intmask_value;
-	u32  ecc_intmask_set;
-	u32  ecc_intmask_clr;
-	u32  ecc_intstatus_serr;
-	u32  ecc_intstatus_derr;
-	u32  mpu_status_l2_ecc;
-	u32  mpu_clear_l2_ecc;
-	u32  mpu_status_l1_parity;
-	u32  mpu_clear_l1_parity;
-	u32  mpu_set_l1_parity;
-	u32  _pad_0xb8_0xbf[2];
-	u32  noc_timeout;
-	u32  noc_idlereq_set;
-	u32  noc_idlereq_clr;
-	u32  noc_idlereq_value;
-	u32  noc_idleack;
-	u32  noc_idlestatus;
-	u32  fpga2soc_ctrl;
-	u32  _pad_0xdc_0xff[9];
-	u32  tsmc_tsel_0;
-	u32  tsmc_tsel_1;
-	u32  tsmc_tsel_2;
-	u32  tsmc_tsel_3;
-	u32  _pad_0x110_0x200[60];
-	u32  romhw_ctrl;
-	u32  romcode_ctrl;
-	u32  romcode_cpu1startaddr;
-	u32  romcode_initswstate;
-	u32  romcode_initswlastld;
-	u32  _pad_0x214_0x217;
-	u32  warmram_enable;
-	u32  warmram_datastart;
-	u32  warmram_length;
-	u32  warmram_execution;
-	u32  warmram_crc;
-	u32  _pad_0x22c_0x22f;
-	u32  isw_handoff[8];
-	u32  romcode_bootromswstate[8];
-};
+#define SYSMGR_A10_WDDBG			0x08
+#define SYSMGR_A10_BOOTINFO			0x0c
+#define SYSMGR_A10_DMA				0x20
+#define SYSMGR_A10_DMA_PERIPH			0x24
+#define SYSMGR_A10_SDMMC			0x28
+#define SYSMGR_A10_SDMMC_L3MASTER		0x2c
+#define SYSMGR_A10_EMAC_GLOBAL			0x40
+#define SYSMGR_A10_EMAC0			0x44
+#define SYSMGR_A10_EMAC1			0x48
+#define SYSMGR_A10_EMAC2			0x4c
+#define SYSMGR_A10_FPGAINTF_EN_GLOBAL		0x60
+#define SYSMGR_A10_FPGAINTF_EN0			0x64
+#define SYSMGR_A10_FPGAINTF_EN1			0x68
+#define SYSMGR_A10_FPGAINTF_EN2			0x6c
+#define SYSMGR_A10_FPGAINTF_EN3			0x70
+#define SYSMGR_A10_ECC_INTMASK_VAL		0x90
+#define SYSMGR_A10_ECC_INTMASK_SET		0x94
+#define SYSMGR_A10_ECC_INTMASK_CLR		0x98
+#define SYSMGR_A10_NOC_TIMEOUT			0xc0
+#define SYSMGR_A10_NOC_IDLEREQ_SET		0xc4
+#define SYSMGR_A10_NOC_IDLEREQ_CLR		0xc8
+#define SYSMGR_A10_NOC_IDLEREQ_VAL		0xcc
+#define SYSMGR_A10_NOC_IDLEACK			0xd0
+#define SYSMGR_A10_NOC_IDLESTATUS		0xd4
+#define SYSMGR_A10_FPGA2SOC_CTRL		0xd8
+
+#define SYSMGR_SDMMC				SYSMGR_A10_SDMMC
 
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
 #define SYSMGR_BOOTINFO_BSEL_SHIFT	12
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
index 52e59df513..90cb465d13 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
@@ -13,106 +13,29 @@ void sysmgr_config_warmrstcfgio(int enable);
 
 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
 
-struct socfpga_system_manager {
-	/* System Manager Module */
-	u32	siliconid1;			/* 0x00 */
-	u32	siliconid2;
-	u32	_pad_0x8_0xf[2];
-	u32	wddbg;				/* 0x10 */
-	u32	bootinfo;
-	u32	hpsinfo;
-	u32	parityinj;
-	/* FPGA Interface Group */
-	u32	fpgaintfgrp_gbl;		/* 0x20 */
-	u32	fpgaintfgrp_indiv;
-	u32	fpgaintfgrp_module;
-	u32	_pad_0x2c_0x2f;
-	/* Scan Manager Group */
-	u32	scanmgrgrp_ctrl;		/* 0x30 */
-	u32	_pad_0x34_0x3f[3];
-	/* Freeze Control Group */
-	u32	frzctrl_vioctrl;		/* 0x40 */
-	u32	_pad_0x44_0x4f[3];
-	u32	frzctrl_hioctrl;		/* 0x50 */
-	u32	frzctrl_src;
-	u32	frzctrl_hwctrl;
-	u32	_pad_0x5c_0x5f;
-	/* EMAC Group */
-	u32	emacgrp_ctrl;			/* 0x60 */
-	u32	emacgrp_l3master;
-	u32	_pad_0x68_0x6f[2];
-	/* DMA Controller Group */
-	u32	dmagrp_ctrl;			/* 0x70 */
-	u32	dmagrp_persecurity;
-	u32	_pad_0x78_0x7f[2];
-	/* Preloader (initial software) Group */
-	u32	iswgrp_handoff[8];		/* 0x80 */
-	u32	_pad_0xa0_0xbf[8];		/* 0xa0 */
-	/* Boot ROM Code Register Group */
-	u32	romcodegrp_ctrl;		/* 0xc0 */
-	u32	romcodegrp_cpu1startaddr;
-	u32	romcodegrp_initswstate;
-	u32	romcodegrp_initswlastld;
-	u32	romcodegrp_bootromswstate;	/* 0xd0 */
-	u32	__pad_0xd4_0xdf[3];
-	/* Warm Boot from On-Chip RAM Group */
-	u32	romcodegrp_warmramgrp_enable;	/* 0xe0 */
-	u32	romcodegrp_warmramgrp_datastart;
-	u32	romcodegrp_warmramgrp_length;
-	u32	romcodegrp_warmramgrp_execution;
-	u32	romcodegrp_warmramgrp_crc;	/* 0xf0 */
-	u32	__pad_0xf4_0xff[3];
-	/* Boot ROM Hardware Register Group */
-	u32	romhwgrp_ctrl;			/* 0x100 */
-	u32	_pad_0x104_0x107;
-	/* SDMMC Controller Group */
-	u32	sdmmcgrp_ctrl;
-	u32	sdmmcgrp_l3master;
-	/* NAND Flash Controller Register Group */
-	u32	nandgrp_bootstrap;		/* 0x110 */
-	u32	nandgrp_l3master;
-	/* USB Controller Group */
-	u32	usbgrp_l3master;
-	u32	_pad_0x11c_0x13f[9];
-	/* ECC Management Register Group */
-	u32	eccgrp_l2;			/* 0x140 */
-	u32	eccgrp_ocram;
-	u32	eccgrp_usb0;
-	u32	eccgrp_usb1;
-	u32	eccgrp_emac0;			/* 0x150 */
-	u32	eccgrp_emac1;
-	u32	eccgrp_dma;
-	u32	eccgrp_can0;
-	u32	eccgrp_can1;			/* 0x160 */
-	u32	eccgrp_nand;
-	u32	eccgrp_qspi;
-	u32	eccgrp_sdmmc;
-	u32	_pad_0x170_0x3ff[164];
-	/* Pin Mux Control Group */
-	u32	emacio[20];			/* 0x400 */
-	u32	flashio[12];			/* 0x450 */
-	u32	generalio[28];			/* 0x480 */
-	u32	_pad_0x4f0_0x4ff[4];
-	u32	mixed1io[22];			/* 0x500 */
-	u32	mixed2io[8];			/* 0x558 */
-	u32	gplinmux[23];			/* 0x578 */
-	u32	gplmux[71];			/* 0x5d4 */
-	u32	nandusefpga;			/* 0x6f0 */
-	u32	_pad_0x6f4;
-	u32	rgmii1usefpga;			/* 0x6f8 */
-	u32	_pad_0x6fc_0x700[2];
-	u32	i2c0usefpga;			/* 0x704 */
-	u32	sdmmcusefpga;			/* 0x708 */
-	u32	_pad_0x70c_0x710[2];
-	u32	rgmii0usefpga;			/* 0x714 */
-	u32	_pad_0x718_0x720[3];
-	u32	i2c3usefpga;			/* 0x724 */
-	u32	i2c2usefpga;			/* 0x728 */
-	u32	i2c1usefpga;			/* 0x72c */
-	u32	spim1usefpga;			/* 0x730 */
-	u32	_pad_0x734;
-	u32	spim0usefpga;			/* 0x738 */
-};
+#define SYSMGR_GEN5_WDDBG			0x10
+#define SYSMGR_GEN5_BOOTINFO			0x14
+#define SYSMGR_GEN5_FPGAINFGRP_GBL		0x20
+#define SYSMGR_GEN5_FPGAINFGRP_INDIV		0x24
+#define SYSMGR_GEN5_FPGAINFGRP_MODULE		0x28
+#define SYSMGR_GEN5_SCANMGRGRP_CTRL		0x30
+#define SYSMGR_GEN5_ISWGRP_HANDOFF		0x80
+#define SYSMGR_GEN5_ROMCODEGRP_CTRL		0xc0
+#define SYSMGR_GEN5_WARMRAMGRP_EN		0xe0
+#define SYSMGR_GEN5_SDMMC			0x108
+#define SYSMGR_GEN5_ECCGRP_OCRAM		0x144
+#define SYSMGR_GEN5_EMACIO			0x400
+#define SYSMGR_GEN5_NAND_USEFPGA		0x6f0
+#define SYSMGR_GEN5_RGMII0_USEFPGA		0x6f8
+#define SYSMGR_GEN5_SDMMC_USEFPGA		0x708
+#define SYSMGR_GEN5_RGMII1_USEFPGA		0x704
+#define SYSMGR_GEN5_SPIM1_USEFPGA		0x730
+#define SYSMGR_GEN5_SPIM0_USEFPGA		0x738
+
+#define SYSMGR_SDMMC				SYSMGR_GEN5_SDMMC
+
+#define SYSMGR_ISWGRP_HANDOFF_OFFSET(i)	\
+	SYSMGR_GEN5_ISWGRP_HANDOFF + ((i) * sizeof(u32))
 #endif
 
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT	3
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
deleted file mode 100644
index 297f9e1999..0000000000
--- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
- *
- */
-
-#ifndef	_SYSTEM_MANAGER_S10_
-#define	_SYSTEM_MANAGER_S10_
-
-void sysmgr_pinmux_init(void);
-void populate_sysmgr_fpgaintf_module(void);
-void populate_sysmgr_pinmux(void);
-void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
-
-struct socfpga_system_manager {
-	/* System Manager Module */
-	u32	siliconid1;			/* 0x00 */
-	u32	siliconid2;
-	u32	wddbg;
-	u32	_pad_0xc;
-	u32	mpu_status;			/* 0x10 */
-	u32	mpu_ace;
-	u32	_pad_0x18_0x1c[2];
-	u32	dma;				/* 0x20 */
-	u32	dma_periph;
-	/* SDMMC Controller Group */
-	u32	sdmmcgrp_ctrl;
-	u32	sdmmcgrp_l3master;
-	/* NAND Flash Controller Register Group */
-	u32	nandgrp_bootstrap;		/* 0x30 */
-	u32	nandgrp_l3master;
-	/* USB Controller Group */
-	u32	usb0_l3master;
-	u32	usb1_l3master;
-	/* EMAC Group */
-	u32	emac_gbl;			/* 0x40 */
-	u32	emac0;
-	u32	emac1;
-	u32	emac2;
-	u32	emac0_ace;			/* 0x50 */
-	u32	emac1_ace;
-	u32	emac2_ace;
-	u32	nand_axuser;
-	u32	_pad_0x60_0x64[2];		/* 0x60 */
-	/* FPGA interface Group */
-	u32	fpgaintf_en_1;
-	u32	fpgaintf_en_2;
-	u32	fpgaintf_en_3;			/* 0x70 */
-	u32	dma_l3master;
-	u32	etr_l3master;
-	u32	_pad_0x7c;
-	u32	sec_ctrl_slt;			/* 0x80 */
-	u32	osc_trim;
-	u32	_pad_0x88_0x8c[2];
-	/* ECC Group */
-	u32	ecc_intmask_value;		/* 0x90 */
-	u32	ecc_intmask_set;
-	u32	ecc_intmask_clr;
-	u32	ecc_intstatus_serr;
-	u32	ecc_intstatus_derr;		/* 0xa0 */
-	u32	_pad_0xa4_0xac[3];
-	u32	noc_addr_remap;			/* 0xb0 */
-	u32	hmc_clk;
-	u32	io_pa_ctrl;
-	u32	_pad_0xbc;
-	/* NOC Group */
-	u32	noc_timeout;			/* 0xc0 */
-	u32	noc_idlereq_set;
-	u32	noc_idlereq_clr;
-	u32	noc_idlereq_value;
-	u32	noc_idleack;			/* 0xd0 */
-	u32	noc_idlestatus;
-	u32	fpga2soc_ctrl;
-	u32	fpga_config;
-	u32	iocsrclk_gate;			/* 0xe0 */
-	u32	gpo;
-	u32	gpi;
-	u32	_pad_0xec;
-	u32	mpu;				/* 0xf0 */
-	u32	sdm_hps_spare;
-	u32	hps_sdm_spare;
-	u32	_pad_0xfc_0x1fc[65];
-	/* Boot scratch register group */
-	u32	boot_scratch_cold0;		/* 0x200 */
-	u32	boot_scratch_cold1;
-	u32	boot_scratch_cold2;
-	u32	boot_scratch_cold3;
-	u32	boot_scratch_cold4;		/* 0x210 */
-	u32	boot_scratch_cold5;
-	u32	boot_scratch_cold6;
-	u32	boot_scratch_cold7;
-	u32	boot_scratch_cold8;		/* 0x220 */
-	u32	boot_scratch_cold9;
-	u32	_pad_0x228_0xffc[886];
-	/* Pin select and pin control group */
-	u32	pinsel0[40];			/* 0x1000 */
-	u32	_pad_0x10a0_0x10fc[24];
-	u32	pinsel40[8];
-	u32	_pad_0x1120_0x112c[4];
-	u32	ioctrl0[28];
-	u32	_pad_0x11a0_0x11fc[24];
-	u32	ioctrl28[20];
-	u32	_pad_0x1250_0x12fc[44];
-	/* Use FPGA mux */
-	u32	rgmii0usefpga;			/* 0x1300 */
-	u32	rgmii1usefpga;
-	u32	rgmii2usefpga;
-	u32	i2c0usefpga;
-	u32	i2c1usefpga;
-	u32	i2c_emac0_usefpga;
-	u32	i2c_emac1_usefpga;
-	u32	i2c_emac2_usefpga;
-	u32	nandusefpga;
-	u32	_pad_0x1324;
-	u32	spim0usefpga;
-	u32	spim1usefpga;
-	u32	spis0usefpga;
-	u32	spis1usefpga;
-	u32	uart0usefpga;
-	u32	uart1usefpga;
-	u32	mdio0usefpga;
-	u32	mdio1usefpga;
-	u32	mdio2usefpga;
-	u32	_pad_0x134c;
-	u32	jtagusefpga;
-	u32	sdmmcusefpga;
-	u32	hps_osc_clk;
-	u32	_pad_0x135c_0x13fc[41];
-	u32	iodelay0[40];
-	u32	_pad_0x14a0_0x14fc[24];
-	u32	iodelay40[8];
-
-};
-
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	BIT(0)
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	BIT(1)
-#define SYSMGR_ECC_OCRAM_EN	BIT(0)
-#define SYSMGR_ECC_OCRAM_SERR	BIT(3)
-#define SYSMGR_ECC_OCRAM_DERR	BIT(4)
-#define SYSMGR_FPGAINTF_USEFPGA	0x1
-
-#define SYSMGR_FPGAINTF_NAND	BIT(4)
-#define SYSMGR_FPGAINTF_SDMMC	BIT(8)
-#define SYSMGR_FPGAINTF_SPIM0	BIT(16)
-#define SYSMGR_FPGAINTF_SPIM1	BIT(24)
-#define SYSMGR_FPGAINTF_EMAC0	BIT(0)
-#define SYSMGR_FPGAINTF_EMAC1	BIT(8)
-#define SYSMGR_FPGAINTF_EMAC2	BIT(16)
-
-#define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
-#define SYSMGR_SDMMC_DRVSEL_SHIFT	0
-
-/* EMAC Group Bit definitions */
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
-
-#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB			0
-#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
-
-#define SYSMGR_NOC_H2F_MSK		0x00000001
-#define SYSMGR_NOC_LWH2F_MSK		0x00000010
-#define SYSMGR_HMC_CLK_STATUS_MSK	0x00000001
-
-#define SYSMGR_DMA_IRQ_NS		0xFF000000
-#define SYSMGR_DMA_MGR_NS		0x00010000
-
-#define SYSMGR_DMAPERIPH_ALL_NS		0xFFFFFFFF
-
-#define SYSMGR_WDDBG_PAUSE_ALL_CPU	0x0F0F0F0F
-
-#endif /* _SYSTEM_MANAGER_S10_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
new file mode 100644
index 0000000000..3a6c9515c6
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _SYSTEM_MANAGER_SOC64_H_
+#define _SYSTEM_MANAGER_SOC64_H_
+
+void sysmgr_pinmux_init(void);
+void populate_sysmgr_fpgaintf_module(void);
+void populate_sysmgr_pinmux(void);
+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
+
+#define SYSMGR_SOC64_WDDBG			0x08
+#define SYSMGR_SOC64_DMA			0x20
+#define SYSMGR_SOC64_DMA_PERIPH			0x24
+#define SYSMGR_SOC64_SDMMC			0x28
+#define SYSMGR_SOC64_SDMMC_L3MASTER		0x2c
+#define SYSMGR_SOC64_EMAC_GLOBAL		0x40
+#define SYSMGR_SOC64_EMAC0			0x44
+#define SYSMGR_SOC64_EMAC1			0x48
+#define SYSMGR_SOC64_EMAC2			0x4c
+#define SYSMGR_SOC64_EMAC0_ACE			0x50
+#define SYSMGR_SOC64_EMAC1_ACE			0x54
+#define SYSMGR_SOC64_EMAC2_ACE			0x58
+#define SYSMGR_SOC64_NAND_AXUSER		0x5c
+#define SYSMGR_SOC64_FPGAINTF_EN1		0x68
+#define SYSMGR_SOC64_FPGAINTF_EN2		0x6c
+#define SYSMGR_SOC64_FPGAINTF_EN3		0x70
+#define SYSMGR_SOC64_DMA_L3MASTER		0x74
+#define SYSMGR_SOC64_HMC_CLK			0xb4
+#define SYSMGR_SOC64_IO_PA_CTRL			0xb8
+#define SYSMGR_SOC64_NOC_TIMEOUT		0xc0
+#define SYSMGR_SOC64_NOC_IDLEREQ_SET		0xc4
+#define SYSMGR_SOC64_NOC_IDLEREQ_CLR		0xc8
+#define SYSMGR_SOC64_NOC_IDLEREQ_VAL		0xcc
+#define SYSMGR_SOC64_NOC_IDLEACK		0xd0
+#define SYSMGR_SOC64_NOC_IDLESTATUS		0xd4
+#define SYSMGR_SOC64_FPGA2SOC_CTRL		0xd8
+#define SYSMGR_SOC64_FPGA_CONFIG		0xdc
+#define SYSMGR_SOC64_IOCSRCLK_GATE		0xe0
+#define SYSMGR_SOC64_GPO			0xe4
+#define SYSMGR_SOC64_GPI			0xe8
+#define SYSMGR_SOC64_MPU			0xf0
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0		0x200
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1		0x204
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2		0x208
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3		0x20c
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4		0x210
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5		0x214
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6		0x218
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7		0x21c
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8		0x220
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9		0x224
+#define SYSMGR_SOC64_PINSEL0			0x1000
+#define SYSMGR_SOC64_IOCTRL0			0x1130
+#define SYSMGR_SOC64_EMAC0_USEFPGA		0x1300
+#define SYSMGR_SOC64_EMAC1_USEFPGA		0x1304
+#define SYSMGR_SOC64_EMAC2_USEFPGA		0x1308
+#define SYSMGR_SOC64_I2C0_USEFPGA		0x130c
+#define SYSMGR_SOC64_I2C1_USEFPGA		0x1310
+#define SYSMGR_SOC64_I2C_EMAC0_USEFPGA		0x1314
+#define SYSMGR_SOC64_I2C_EMAC1_USEFPGA		0x1318
+#define SYSMGR_SOC64_I2C_EMAC2_USEFPGA		0x131c
+#define SYSMGR_SOC64_NAND_USEFPGA		0x1320
+#define SYSMGR_SOC64_SPIM0_USEFPGA		0x1328
+#define SYSMGR_SOC64_SPIM1_USEFPGA		0x132c
+#define SYSMGR_SOC64_SPIS0_USEFPGA		0x1330
+#define SYSMGR_SOC64_SPIS1_USEFPGA		0x1334
+#define SYSMGR_SOC64_UART0_USEFPGA		0x1338
+#define SYSMGR_SOC64_UART1_USEFPGA		0x133c
+#define SYSMGR_SOC64_MDIO0_USEFPGA		0x1340
+#define SYSMGR_SOC64_MDIO1_USEFPGA		0x1344
+#define SYSMGR_SOC64_MDIO2_USEFPGA		0x1348
+#define SYSMGR_SOC64_JTAG_USEFPGA		0x1350
+#define SYSMGR_SOC64_SDMMC_USEFPGA		0x1354
+#define SYSMGR_SOC64_HPS_OSC_CLK		0x1358
+#define SYSMGR_SOC64_IODELAY0			0x1400
+
+#define SYSMGR_SDMMC				SYSMGR_SOC64_SDMMC
+
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	BIT(0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	BIT(1)
+#define SYSMGR_ECC_OCRAM_EN	BIT(0)
+#define SYSMGR_ECC_OCRAM_SERR	BIT(3)
+#define SYSMGR_ECC_OCRAM_DERR	BIT(4)
+#define SYSMGR_FPGAINTF_USEFPGA	0x1
+
+#define SYSMGR_FPGAINTF_NAND	BIT(4)
+#define SYSMGR_FPGAINTF_SDMMC	BIT(8)
+#define SYSMGR_FPGAINTF_SPIM0	BIT(16)
+#define SYSMGR_FPGAINTF_SPIM1	BIT(24)
+#define SYSMGR_FPGAINTF_EMAC0	BIT(0)
+#define SYSMGR_FPGAINTF_EMAC1	BIT(8)
+#define SYSMGR_FPGAINTF_EMAC2	BIT(16)
+
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
+#define SYSMGR_SDMMC_DRVSEL_SHIFT	0
+
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB			0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
+
+#define SYSMGR_NOC_H2F_MSK		0x00000001
+#define SYSMGR_NOC_LWH2F_MSK		0x00000010
+#define SYSMGR_HMC_CLK_STATUS_MSK	0x00000001
+
+#define SYSMGR_DMA_IRQ_NS		0xFF000000
+#define SYSMGR_DMA_MGR_NS		0x00010000
+
+#define SYSMGR_DMAPERIPH_ALL_NS		0xFFFFFFFF
+
+#define SYSMGR_WDDBG_PAUSE_ALL_CPU	0x0F0F0F0F
+
+#endif /* _SYSTEM_MANAGER_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 4498ab55df..3254bc1805 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -287,9 +287,6 @@ int mbox_qspi_close(void)
 
 int mbox_qspi_open(void)
 {
-	static const struct socfpga_system_manager *sysmgr_regs =
-		(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 	int ret;
 	u32 resp_buf[1];
 	u32 resp_buf_len;
@@ -318,7 +315,8 @@ int mbox_qspi_open(void)
 
 	/* We are getting QSPI ref clock and set into sysmgr boot register */
 	printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
-	writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0);
+	writel(resp_buf[0],
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
 
 	return 0;
 
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 904b3d030a..db71105af3 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -23,6 +23,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+phys_addr_t socfpga_clkmgr_base __section(".data");
+phys_addr_t socfpga_rstmgr_base __section(".data");
+phys_addr_t socfpga_sysmgr_base __section(".data");
+
 #ifdef CONFIG_SYS_L2_PL310
 static const struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -146,6 +150,8 @@ void socfpga_fpga_add(void *fpga_desc)
 
 int arch_cpu_init(void)
 {
+	socfpga_get_managers_addr();
+
 #ifdef CONFIG_HW_WATCHDOG
 	/*
 	 * In case the watchdog is enabled, make sure to (re-)configure it
@@ -203,3 +209,63 @@ U_BOOT_CMD(bridge, 3, 1, do_bridge,
 );
 
 #endif
+
+static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
+{
+	const void *blob = gd->fdt_blob;
+	struct fdt_resource r;
+	int node;
+	int ret;
+
+	node = fdt_node_offset_by_compatible(blob, -1, compat);
+	if (node < 0)
+		return node;
+
+	if (!fdtdec_get_is_enabled(blob, node))
+		return -ENODEV;
+
+	ret = fdt_get_resource(blob, node, "reg", 0, &r);
+	if (ret)
+		return ret;
+
+	*base = (phys_addr_t)r.start;
+
+	return 0;
+}
+
+void socfpga_get_managers_addr(void)
+{
+	int ret;
+
+	ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
+	if (ret)
+		hang();
+
+	ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
+	if (ret)
+		hang();
+
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+	ret = socfpga_get_base_addr("intel,agilex-clkmgr",
+				    &socfpga_clkmgr_base);
+#else
+	ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
+#endif
+	if (ret)
+		hang();
+}
+
+phys_addr_t socfpga_get_rstmgr_addr(void)
+{
+	return socfpga_rstmgr_base;
+}
+
+phys_addr_t socfpga_get_sysmgr_addr(void)
+{
+	return socfpga_sysmgr_base;
+}
+
+phys_addr_t socfpga_get_clkmgr_addr(void)
+{
+	return socfpga_clkmgr_base;
+}
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 2e2a40b65d..d56349b7f3 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -28,9 +28,6 @@
 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7	0x78
 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3	0x98
 
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 /*
  * FPGA programming support for SoC FPGA Arria 10
  */
@@ -81,7 +78,8 @@ void socfpga_init_security_policies(void)
 	writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
 	writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
 
-	writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
+	writel(0x0007FFFF,
+	       socfpga_get_sysmgr_addr() + SYSMGR_A10_ECC_INTMASK_SET);
 }
 
 void socfpga_sdram_remap_zero(void)
@@ -105,8 +103,9 @@ int arch_early_init_r(void)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
-	const u32 bsel =
-		SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
+	const u32 bootinfo = readl(socfpga_get_sysmgr_addr() +
+				   SYSMGR_A10_BOOTINFO);
+	const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
 
 	puts("CPU:   Altera SoCFPGA Arria 10\n");
 
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 22042d0de0..35938b2dfc 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 static struct nic301_registers *nic301_regs =
 	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 static struct scu_registers *scu_regs =
@@ -120,8 +118,9 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
-	const u32 bsel =
-		SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
+	const u32 bootinfo = readl(socfpga_get_sysmgr_addr() +
+				   SYSMGR_GEN5_BOOTINFO);
+	const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
 
 	puts("CPU:   Altera SoCFPGA Platform\n");
 	socfpga_fpga_id(1);
@@ -134,7 +133,8 @@ int print_cpuinfo(void)
 #ifdef CONFIG_ARCH_MISC_INIT
 int arch_misc_init(void)
 {
-	const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
+	const u32 bsel = readl(socfpga_get_sysmgr_addr() +
+			       SYSMGR_GEN5_BOOTINFO) & 0x7;
 	const int fpga_id = socfpga_fpga_id(0);
 	env_set("bootmode", bsel_str[bsel].mode);
 	if (fpga_id >= 0)
@@ -192,10 +192,12 @@ int arch_early_init_r(void)
 	 * to support that old code, we write it here instead of in the
 	 * reset_cpu() function just before resetting the CPU.
 	 */
-	writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
+	writel(0xae9efebc,
+	       socfpga_get_sysmgr_addr() + SYSMGR_GEN5_WARMRAMGRP_EN);
 
 	for (i = 0; i < 8; i++)	/* Cache initial SW setting regs */
-		iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
+		iswgrp_handoff[i] = readl(socfpga_get_sysmgr_addr() +
+					  SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
 
 	socfpga_bridges_reset(1);
 
@@ -208,8 +210,6 @@ int arch_early_init_r(void)
 }
 
 #ifndef CONFIG_SPL_BUILD
-static struct socfpga_reset_manager *reset_manager_base =
-	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
 static struct socfpga_sdr_ctrl *sdr_ctrl =
 	(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 
@@ -223,20 +223,26 @@ void do_bridge_reset(int enable, unsigned int mask)
 						 !(mask & BIT(2)));
 		for (i = 0; i < 2; i++) {	/* Reload SW setting cache */
 			iswgrp_handoff[i] =
-				readl(&sysmgr_regs->iswgrp_handoff[i]);
+				readl(socfpga_get_sysmgr_addr() +
+				      SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
 		}
 
-		writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
+		writel(iswgrp_handoff[2],
+		       socfpga_get_sysmgr_addr() +
+		       SYSMGR_GEN5_FPGAINFGRP_MODULE);
 		writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
-		writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
+		writel(iswgrp_handoff[0],
+		       socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 		writel(iswgrp_handoff[1], &nic301_regs->remap);
 
-		writel(0x7, &reset_manager_base->brg_mod_reset);
-		writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
+		writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
+		writel(iswgrp_handoff[0],
+		       socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 	} else {
-		writel(0, &sysmgr_regs->fpgaintfgrp_module);
+		writel(0, socfpga_get_sysmgr_addr() +
+		       SYSMGR_GEN5_FPGAINFGRP_MODULE);
 		writel(0, &sdr_ctrl->fpgaport_rst);
-		writel(0x7, &reset_manager_base->brg_mod_reset);
+		writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 		writel(1, &nic301_regs->remap);
 	}
 }
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 0a5fab11c0..a3f5b4364e 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -23,9 +23,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 /*
  * FPGA programming support for SoC FPGA Stratix 10
  */
@@ -68,9 +65,9 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
 	else
 		return -EINVAL;
 
-	clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
-			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
-			modereg);
+	clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
+			gmac_index,
+			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
 
 	return 0;
 }
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 471a3045af..aa5299415a 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -15,11 +15,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_reset_manager *reset_manager_base =
-		(void *)SOCFPGA_RSTMGR_ADDRESS;
-static const struct socfpga_system_manager *sysmgr_regs =
-		(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 struct bridge_cfg {
 	int compat_id;
 	u32  mask_noc;
@@ -63,14 +58,14 @@ static const struct bridge_cfg bridge_cfg_tbl[] = {
 void socfpga_watchdog_disable(void)
 {
 	/* assert reset for watchdog */
-	setbits_le32(&reset_manager_base->per1modrst,
+	setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
 		     ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
 }
 
 /* Release NOC ddr scheduler from reset */
 void socfpga_reset_deassert_noc_ddr_scheduler(void)
 {
-	clrbits_le32(&reset_manager_base->brgmodrst,
+	clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
 		     ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
 }
 
@@ -100,20 +95,23 @@ int socfpga_reset_deassert_bridges_handoff(void)
 	}
 
 	/* clear idle request to all bridges */
-	setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
+	setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_CLR,
+		     mask_noc);
 
 	/* Release bridges from reset state per handoff value */
-	clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
+	clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
+		     mask_rstmgr);
 
 	/* Poll until all idleack to 0, timeout at 1000ms */
-	return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
-				 false, 1000, false);
+	return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
+				 SYSMGR_A10_NOC_IDLEACK),
+				 mask_noc, false, 1000, false);
 }
 
 /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
 void socfpga_reset_deassert_osc1wd0(void)
 {
-	clrbits_le32(&reset_manager_base->per1modrst,
+	clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
 		     ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
 }
 
@@ -122,24 +120,24 @@ void socfpga_reset_deassert_osc1wd0(void)
  */
 void socfpga_per_reset(u32 reset, int set)
 {
-	const u32 *reg;
+	unsigned long reg;
 	u32 rstmgr_bank = RSTMGR_BANK(reset);
 
 	switch (rstmgr_bank) {
 	case 0:
-		reg = &reset_manager_base->mpumodrst;
+		reg = RSTMGR_A10_MPUMODRST;
 		break;
 	case 1:
-		reg = &reset_manager_base->per0modrst;
+		reg = RSTMGR_A10_PER0MODRST;
 		break;
 	case 2:
-		reg = &reset_manager_base->per1modrst;
+		reg = RSTMGR_A10_PER1MODRST;
 		break;
 	case 3:
-		reg = &reset_manager_base->brgmodrst;
+		reg = RSTMGR_A10_BRGMODRST;
 		break;
 	case 4:
-		reg = &reset_manager_base->sysmodrst;
+		reg = RSTMGR_A10_SYSMODRST;
 		break;
 
 	default:
@@ -147,9 +145,11 @@ void socfpga_per_reset(u32 reset, int set)
 	}
 
 	if (set)
-		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+		setbits_le32(socfpga_get_rstmgr_addr() + reg,
+			     1 << RSTMGR_RESET(reset));
 	else
-		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+		clrbits_le32(socfpga_get_rstmgr_addr() + reg,
+			     1 << RSTMGR_RESET(reset));
 }
 
 /*
@@ -174,11 +174,13 @@ void socfpga_per_reset_all(void)
 		ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
 
 	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
-	writel(~l4wd0, &reset_manager_base->per1modrst);
-	setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
+	writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST);
+	setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
+		     ~mask_ecc_ocp);
 
 	/* Finally disable the ECC_OCP */
-	setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
+	setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
+		     mask_ecc_ocp);
 }
 
 int socfpga_bridges_reset(void)
@@ -194,13 +196,15 @@ int socfpga_bridges_reset(void)
 		ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
 		ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
 		ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
-		&sysmgr_regs->noc_idlereq_set);
+		socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_SET);
 
 	/* Enable the NOC timeout */
-	writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
+	writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK,
+	       socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT);
 
 	/* Poll until all idleack to 1 */
-	ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
+	ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
+				SYSMGR_A10_NOC_IDLEACK),
 				ALT_SYSMGR_NOC_H2F_SET_MSK |
 				ALT_SYSMGR_NOC_LWH2F_SET_MSK |
 				ALT_SYSMGR_NOC_F2H_SET_MSK |
@@ -212,7 +216,8 @@ int socfpga_bridges_reset(void)
 		return ret;
 
 	/* Poll until all idlestatus to 1 */
-	ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
+	ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
+				SYSMGR_A10_NOC_IDLESTATUS),
 				ALT_SYSMGR_NOC_H2F_SET_MSK |
 				ALT_SYSMGR_NOC_LWH2F_SET_MSK |
 				ALT_SYSMGR_NOC_F2H_SET_MSK |
@@ -224,16 +229,16 @@ int socfpga_bridges_reset(void)
 		return ret;
 
 	/* Put all bridges (except NOR DDR scheduler) into reset state */
-	setbits_le32(&reset_manager_base->brgmodrst,
+	setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
 		     (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
-		     ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
-		     ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
-		     ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
-		     ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
-		     ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
+		      ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
 
 	/* Disable NOC timeout */
-	writel(0, &sysmgr_regs->noc_timeout);
+	writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT);
 
 	return 0;
 }
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 9a32f5abfe..1008a78dc8 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -10,32 +10,27 @@
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/system_manager.h>
 
-static const struct socfpga_reset_manager *reset_manager_base =
-		(void *)SOCFPGA_RSTMGR_ADDRESS;
-static const struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 /* Assert or de-assert SoCFPGA reset manager reset. */
 void socfpga_per_reset(u32 reset, int set)
 {
-	const u32 *reg;
+	unsigned long reg;
 	u32 rstmgr_bank = RSTMGR_BANK(reset);
 
 	switch (rstmgr_bank) {
 	case 0:
-		reg = &reset_manager_base->mpu_mod_reset;
+		reg = RSTMGR_GEN5_MPUMODRST;
 		break;
 	case 1:
-		reg = &reset_manager_base->per_mod_reset;
+		reg = RSTMGR_GEN5_PERMODRST;
 		break;
 	case 2:
-		reg = &reset_manager_base->per2_mod_reset;
+		reg = RSTMGR_GEN5_PER2MODRST;
 		break;
 	case 3:
-		reg = &reset_manager_base->brg_mod_reset;
+		reg = RSTMGR_GEN5_BRGMODRST;
 		break;
 	case 4:
-		reg = &reset_manager_base->misc_mod_reset;
+		reg = RSTMGR_GEN5_MISCMODRST;
 		break;
 
 	default:
@@ -43,9 +38,11 @@ void socfpga_per_reset(u32 reset, int set)
 	}
 
 	if (set)
-		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+		setbits_le32(socfpga_get_rstmgr_addr() + reg,
+			     1 << RSTMGR_RESET(reset));
 	else
-		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+		clrbits_le32(socfpga_get_rstmgr_addr() + reg,
+			     1 << RSTMGR_RESET(reset));
 }
 
 /*
@@ -57,8 +54,8 @@ void socfpga_per_reset_all(void)
 {
 	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
 
-	writel(~l4wd0, &reset_manager_base->per_mod_reset);
-	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+	writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_PERMODRST);
+	writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_PER2MODRST);
 }
 
 #define L3REGS_REMAP_LWHPS2FPGA_MASK	0x10
@@ -83,8 +80,10 @@ void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)
 	if (f2h)
 		brgmask |= BIT(2);
 
-	writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]);
-	writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]);
+	writel(brgmask,
+	       socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(0));
+	writel(l3rmask,
+	       socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(1));
 }
 
 void socfpga_bridges_reset(int enable)
@@ -95,7 +94,7 @@ void socfpga_bridges_reset(int enable)
 
 	if (enable) {
 		/* brdmodrst */
-		writel(0x7, &reset_manager_base->brg_mod_reset);
+		writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 		writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
 	} else {
 		socfpga_bridges_set_handoff_regs(false, false, false);
@@ -109,7 +108,7 @@ void socfpga_bridges_reset(int enable)
 		}
 
 		/* brdmodrst */
-		writel(0, &reset_manager_base->brg_mod_reset);
+		writel(0, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 
 		/* Remap the bridges into memory map */
 		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 499a84aff5..c7430777b2 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -12,31 +12,28 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_reset_manager *reset_manager_base =
-		(void *)SOCFPGA_RSTMGR_ADDRESS;
-static const struct socfpga_system_manager *system_manager_base =
-		(void *)SOCFPGA_SYSMGR_ADDRESS;
-
 /* Assert or de-assert SoCFPGA reset manager reset. */
 void socfpga_per_reset(u32 reset, int set)
 {
-	const void *reg;
+	unsigned long reg;
 
 	if (RSTMGR_BANK(reset) == 0)
-		reg = &reset_manager_base->mpumodrst;
+		reg = RSTMGR_SOC64_MPUMODRST;
 	else if (RSTMGR_BANK(reset) == 1)
-		reg = &reset_manager_base->per0modrst;
+		reg = RSTMGR_SOC64_PER0MODRST;
 	else if (RSTMGR_BANK(reset) == 2)
-		reg = &reset_manager_base->per1modrst;
+		reg = RSTMGR_SOC64_PER1MODRST;
 	else if (RSTMGR_BANK(reset) == 3)
-		reg = &reset_manager_base->brgmodrst;
+		reg = RSTMGR_SOC64_BRGMODRST;
 	else	/* Invalid reset register, do nothing */
 		return;
 
 	if (set)
-		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+		setbits_le32(socfpga_get_rstmgr_addr() + reg,
+			     1 << RSTMGR_RESET(reset));
 	else
-		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+		clrbits_le32(socfpga_get_rstmgr_addr() + reg,
+			     1 << RSTMGR_RESET(reset));
 }
 
 /*
@@ -50,47 +47,52 @@ void socfpga_per_reset_all(void)
 
 	/* disable all except OCP and l4wd0. OCP disable later */
 	writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
-	       &reset_manager_base->per0modrst);
-	writel(~l4wd0, &reset_manager_base->per0modrst);
-	writel(0xffffffff, &reset_manager_base->per1modrst);
+		      socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
+	writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
+	writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
 }
 
 void socfpga_bridges_reset(int enable)
 {
 	if (enable) {
 		/* clear idle request to all bridges */
-		setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
+		setbits_le32(socfpga_get_sysmgr_addr() +
+			     SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
 
 		/* Release all bridges from reset state */
-		clrbits_le32(&reset_manager_base->brgmodrst, ~0);
+		clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
+			     ~0);
 
 		/* Poll until all idleack to 0 */
-		while (readl(&system_manager_base->noc_idleack))
+		while (readl(socfpga_get_sysmgr_addr() +
+			     SYSMGR_SOC64_NOC_IDLEACK))
 			;
 	} else {
 		/* set idle request to all bridges */
-		writel(~0, &system_manager_base->noc_idlereq_set);
+		writel(~0,
+		       socfpga_get_sysmgr_addr() +
+		       SYSMGR_SOC64_NOC_IDLEREQ_SET);
 
 		/* Enable the NOC timeout */
-		writel(1, &system_manager_base->noc_timeout);
+		writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
 
 		/* Poll until all idleack to 1 */
-		while ((readl(&system_manager_base->noc_idleack) ^
+		while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLEACK) ^
 			(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
 			;
 
 		/* Poll until all idlestatus to 1 */
-		while ((readl(&system_manager_base->noc_idlestatus) ^
+		while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLESTATUS) ^
 			(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
 			;
 
 		/* Reset all bridges (except NOR DDR scheduler & F2S) */
-		setbits_le32(&reset_manager_base->brgmodrst,
+		setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
 			     ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
-			     RSTMGR_BRGMODRST_FPGA2SOC_MASK));
+			       RSTMGR_BRGMODRST_FPGA2SOC_MASK));
 
 		/* Disable NOC timeout */
-		writel(0, &system_manager_base->noc_timeout);
+		writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
 	}
 }
 
@@ -99,6 +101,6 @@ void socfpga_bridges_reset(int enable)
  */
 int cpu_has_been_warmreset(void)
 {
-	return readl(&reset_manager_base->status) &
-		RSTMGR_L4WD_MPU_WARMRESET_MASK;
+	return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
+			RSTMGR_L4WD_MPU_WARMRESET_MASK;
 }
diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c
index 52175af48b..f7ee28915e 100644
--- a/arch/arm/mach-socfpga/scan_manager.c
+++ b/arch/arm/mach-socfpga/scan_manager.c
@@ -31,8 +31,6 @@ static const struct socfpga_scan_manager *scan_manager_base =
 		(void *)(SOCFPGA_SCANMGR_ADDRESS);
 static const struct socfpga_freeze_controller *freeze_controller_base =
 		(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
-static struct socfpga_system_manager *sys_mgr_base =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 /**
  * scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle
@@ -218,7 +216,7 @@ u32 scan_mgr_get_fpga_id(void)
 	int ret;
 
 	/* Enable HPS to talk to JTAG in the FPGA through the System Manager */
-	writel(0x1, &sys_mgr_base->scanmgrgrp_ctrl);
+	writel(0x1, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SCANMGRGRP_CTRL);
 
 	/* Enable port 7 */
 	writel(0x80, &scan_manager_base->en);
@@ -253,7 +251,7 @@ u32 scan_mgr_get_fpga_id(void)
 
 	/* Disable all port */
 	writel(0, &scan_manager_base->en);
-	writel(0, &sys_mgr_base->scanmgrgrp_ctrl);
+	writel(0, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SCANMGRGRP_CTRL);
 
 	return id;
 }
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index d36732447b..7c38c50981 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -32,12 +32,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 u32 spl_boot_device(void)
 {
-	const u32 bsel = readl(&sysmgr_regs->bootinfo);
+	const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
 
 	switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
 	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
@@ -107,6 +104,11 @@ void spl_board_init(void)
 
 void board_init_f(ulong dummy)
 {
+	if (spl_early_init())
+		hang();
+
+	socfpga_get_managers_addr();
+
 	dcache_disable();
 
 	socfpga_init_security_policies();
@@ -117,8 +119,6 @@ void board_init_f(ulong dummy)
 	socfpga_per_reset_all();
 	socfpga_watchdog_disable();
 
-	spl_early_init();
-
 	/* Configure the clock based on handoff */
 	cm_basic_init(gd->fdt_blob);
 
diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c
new file mode 100644
index 0000000000..c745d64114
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <common.h>
+#include <image.h>
+#include <spl.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <watchdog.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_MMC1;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
+	return MMCSD_MODE_FS;
+#else
+	return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = spl_early_init();
+	if (ret)
+		hang();
+
+	socfpga_get_managers_addr();
+
+#ifdef CONFIG_HW_WATCHDOG
+	/* Ensure watchdog is paused when debugging is happening */
+	writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+
+	/* Enable watchdog before initializing the HW */
+	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
+	hw_watchdog_init();
+#endif
+
+	/* ensure all processors are not released prior Linux boot */
+	writeq(0, CPU_RELEASE_ADDR);
+
+	timer_init();
+
+	sysmgr_pinmux_init();
+
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+	if (ret) {
+		debug("Clock init failed: %d\n", ret);
+		hang();
+	}
+
+	preloader_console_init();
+	cm_print_clock_quick_summary();
+
+	firewall_setup();
+	ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
+	if (ret) {
+		debug("CCU init failed: %d\n", ret);
+		hang();
+	}
+
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		hang();
+	}
+#endif
+
+	mbox_init();
+
+#ifdef CONFIG_CADENCE_QSPI
+	mbox_qspi_open();
+#endif
+}
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 408e409375..e19f55aa9b 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -24,12 +24,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 u32 spl_boot_device(void)
 {
-	const u32 bsel = readl(&sysmgr_regs->bootinfo);
+	const u32 bsel = readl(socfpga_get_sysmgr_addr() +
+			       SYSMGR_GEN5_BOOTINFO);
 
 	switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
 	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
@@ -67,17 +65,23 @@ void board_init_f(ulong dummy)
 	int ret;
 	struct udevice *dev;
 
+	ret = spl_early_init();
+	if (ret)
+		hang();
+
+	socfpga_get_managers_addr();
+
 	/*
-	 * First C code to run. Clear fake OCRAM ECC first as SBE
+	 * Clear fake OCRAM ECC first as SBE
 	 * and DBE might triggered during power on
 	 */
-	reg = readl(&sysmgr_regs->eccgrp_ocram);
+	reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
 	if (reg & SYSMGR_ECC_OCRAM_SERR)
 		writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
-		       &sysmgr_regs->eccgrp_ocram);
+		       socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
 	if (reg & SYSMGR_ECC_OCRAM_DERR)
 		writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
-		       &sysmgr_regs->eccgrp_ocram);
+		       socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
 
 	socfpga_sdram_remap_zero();
 	socfpga_pl310_clear();
@@ -128,12 +132,6 @@ void board_init_f(ulong dummy)
 	debug_uart_init();
 #endif
 
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
 	ret = uclass_get_device(UCLASS_RESET, 0, &dev);
 	if (ret)
 		debug("Reset init failed: %d\n", ret);
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index ec65e1ce64..8d96918cb4 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -12,8 +12,9 @@
 #include <image.h>
 #include <spl.h>
 #include <asm/arch/clock_manager.h>
-#include <asm/arch/firewall_s10.h>
+#include <asm/arch/firewall.h>
 #include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/system_manager.h>
 #include <watchdog.h>
@@ -21,9 +22,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 u32 spl_boot_device(void)
 {
 	/* TODO: Get from SDM or handoff */
@@ -41,88 +39,21 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
-void spl_disable_firewall_l4_per(void)
-{
-	const struct socfpga_firwall_l4_per *firwall_l4_per_base =
-		(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
-	u32 i;
-	const u32 *addr[] = {
-			&firwall_l4_per_base->nand,
-			&firwall_l4_per_base->nand_data,
-			&firwall_l4_per_base->usb0,
-			&firwall_l4_per_base->usb1,
-			&firwall_l4_per_base->spim0,
-			&firwall_l4_per_base->spim1,
-			&firwall_l4_per_base->emac0,
-			&firwall_l4_per_base->emac1,
-			&firwall_l4_per_base->emac2,
-			&firwall_l4_per_base->sdmmc,
-			&firwall_l4_per_base->gpio0,
-			&firwall_l4_per_base->gpio1,
-			&firwall_l4_per_base->i2c0,
-			&firwall_l4_per_base->i2c1,
-			&firwall_l4_per_base->i2c2,
-			&firwall_l4_per_base->i2c3,
-			&firwall_l4_per_base->i2c4,
-			&firwall_l4_per_base->timer0,
-			&firwall_l4_per_base->timer1,
-			&firwall_l4_per_base->uart0,
-			&firwall_l4_per_base->uart1
-			};
-
-	/*
-	 * The following lines of code will enable non-secure access
-	 * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This
-	 * is needed as most OS run in non-secure mode. Thus we need to
-	 * enable non-secure access to these peripherals in order for the
-	 * OS to use these peripherals.
-	 */
-	for (i = 0; i < ARRAY_SIZE(addr); i++)
-		writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
-}
-
-void spl_disable_firewall_l4_sys(void)
-{
-	const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
-		(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
-	u32 i;
-	const u32 *addr[] = {
-			&firwall_l4_sys_base->dma_ecc,
-			&firwall_l4_sys_base->emac0rx_ecc,
-			&firwall_l4_sys_base->emac0tx_ecc,
-			&firwall_l4_sys_base->emac1rx_ecc,
-			&firwall_l4_sys_base->emac1tx_ecc,
-			&firwall_l4_sys_base->emac2rx_ecc,
-			&firwall_l4_sys_base->emac2tx_ecc,
-			&firwall_l4_sys_base->nand_ecc,
-			&firwall_l4_sys_base->nand_read_ecc,
-			&firwall_l4_sys_base->nand_write_ecc,
-			&firwall_l4_sys_base->ocram_ecc,
-			&firwall_l4_sys_base->sdmmc_ecc,
-			&firwall_l4_sys_base->usb0_ecc,
-			&firwall_l4_sys_base->usb1_ecc,
-			&firwall_l4_sys_base->clock_manager,
-			&firwall_l4_sys_base->io_manager,
-			&firwall_l4_sys_base->reset_manager,
-			&firwall_l4_sys_base->system_manager,
-			&firwall_l4_sys_base->watchdog0,
-			&firwall_l4_sys_base->watchdog1,
-			&firwall_l4_sys_base->watchdog2,
-			&firwall_l4_sys_base->watchdog3
-		};
-
-	for (i = 0; i < ARRAY_SIZE(addr); i++)
-		writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
-}
-
 void board_init_f(ulong dummy)
 {
 	const struct cm_config *cm_default_cfg = cm_get_default_config();
 	int ret;
 
+	ret = spl_early_init();
+	if (ret)
+		hang();
+
+	socfpga_get_managers_addr();
+
 #ifdef CONFIG_HW_WATCHDOG
 	/* Ensure watchdog is paused when debugging is happening */
-	writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
+	writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
 
 	/* Enable watchdog before initializing the HW */
 	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
@@ -145,29 +76,11 @@ void board_init_f(ulong dummy)
 	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 	debug_uart_init();
 #endif
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
 
 	preloader_console_init();
 	cm_print_clock_quick_summary();
 
-	/* enable non-secure interface to DMA330 DMA and peripherals */
-	writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
-	writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
-
-	spl_disable_firewall_l4_per();
-
-	spl_disable_firewall_l4_sys();
-
-	/* disable lwsocf2fpga and soc2fpga bridge security */
-	writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
-	writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
-
-	/* disable SMMU security */
-	writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
+	firewall_setup();
 
 	/* disable ocram security at CCU for non secure access */
 	clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c b/arch/arm/mach-socfpga/system_manager_gen5.c
index 9d04aea2a8..09caebb3c8 100644
--- a/arch/arm/mach-socfpga/system_manager_gen5.c
+++ b/arch/arm/mach-socfpga/system_manager_gen5.c
@@ -8,9 +8,6 @@
 #include <asm/arch/system_manager.h>
 #include <asm/arch/fpga_manager.h>
 
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 /*
  * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
  * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
@@ -21,30 +18,41 @@ static void populate_sysmgr_fpgaintf_module(void)
 	u32 handoff_val = 0;
 
 	/* ISWGRP_HANDOFF_FPGAINTF */
-	writel(0, &sysmgr_regs->iswgrp_handoff[2]);
+	writel(0, socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
 
 	/* Enable the signal for those HPS peripherals that use FPGA. */
-	if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_NAND_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_NAND;
-	if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_RGMII1_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_EMAC1;
-	if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SDMMC_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_SDMMC;
-	if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_RGMII0_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_EMAC0;
-	if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SPIM0_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_SPIM0;
-	if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SPIM1_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_SPIM1;
 
 	/* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
 	based on pinmux setting */
-	setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
+	setbits_le32(socfpga_get_sysmgr_addr() +
+		     SYSMGR_ISWGRP_HANDOFF_OFFSET(2),
+		     handoff_val);
 
-	handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
+	handoff_val = readl(socfpga_get_sysmgr_addr() +
+			    SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
 	if (fpgamgr_test_fpga_ready()) {
 		/* Enable the required signals only */
-		writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
+		writel(handoff_val,
+		       socfpga_get_sysmgr_addr() +
+		       SYSMGR_GEN5_FPGAINFGRP_MODULE);
 	}
 }
 
@@ -53,7 +61,7 @@ static void populate_sysmgr_fpgaintf_module(void)
  */
 void sysmgr_pinmux_init(void)
 {
-	u32 regs = (u32)&sysmgr_regs->emacio[0];
+	u32 regs = (u32)socfpga_get_sysmgr_addr() + SYSMGR_GEN5_EMACIO;
 	const u8 *sys_mgr_init_table;
 	unsigned int len;
 	int i;
@@ -74,9 +82,11 @@ void sysmgr_pinmux_init(void)
 void sysmgr_config_warmrstcfgio(int enable)
 {
 	if (enable)
-		setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
+		setbits_le32(socfpga_get_sysmgr_addr() +
+			     SYSMGR_GEN5_ROMCODEGRP_CTRL,
 			     SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
 	else
-		clrbits_le32(&sysmgr_regs->romcodegrp_ctrl,
+		clrbits_le32(socfpga_get_sysmgr_addr() +
+			     SYSMGR_GEN5_ROMCODEGRP_CTRL,
 			     SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
 }
diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c
index 122828c9ce..cdda881efd 100644
--- a/arch/arm/mach-socfpga/system_manager_s10.c
+++ b/arch/arm/mach-socfpga/system_manager_s10.c
@@ -10,9 +10,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 /*
  * Configure all the pin muxes
  */
@@ -32,24 +29,33 @@ void populate_sysmgr_fpgaintf_module(void)
 	u32 handoff_val = 0;
 
 	/* Enable the signal for those HPS peripherals that use FPGA. */
-	if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NAND_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_NAND;
-	if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_SDMMC;
-	if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM0_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_SPIM0;
-	if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM1_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_SPIM1;
-	writel(handoff_val, &sysmgr_regs->fpgaintf_en_2);
+	writel(handoff_val,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN2);
 
 	handoff_val = 0;
-	if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_EMAC0;
-	if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_EMAC1;
-	if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_EMAC2;
-	writel(handoff_val, &sysmgr_regs->fpgaintf_en_3);
+	writel(handoff_val,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN3);
 }
 
 /*
@@ -64,14 +70,16 @@ void populate_sysmgr_pinmux(void)
 	sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
 	for (i = 0; i < len; i = i + 2) {
 		writel(sys_mgr_table_u32[i + 1],
-		       sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]);
+		       sys_mgr_table_u32[i] +
+		       (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_PINSEL0);
 	}
 
 	/* setup the pin ctrl */
 	sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
 	for (i = 0; i < len; i = i + 2) {
 		writel(sys_mgr_table_u32[i + 1],
-		       sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]);
+		       sys_mgr_table_u32[i] +
+		       (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IOCTRL0);
 	}
 
 	/* setup the fpga use */
@@ -79,13 +87,15 @@ void populate_sysmgr_pinmux(void)
 	for (i = 0; i < len; i = i + 2) {
 		writel(sys_mgr_table_u32[i + 1],
 		       sys_mgr_table_u32[i] +
-		       (u8 *)&sysmgr_regs->rgmii0usefpga);
+		       (u8 *)socfpga_get_sysmgr_addr() +
+		       SYSMGR_SOC64_EMAC0_USEFPGA);
 	}
 
 	/* setup the IO delay */
 	sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
 	for (i = 0; i < len; i = i + 2) {
 		writel(sys_mgr_table_u32[i + 1],
-		       sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]);
+		       sys_mgr_table_u32[i] +
+		       (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IODELAY0);
 	}
 }
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index 7cafc7dcfc..3da85791a1 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -10,9 +10,6 @@
 #include <asm/arch/handoff_s10.h>
 #include <asm/arch/system_manager.h>
 
-static const struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 const struct cm_config * const cm_get_default_config(void)
 {
 	struct cm_config *cm_handoff_cfg = (struct cm_config *)
@@ -36,11 +33,14 @@ const struct cm_config * const cm_get_default_config(void)
 const unsigned int cm_get_osc_clk_hz(void)
 {
 #ifdef CONFIG_SPL_BUILD
-	u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
 
-	writel(clock, &sysmgr_regs->boot_scratch_cold1);
+	u32 clock = readl(HANDOFF_CLOCK_OSC);
+
+	writel(clock,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
 #endif
-	return readl(&sysmgr_regs->boot_scratch_cold1);
+	return readl(socfpga_get_sysmgr_addr() +
+		     SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
 }
 
 const unsigned int cm_get_intosc_clk_hz(void)
@@ -51,9 +51,11 @@ const unsigned int cm_get_intosc_clk_hz(void)
 const unsigned int cm_get_fpga_clk_hz(void)
 {
 #ifdef CONFIG_SPL_BUILD
-	u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
+	u32 clock = readl(HANDOFF_CLOCK_FPGA);
 
-	writel(clock, &sysmgr_regs->boot_scratch_cold2);
+	writel(clock,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
 #endif
-	return readl(&sysmgr_regs->boot_scratch_cold2);
+	return readl(socfpga_get_sysmgr_addr() +
+		     SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
 }
diff --git a/board/intel/agilex-socdk/MAINTAINERS b/board/intel/agilex-socdk/MAINTAINERS
new file mode 100644
index 0000000000..b8e28f0b24
--- /dev/null
+++ b/board/intel/agilex-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M:	Ley Foon Tan <ley.foon.tan@intel.com>
+M:	Chee Hong Ang <chee.hong.ang@intel.com>
+S:	Maintained
+F:	board/intel/agilex-socdk/
+F:	include/configs/socfpga_agilex_socdk.h
+F:	configs/socfpga_agilex_defconfig
diff --git a/board/intel/agilex-socdk/Makefile b/board/intel/agilex-socdk/Makefile
new file mode 100644
index 0000000000..b86223a571
--- /dev/null
+++ b/board/intel/agilex-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2019 Intel Corporation <www.intel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0
+#
+
+obj-y	:= socfpga.o
diff --git a/board/intel/agilex-socdk/socfpga.c b/board/intel/agilex-socdk/socfpga.c
new file mode 100644
index 0000000000..72a3e0836d
--- /dev/null
+++ b/board/intel/agilex-socdk/socfpga.c
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index c527617e43..61488daa3c 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -731,6 +731,12 @@ config SPL_UBI
 	  README.ubispl for more info.
 
 if SPL_DM
+config SPL_CACHE
+	depends on CACHE
+	bool "Support cache drivers in SPL"
+	help
+	  Enable support for cache drivers in SPL.
+
 config SPL_DM_SPI
 	bool "Support SPI DM drivers in SPL"
 	help
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
new file mode 100644
index 0000000000..cdb93960d0
--- /dev/null
+++ b/configs/socfpga_agilex_defconfig
@@ -0,0 +1,60 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_agilex"
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_BOOTDELAY=5
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
diff --git a/drivers/Makefile b/drivers/Makefile
index b51bdeedbe..44a08da602 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/
 obj-$(CONFIG_$(SPL_TPL_)DM) += core/
 obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 629039e7a8..1e452ad6d9 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -31,4 +31,12 @@ config V5L2_CACHE
 	  It will configure tag and data ram timing control from the
 	  device tree and enable L2 cache.
 
+config NCORE_CACHE
+	bool "Arteris Ncore cache coherent unit driver"
+	select CACHE
+	help
+	  This driver is for the Arteris Ncore cache coherent unit (CCU)
+	  controller. The driver initializes cache directories and coherent
+	  agent interfaces.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 4a6458c602..fed50be3f9 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,5 +1,6 @@
 
-obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/drivers/cache/cache-ncore.c b/drivers/cache/cache-ncore.c
new file mode 100644
index 0000000000..e3aca36071
--- /dev/null
+++ b/drivers/cache/cache-ncore.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+#include <dm.h>
+#include <wait_bit.h>
+
+#include <asm/io.h>
+
+/* Directory */
+#define DIRUSFER		0x80010
+#define DIRUCASER0		0x80040
+#define DIRUSFMCR		0x80080
+#define DIRUSFMAR		0x80084
+
+#define DIRUSFMCR_SFID_SHIFT	16
+
+/* Coherent cache agent interface */
+#define CAIUIDR			0x00ffc
+
+#define CAIUIDR_CA_GET(v)	(((v) & 0x00008000) >> 15)
+#define CAIUIDR_TYPE_GET(v)	(((v) & 0x000f0000) >> 16)
+#define CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT	0
+#define CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT	1
+
+/* Coherent subsystem */
+#define CSADSER0		0xff040
+#define CSUIDR			0xffff8
+#define CSIDR			0xffffc
+
+#define CSUIDR_NUMCAIUS_GET(v)	(((v) & 0x0000007f) >> 0)
+#define CSUIDR_NUMDIRUS_GET(v)	(((v) & 0x003f0000) >> 16)
+#define CSUIDR_NUMCMIUS_GET(v)	(((v) & 0x3f000000) >> 24)
+
+#define CSIDR_NUMSFS_GET(v)	(((v) & 0x007c0000) >> 18)
+
+#define DIR_REG_SZ		0x1000
+#define CAIU_REG_SZ		0x1000
+
+#define CCU_DIR_REG_ADDR(base, reg, dir)	\
+		((base) + (reg) + ((dir) * DIR_REG_SZ))
+
+/* OCRAM firewall register */
+#define OCRAM_FW_01			0x100204
+#define OCRAM_SECURE_REGIONS		4
+
+#define OCRAM_PRIVILEGED_MASK		BIT(29)
+#define OCRAM_SECURE_MASK		BIT(30)
+
+static void ncore_ccu_init_dirs(void __iomem *base)
+{
+	ulong i, f;
+	int ret;
+	u32 num_of_dirs;
+	u32 num_of_snoop_filters;
+	u32 reg;
+
+	num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
+	num_of_snoop_filters =
+		CSIDR_NUMSFS_GET(readl(base + CSIDR)) + 1;
+
+	/* Initialize each snoop filter in each directory */
+	for (f = 0; f < num_of_snoop_filters; f++) {
+		reg = f << DIRUSFMCR_SFID_SHIFT;
+		for (i = 0; i < num_of_dirs; i++) {
+			/* Initialize all entries */
+			writel(reg, CCU_DIR_REG_ADDR(base, DIRUSFMCR, i));
+
+			/* Poll snoop filter maintenance operation active
+			 * bit become 0.
+			 */
+			ret = wait_for_bit_le32((const void *)
+						CCU_DIR_REG_ADDR(base,
+								 DIRUSFMAR, i),
+						BIT(0), false, 1000, false);
+			if (ret) {
+				puts("CCU: Directory initialization failed!\n");
+				hang();
+			}
+
+			/* Enable snoop filter, a bit per snoop filter */
+			setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
+				     BIT(f));
+		}
+	}
+}
+
+static void ncore_ccu_init_coh_agent(void __iomem *base)
+{
+	u32 num_of_coh_agent_intf;
+	u32 num_of_dirs;
+	u32 reg;
+	u32 type;
+	u32 i, dir;
+
+	num_of_coh_agent_intf =
+		CSUIDR_NUMCAIUS_GET(readl(base + CSUIDR));
+	num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
+
+	for (i = 0; i < num_of_coh_agent_intf; i++) {
+		reg = readl(base + CAIUIDR + (i * CAIU_REG_SZ));
+		if (CAIUIDR_CA_GET(reg)) {
+			/* Caching agent bit is enabled, enable caching agent
+			 * snoop in each directory
+			 */
+			for (dir = 0; dir < num_of_dirs; dir++) {
+				setbits_le32((ulong)
+					     CCU_DIR_REG_ADDR(base, DIRUCASER0,
+							      dir),
+					     BIT(i));
+			}
+		}
+
+		type = CAIUIDR_TYPE_GET(reg);
+		if (type == CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT ||
+		    type == CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT) {
+			/* DVM support is enabled, enable ACE DVM snoop*/
+			setbits_le32((ulong)(base + CSADSER0),
+				     BIT(i));
+		}
+	}
+}
+
+static void ocram_bypass_firewall(void __iomem *base)
+{
+	int i;
+
+	for (i = 0; i < OCRAM_SECURE_REGIONS; i++) {
+		clrbits_le32(base + OCRAM_FW_01 + (i * sizeof(u32)),
+			     OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
+	}
+}
+
+static int ncore_ccu_probe(struct udevice *dev)
+{
+	void __iomem *base;
+	fdt_addr_t addr;
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	base = (void __iomem *)addr;
+
+	ncore_ccu_init_dirs(base);
+	ncore_ccu_init_coh_agent(base);
+	ocram_bypass_firewall(base);
+
+	return 0;
+}
+
+static const struct udevice_id ncore_ccu_ids[] = {
+	{ .compatible = "arteris,ncore-ccu" },
+	{}
+};
+
+U_BOOT_DRIVER(ncore_ccu) = {
+	.name   = "ncore_ccu",
+	.id     = UCLASS_CACHE,
+	.of_match = ncore_ccu_ids,
+	.probe	= ncore_ccu_probe,
+	.flags  = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index a3ae8b24b0..96215ad5c4 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -3,4 +3,5 @@
 # Copyright (C) 2018 Marek Vasut <marex@denx.de>
 #
 
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
new file mode 100644
index 0000000000..5fedec549d
--- /dev/null
+++ b/drivers/clk/altera/clk-agilex.c
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/util.h>
+#include <dt-bindings/clock/agilex-clock.h>
+
+#include <asm/arch/clock_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_platdata {
+	void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val)
+{
+	CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+	cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
+{
+	CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+	cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
+{
+	CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+	cm_wait_for_fsm();
+}
+
+#define MEMBUS_MAINPLL				0
+#define MEMBUS_PERPLL				1
+#define MEMBUS_TIMEOUT				1000
+#define MEMBUS_ADDR_CLKSLICE			0x27
+#define MEMBUS_CLKSLICE_SYNC_MODE_EN		0x80
+
+static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
+			       int timeout)
+{
+	int cnt = 0;
+	u32 req_status;
+
+	if (pll == MEMBUS_MAINPLL)
+		req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
+	else
+		req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
+
+	while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) {
+		if (pll == MEMBUS_MAINPLL)
+			req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
+		else
+			req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
+		cnt++;
+	}
+
+	if (cnt >= timeout)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
+			    u32 addr_offset, u32 wdat, int timeout)
+{
+	u32 addr;
+	u32 val;
+
+	addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
+
+	val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK |
+	       (wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr);
+
+	if (pll == MEMBUS_MAINPLL)
+		CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
+	else
+		CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
+
+	debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr);
+
+	return membus_wait_for_req(plat, pll, timeout);
+}
+
+static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
+			   u32 addr_offset, u32 *rdata, int timeout)
+{
+	u32 addr;
+	u32 val;
+
+	addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
+
+	val = ((CLKMGR_MEM_REQ_SET_MSK & ~CLKMGR_MEM_WR_SET_MSK) | addr);
+
+	if (pll == MEMBUS_MAINPLL)
+		CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
+	else
+		CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
+
+	*rdata = 0;
+
+	if (membus_wait_for_req(plat, pll, timeout))
+		return -ETIMEDOUT;
+
+	if (pll == MEMBUS_MAINPLL)
+		*rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT);
+	else
+		*rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT);
+
+	debug("MEMBUS: Read 0x%08x from addr = 0x%08x\n", *rdata, addr);
+
+	return 0;
+}
+
+static u32 calc_vocalib_pll(u32 pllm, u32 pllglob)
+{
+	u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib;
+
+	mdiv = pllm & CLKMGR_PLLM_MDIV_MASK;
+	arefclkdiv = (pllglob & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
+		      CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
+	drefclkdiv = (pllglob & CLKMGR_PLLGLOB_DREFCLKDIV_MASK) >>
+		      CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET;
+	refclkdiv = (pllglob & CLKMGR_PLLGLOB_REFCLKDIV_MASK) >>
+		     CLKMGR_PLLGLOB_REFCLKDIV_OFFSET;
+	mscnt = CLKMGR_VCOCALIB_MSCNT_CONST / (mdiv * BIT(drefclkdiv));
+	if (!mscnt)
+		mscnt = 1;
+	hscnt = (mdiv * mscnt * BIT(drefclkdiv) / refclkdiv) -
+		CLKMGR_VCOCALIB_HSCNT_CONST;
+	vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+		   ((mscnt << CLKMGR_VCOCALIB_MSCNT_OFFSET) &
+		     CLKMGR_VCOCALIB_MSCNT_MASK);
+
+	/* Dump all the pll calibration settings for debug purposes */
+	debug("mdiv          : %d\n", mdiv);
+	debug("arefclkdiv    : %d\n", arefclkdiv);
+	debug("drefclkdiv    : %d\n", drefclkdiv);
+	debug("refclkdiv     : %d\n", refclkdiv);
+	debug("mscnt         : %d\n", mscnt);
+	debug("hscnt         : %d\n", hscnt);
+	debug("vcocalib      : 0x%08x\n", vcocalib);
+
+	return vcocalib;
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_basic_init(struct udevice *dev,
+			   const struct cm_config * const cfg)
+{
+	struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
+	u32 vcocalib;
+	u32 rdata;
+
+	if (!cfg)
+		return;
+
+	/* Put both PLLs in bypass */
+	clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+	clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+	/* Put both PLLs in Reset and Power Down */
+	CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
+		       CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+	CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLGLOB,
+		       CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+
+	/* setup main PLL dividers where calculate the vcocalib value */
+	vcocalib = calc_vocalib_pll(cfg->main_pll_pllm, cfg->main_pll_pllglob);
+	CM_REG_WRITEL(plat, cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
+		      CLKMGR_MAINPLL_PLLGLOB);
+	CM_REG_WRITEL(plat, cfg->main_pll_fdbck, CLKMGR_MAINPLL_FDBCK);
+	CM_REG_WRITEL(plat, vcocalib, CLKMGR_MAINPLL_VCOCALIB);
+	CM_REG_WRITEL(plat, cfg->main_pll_pllc0, CLKMGR_MAINPLL_PLLC0);
+	CM_REG_WRITEL(plat, cfg->main_pll_pllc1, CLKMGR_MAINPLL_PLLC1);
+	CM_REG_WRITEL(plat, cfg->main_pll_pllc2, CLKMGR_MAINPLL_PLLC2);
+	CM_REG_WRITEL(plat, cfg->main_pll_pllc3, CLKMGR_MAINPLL_PLLC3);
+	CM_REG_WRITEL(plat, cfg->main_pll_pllm, CLKMGR_MAINPLL_PLLM);
+	CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
+	CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
+	CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
+
+	/* setup peripheral PLL dividers where calculate the vcocalib value */
+	vcocalib = calc_vocalib_pll(cfg->per_pll_pllm, cfg->per_pll_pllglob);
+	CM_REG_WRITEL(plat, cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
+		      CLKMGR_PERPLL_PLLGLOB);
+	CM_REG_WRITEL(plat, cfg->per_pll_fdbck, CLKMGR_PERPLL_FDBCK);
+	CM_REG_WRITEL(plat, vcocalib, CLKMGR_PERPLL_VCOCALIB);
+	CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0);
+	CM_REG_WRITEL(plat, cfg->per_pll_pllc1, CLKMGR_PERPLL_PLLC1);
+	CM_REG_WRITEL(plat, cfg->per_pll_pllc2, CLKMGR_PERPLL_PLLC2);
+	CM_REG_WRITEL(plat, cfg->per_pll_pllc3, CLKMGR_PERPLL_PLLC3);
+	CM_REG_WRITEL(plat, cfg->per_pll_pllm, CLKMGR_PERPLL_PLLM);
+	CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
+	CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
+
+	/* Take both PLL out of reset and power up */
+	CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
+		       CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+	CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,
+		       CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+
+	/* Membus programming to set mainpll and perripll to
+	 * source synchronous mode
+	 */
+	membus_read_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE, &rdata,
+			MEMBUS_TIMEOUT);
+	membus_write_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE,
+			 (rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),
+			 MEMBUS_TIMEOUT);
+	membus_read_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE, &rdata,
+			MEMBUS_TIMEOUT);
+	membus_write_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE,
+			 (rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),
+			 MEMBUS_TIMEOUT);
+
+	cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+	/* Configure ping pong counters in altera group */
+	CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
+	CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
+	CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
+	CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
+	CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
+	CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR);
+	CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR);
+	CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR);
+
+	CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
+	CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
+
+	CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) |
+			CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+			CLKMGR_MAINPLL_PLLGLOB);
+	CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) |
+			CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+			CLKMGR_PERPLL_PLLGLOB);
+
+	/* Take all PLLs out of bypass */
+	clk_write_bypass_mainpll(plat, 0);
+	clk_write_bypass_perpll(plat, 0);
+
+	/* Clear the loss of lock bits (write 1 to clear) */
+	CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
+		       CLKMGR_INTER_PERPLLLOST_MASK |
+		       CLKMGR_INTER_MAINPLLLOST_MASK);
+
+	/* Take all ping pong counters out of reset */
+	CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,
+		       CLKMGR_ALT_EXTCNTRST_ALLCNTRST);
+
+	/* Out of boot mode */
+	clk_write_ctrl(plat,
+		       CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
+}
+
+static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
+			      u32 pllglob_reg, u32 pllm_reg)
+{
+	 u64 fref, arefdiv, mdiv, reg, vco;
+
+	reg = CM_REG_READL(plat, pllglob_reg);
+
+	fref = (reg & CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
+		CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
+
+	switch (fref) {
+	case CLKMGR_VCO_PSRC_EOSC1:
+		fref = cm_get_osc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_INTOSC:
+		fref = cm_get_intosc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_F2S:
+		fref = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	arefdiv = (reg & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
+		   CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
+
+	mdiv = CM_REG_READL(plat, pllm_reg) & CLKMGR_PLLM_MDIV_MASK;
+
+	vco = fref / arefdiv;
+	vco = vco * mdiv;
+
+	return vco;
+}
+
+static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
+				 CLKMGR_MAINPLL_PLLM);
+}
+
+static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
+				 CLKMGR_PERPLL_PLLM);
+}
+
+static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg)
+{
+	u32 clksrc = CM_REG_READL(plat, reg);
+
+	return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
+}
+
+static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
+			     u32 main_reg, u32 per_reg)
+{
+	u64 clock;
+	u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);
+
+	switch (clklsrc) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = clk_get_main_vco_clk_hz(plat);
+		clock /= (CM_REG_READL(plat, main_reg) &
+			  CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = clk_get_per_vco_clk_hz(plat);
+		clock /= (CM_REG_READL(plat, per_reg) &
+			  CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	default:
+		return 0;
+	}
+
+	return clock;
+}
+
+static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
+				      CLKMGR_MAINPLL_PLLC0,
+				      CLKMGR_PERPLL_PLLC0);
+
+	clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
+		 CLKMGR_CLKCNT_MSK);
+
+	return clock;
+}
+
+static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
+				      CLKMGR_MAINPLL_PLLC1,
+				      CLKMGR_PERPLL_PLLC1);
+}
+
+static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	u64 clock = clk_get_l3_main_clk_hz(plat);
+
+	clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+	      CLKMGR_NOCDIV_L4MAIN_OFFSET) &
+	      CLKMGR_NOCDIV_DIVIDER_MASK);
+
+	return clock;
+}
+
+static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
+				      CLKMGR_MAINPLL_PLLC3,
+				      CLKMGR_PERPLL_PLLC3);
+
+	clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) &
+		 CLKMGR_CLKCNT_MSK);
+
+	return clock / 4;
+}
+
+static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	u64 clock = clk_get_l3_main_clk_hz(plat);
+
+	clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+		      CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
+		      CLKMGR_NOCDIV_DIVIDER_MASK);
+
+	return clock;
+}
+
+static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	u64 clock = clk_get_l3_main_clk_hz(plat);
+
+	clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+		      CLKMGR_NOCDIV_L4MPCLK_OFFSET) &
+		      CLKMGR_NOCDIV_DIVIDER_MASK);
+
+	return clock;
+}
+
+static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
+		return clk_get_l3_main_clk_hz(plat) / 2;
+
+	return clk_get_l3_main_clk_hz(plat) / 4;
+}
+
+static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id)
+{
+	bool emacsel_a;
+	u32 ctl;
+	u32 ctr_reg;
+	u32 clock;
+	u32 div;
+	u32 reg;
+
+	/* Get EMAC clock source */
+	ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
+	if (emac_id == AGILEX_EMAC0_CLK)
+		ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
+		       CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
+	else if (emac_id == AGILEX_EMAC1_CLK)
+		ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
+		       CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
+	else if (emac_id == AGILEX_EMAC2_CLK)
+		ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
+		       CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
+	else
+		return 0;
+
+	if (ctl) {
+		/* EMAC B source */
+		emacsel_a = false;
+		ctr_reg = CLKMGR_ALTR_EMACBCTR;
+	} else {
+		/* EMAC A source */
+		emacsel_a = true;
+		ctr_reg = CLKMGR_ALTR_EMACACTR;
+	}
+
+	reg = CM_REG_READL(plat, ctr_reg);
+	clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK)
+		 >> CLKMGR_ALT_EMACCTR_SRC_OFFSET;
+	div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK)
+		>> CLKMGR_ALT_EMACCTR_CNT_OFFSET;
+
+	switch (clock) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = clk_get_main_vco_clk_hz(plat);
+		if (emacsel_a) {
+			clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC2) &
+				  CLKMGR_CLKCNT_MSK);
+		} else {
+			clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) &
+				  CLKMGR_CLKCNT_MSK);
+		}
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = clk_get_per_vco_clk_hz(plat);
+		if (emacsel_a) {
+			clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) &
+				  CLKMGR_CLKCNT_MSK);
+		} else {
+			clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) &
+				  CLKMGR_CLKCNT_MSK);
+		}
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	clock /= 1 + div;
+
+	return clock;
+}
+
+static ulong socfpga_clk_get_rate(struct clk *clk)
+{
+	struct socfpga_clk_platdata *plat = dev_get_platdata(clk->dev);
+
+	switch (clk->id) {
+	case AGILEX_MPU_CLK:
+		return clk_get_mpu_clk_hz(plat);
+	case AGILEX_L4_MAIN_CLK:
+		return clk_get_l4_main_clk_hz(plat);
+	case AGILEX_L4_SYS_FREE_CLK:
+		return clk_get_l4_sys_free_clk_hz(plat);
+	case AGILEX_L4_MP_CLK:
+		return clk_get_l4_mp_clk_hz(plat);
+	case AGILEX_L4_SP_CLK:
+		return clk_get_l4_sp_clk_hz(plat);
+	case AGILEX_SDMMC_CLK:
+		return clk_get_sdmmc_clk_hz(plat);
+	case AGILEX_EMAC0_CLK:
+	case AGILEX_EMAC1_CLK:
+	case AGILEX_EMAC2_CLK:
+		return clk_get_emac_clk_hz(plat, clk->id);
+	case AGILEX_USB_CLK:
+		return clk_get_l4_mp_clk_hz(plat);
+	default:
+		return -ENXIO;
+	}
+}
+
+static int socfpga_clk_probe(struct udevice *dev)
+{
+	const struct cm_config *cm_default_cfg = cm_get_default_config();
+
+	clk_basic_init(dev, cm_default_cfg);
+
+	return 0;
+}
+
+static int socfpga_clk_ofdata_to_platdata(struct udevice *dev)
+{
+	struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
+	fdt_addr_t addr;
+
+	addr = devfdt_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	plat->regs = (void __iomem *)addr;
+
+	return 0;
+}
+
+static struct clk_ops socfpga_clk_ops = {
+	.get_rate	= socfpga_clk_get_rate,
+};
+
+static const struct udevice_id socfpga_clk_match[] = {
+	{ .compatible = "intel,agilex-clkmgr" },
+	{}
+};
+
+U_BOOT_DRIVER(socfpga_agilex_clk) = {
+	.name		= "clk-agilex",
+	.id		= UCLASS_CLK,
+	.of_match	= socfpga_clk_match,
+	.ops		= &socfpga_clk_ops,
+	.probe		= socfpga_clk_probe,
+	.ofdata_to_platdata = socfpga_clk_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct socfpga_clk_platdata),
+};
diff --git a/drivers/clk/altera/clk-agilex.h b/drivers/clk/altera/clk-agilex.h
new file mode 100644
index 0000000000..d93328ef29
--- /dev/null
+++ b/drivers/clk/altera/clk-agilex.h
@@ -0,0 +1,237 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef	_CLK_AGILEX_
+#define	_CLK_AGILEX_
+
+#define CM_REG_READL(plat, reg)				\
+	readl((plat)->regs + (reg))
+
+#define CM_REG_WRITEL(plat, data, reg)			\
+	writel(data, (plat)->regs + (reg))
+
+#define CM_REG_CLRBITS(plat, reg, clear)		\
+	clrbits_le32((plat)->regs + (reg), (clear))
+
+#define CM_REG_SETBITS(plat, reg, set)			\
+	setbits_le32((plat)->regs + (reg), (set))
+
+struct cm_config {
+	/* main group */
+	u32 main_pll_mpuclk;
+	u32 main_pll_nocclk;
+	u32 main_pll_nocdiv;
+	u32 main_pll_pllglob;
+	u32 main_pll_fdbck;
+	u32 main_pll_pllc0;
+	u32 main_pll_pllc1;
+	u32 main_pll_pllc2;
+	u32 main_pll_pllc3;
+	u32 main_pll_pllm;
+
+	/* peripheral group */
+	u32 per_pll_emacctl;
+	u32 per_pll_gpiodiv;
+	u32 per_pll_pllglob;
+	u32 per_pll_fdbck;
+	u32 per_pll_pllc0;
+	u32 per_pll_pllc1;
+	u32 per_pll_pllc2;
+	u32 per_pll_pllc3;
+	u32 per_pll_pllm;
+
+	/* altera group */
+	u32 alt_emacactr;
+	u32 alt_emacbctr;
+	u32 alt_emacptpctr;
+	u32 alt_gpiodbctr;
+	u32 alt_sdmmcctr;
+	u32 alt_s2fuser0ctr;
+	u32 alt_s2fuser1ctr;
+	u32 alt_psirefctr;
+
+	/* incoming clock */
+	u32 hps_osc_clk_hz;
+	u32 fpga_clk_hz;
+	u32 spare[3];
+};
+
+/* Clock Manager registers */
+#define CLKMGR_CTRL				0
+#define CLKMGR_STAT				4
+#define CLKMGR_TESTIOCTRL			8
+#define CLKMGR_INTRGEN				0x0c
+#define CLKMGR_INTRMSK				0x10
+#define CLKMGR_INTRCLR				0x14
+#define CLKMGR_INTRSTS				0x18
+#define CLKMGR_INTRSTK				0x1c
+#define CLKMGR_INTRRAW				0x20
+
+/* Clock Manager Main PPL group registers */
+#define CLKMGR_MAINPLL_EN			0x24
+#define CLKMGR_MAINPLL_ENS			0x28
+#define CLKMGR_MAINPLL_ENR			0x2c
+#define CLKMGR_MAINPLL_BYPASS			0x30
+#define CLKMGR_MAINPLL_BYPASSS			0x34
+#define CLKMGR_MAINPLL_BYPASSR			0x38
+#define CLKMGR_MAINPLL_MPUCLK			0x3c
+#define CLKMGR_MAINPLL_NOCCLK			0x40
+#define CLKMGR_MAINPLL_NOCDIV			0x44
+#define CLKMGR_MAINPLL_PLLGLOB			0x48
+#define CLKMGR_MAINPLL_FDBCK			0x4c
+#define CLKMGR_MAINPLL_MEM			0x50
+#define CLKMGR_MAINPLL_MEMSTAT			0x54
+#define CLKMGR_MAINPLL_PLLC0			0x58
+#define CLKMGR_MAINPLL_PLLC1			0x5c
+#define CLKMGR_MAINPLL_VCOCALIB			0x60
+#define CLKMGR_MAINPLL_PLLC2			0x64
+#define CLKMGR_MAINPLL_PLLC3			0x68
+#define CLKMGR_MAINPLL_PLLM			0x6c
+#define CLKMGR_MAINPLL_FHOP			0x70
+#define CLKMGR_MAINPLL_SSC			0x74
+#define CLKMGR_MAINPLL_LOSTLOCK			0x78
+
+/* Clock Manager Peripheral PPL group registers */
+#define CLKMGR_PERPLL_EN			0x7c
+#define CLKMGR_PERPLL_ENS			0x80
+#define CLKMGR_PERPLL_ENR			0x84
+#define CLKMGR_PERPLL_BYPASS			0x88
+#define CLKMGR_PERPLL_BYPASSS			0x8c
+#define CLKMGR_PERPLL_BYPASSR			0x90
+#define CLKMGR_PERPLL_EMACCTL			0x94
+#define CLKMGR_PERPLL_GPIODIV			0x98
+#define CLKMGR_PERPLL_PLLGLOB			0x9c
+#define CLKMGR_PERPLL_FDBCK			0xa0
+#define CLKMGR_PERPLL_MEM			0xa4
+#define CLKMGR_PERPLL_MEMSTAT			0xa8
+#define CLKMGR_PERPLL_PLLC0			0xac
+#define CLKMGR_PERPLL_PLLC1			0xb0
+#define CLKMGR_PERPLL_VCOCALIB			0xb4
+#define CLKMGR_PERPLL_PLLC2			0xb8
+#define CLKMGR_PERPLL_PLLC3			0xbc
+#define CLKMGR_PERPLL_PLLM			0xc0
+#define CLKMGR_PERPLL_FHOP			0xc4
+#define CLKMGR_PERPLL_SSC			0xc8
+#define CLKMGR_PERPLL_LOSTLOCK			0xcc
+
+/* Clock Manager Altera group registers */
+#define CLKMGR_ALTR_JTAG			0xd0
+#define CLKMGR_ALTR_EMACACTR			0xd4
+#define CLKMGR_ALTR_EMACBCTR			0xd8
+#define CLKMGR_ALTR_EMACPTPCTR			0xdc
+#define CLKMGR_ALTR_GPIODBCTR			0xe0
+#define CLKMGR_ALTR_SDMMCCTR			0xe4
+#define CLKMGR_ALTR_S2FUSER0CTR			0xe8
+#define CLKMGR_ALTR_S2FUSER1CTR			0xec
+#define CLKMGR_ALTR_PSIREFCTR			0xf0
+#define CLKMGR_ALTR_EXTCNTRST			0xf4
+
+#define CLKMGR_CTRL_BOOTMODE			BIT(0)
+
+#define CLKMGR_STAT_BUSY			BIT(0)
+#define CLKMGR_STAT_MAINPLL_LOCKED		BIT(8)
+#define CLKMGR_STAT_MAIN_TRANS			BIT(9)
+#define CLKMGR_STAT_PERPLL_LOCKED		BIT(16)
+#define CLKMGR_STAT_PERF_TRANS			BIT(17)
+#define CLKMGR_STAT_BOOTMODE			BIT(24)
+#define CLKMGR_STAT_BOOTCLKSRC			BIT(25)
+
+#define CLKMGR_STAT_ALLPLL_LOCKED_MASK		\
+	(CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED)
+
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK		0x00000001
+#define CLKMGR_INTER_PERPLLLOCKED_MASK		0x00000002
+#define CLKMGR_INTER_MAINPLLLOST_MASK		0x00000004
+#define CLKMGR_INTER_PERPLLLOST_MASK		0x00000008
+
+#define CLKMGR_CLKSRC_MASK			GENMASK(18, 16)
+#define CLKMGR_CLKSRC_OFFSET			16
+#define CLKMGR_CLKSRC_MAIN			0
+#define CLKMGR_CLKSRC_PER			1
+#define CLKMGR_CLKSRC_OSC1			2
+#define CLKMGR_CLKSRC_INTOSC			3
+#define CLKMGR_CLKSRC_FPGA			4
+#define CLKMGR_CLKCNT_MSK			GENMASK(10, 0)
+
+#define CLKMGR_BYPASS_MAINPLL_ALL		0x7
+#define CLKMGR_BYPASS_PERPLL_ALL		0x7f
+
+#define CLKMGR_NOCDIV_L4MAIN_OFFSET		0
+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET		8
+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET		16
+#define CLKMGR_NOCDIV_CSATCLK_OFFSET		24
+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET		26
+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET		28
+#define CLKMGR_NOCDIV_DIVIDER_MASK		0x3
+
+#define CLKMGR_PLLGLOB_PD_MASK				BIT(0)
+#define CLKMGR_PLLGLOB_RST_MASK				BIT(1)
+#define CLKMGR_PLLGLOB_AREFCLKDIV_MASK			GENMASK(11, 8)
+#define CLKMGR_PLLGLOB_DREFCLKDIV_MASK			GENMASK(13, 12)
+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK			GENMASK(13, 8)
+#define CLKMGR_PLLGLOB_MODCLKDIV_MASK			GENMASK(24, 27)
+#define CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET		8
+#define CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET		12
+#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET			8
+#define CLKMGR_PLLGLOB_MODCLKDIV_OFFSET			24
+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK			GENMASK(17, 16)
+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET			16
+#define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK		BIT(29)
+
+#define CLKMGR_VCO_PSRC_EOSC1			0
+#define CLKMGR_VCO_PSRC_INTOSC			1
+#define CLKMGR_VCO_PSRC_F2S			2
+
+#define CLKMGR_MEM_REQ_SET_MSK			BIT(24)
+#define CLKMGR_MEM_WR_SET_MSK			BIT(25)
+#define CLKMGR_MEM_ERR_MSK			BIT(26)
+#define CLKMGR_MEM_WDAT_LSB_OFFSET		16
+#define CLKMGR_MEM_ADDR_MASK			GENMASK(15, 0)
+#define CLKMGR_MEM_ADDR_START			0x00004000
+
+#define CLKMGR_PLLCX_EN_SET_MSK			BIT(27)
+#define CLKMGR_PLLCX_MUTE_SET_MSK		BIT(28)
+
+#define CLKMGR_VCOCALIB_MSCNT_MASK		GENMASK(23, 16)
+#define CLKMGR_VCOCALIB_MSCNT_OFFSET		16
+#define CLKMGR_VCOCALIB_HSCNT_MASK		GENMASK(9, 0)
+#define CLKMGR_VCOCALIB_MSCNT_CONST		100
+#define CLKMGR_VCOCALIB_HSCNT_CONST		4
+
+#define CLKMGR_PLLM_MDIV_MASK			GENMASK(9, 0)
+
+#define CLKMGR_LOSTLOCK_SET_MASK		BIT(0)
+
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		BIT(5)
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET	26
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK		BIT(26)
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET	27
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK		BIT(27)
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET	28
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK		BIT(28)
+
+#define CLKMGR_ALT_EMACCTR_SRC_OFFSET		16
+#define CLKMGR_ALT_EMACCTR_SRC_MASK		GENMASK(18, 16)
+#define CLKMGR_ALT_EMACCTR_CNT_OFFSET		0
+#define CLKMGR_ALT_EMACCTR_CNT_MASK		GENMASK(10, 0)
+
+#define CLKMGR_ALT_EXTCNTRST_EMACACNTRST	BIT(0)
+#define CLKMGR_ALT_EXTCNTRST_EMACBCNTRST	BIT(1)
+#define CLKMGR_ALT_EXTCNTRST_EMACPTPCNTRST	BIT(2)
+#define CLKMGR_ALT_EXTCNTRST_GPIODBCNTRST	BIT(3)
+#define CLKMGR_ALT_EXTCNTRST_SDMMCCNTRST	BIT(4)
+#define CLKMGR_ALT_EXTCNTRST_S2FUSER0CNTRST	BIT(5)
+#define CLKMGR_ALT_EXTCNTRST_S2FUSER1CNTRST	BIT(6)
+#define CLKMGR_ALT_EXTCNTRST_PSIREFCNTRST	BIT(7)
+#define CLKMGR_ALT_EXTCNTRST_ALLCNTRST		\
+	(CLKMGR_ALT_EXTCNTRST_EMACACNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_EMACBCNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_EMACPTPCNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_GPIODBCNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_SDMMCCNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_S2FUSER0CNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_S2FUSER1CNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_PSIREFCNTRST)
+#endif /* _CLK_AGILEX_ */
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 2b1c1be3b5..8f590dc5f6 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,8 +1,8 @@
 config SPL_ALTERA_SDRAM
 	bool "SoCFPGA DDR SDRAM driver in SPL"
 	depends on SPL
-	depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10
-	select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
-	select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
+	depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
+	select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
+	select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
 	help
 	  Enable DDR SDRAM controller for the SoCFPGA devices.
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 341ac0d73b..39dfee5d5a 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -9,5 +9,6 @@
 ifdef CONFIG_$(SPL_)ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
-obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o
+obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
 endif
diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c
new file mode 100644
index 0000000000..0cbcd14056
--- /dev/null
+++ b/drivers/ddr/altera/sdram_agilex.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <div64.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <reset.h>
+#include "sdram_soc64.h"
+#include <wait_bit.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int sdram_mmr_init_full(struct udevice *dev)
+{
+	struct altera_sdram_platdata *plat = dev->platdata;
+	struct altera_sdram_priv *priv = dev_get_priv(dev);
+	u32 i;
+	int ret;
+	phys_size_t hw_size;
+	bd_t bd = {0};
+
+	/* Ensure HMC clock is running */
+	if (poll_hmc_clock_status()) {
+		debug("DDR: Error as HMC clock was not running\n");
+		return -EPERM;
+	}
+
+	/* Trying 3 times to do a calibration */
+	for (i = 0; i < 3; i++) {
+		ret = wait_for_bit_le32((const void *)(plat->hmc +
+					DDRCALSTAT),
+					DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
+					false);
+		if (!ret)
+			break;
+
+		emif_reset(plat);
+	}
+
+	if (ret) {
+		puts("DDR: Error as SDRAM calibration failed\n");
+		return -EPERM;
+	}
+	debug("DDR: Calibration success\n");
+
+	/*
+	 * Configure the DDR IO size
+	 * niosreserve0: Used to indicate DDR width &
+	 *	bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
+	 *	bit[8]   = 1 if user-mode OCT is present
+	 *	bit[9]   = 1 if warm reset compiled into EMIF Cal Code
+	 *	bit[10]  = 1 if warm reset is on during generation in EMIF Cal
+	 * niosreserve1: IP ADCDS version encoded as 16 bit value
+	 *	bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+	 *			    3=EAP, 4-6 are reserved)
+	 *	bit[5:3] = Service Pack # (e.g. 1)
+	 *	bit[9:6] = Minor Release #
+	 *	bit[14:10] = Major Release #
+	 */
+	/* Configure DDR IO size x16, x32 and x64 mode */
+	u32 update_value;
+
+	update_value = hmc_readl(plat, NIOSRESERVED0);
+	update_value = (update_value & 0xFF) >> 5;
+
+	/* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */
+	update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4);
+	hmc_ecc_writel(plat, update_value, DDRIOCTRL);
+
+	/* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */
+	hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
+
+	/* assigning the SDRAM size */
+	phys_size_t size = sdram_calculate_size(plat);
+
+	if (size <= 0)
+		hw_size = PHYS_SDRAM_1_SIZE;
+	else
+		hw_size = size;
+
+	/* Get bank configuration from devicetree */
+	ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
+				     (phys_size_t *)&gd->ram_size, &bd);
+	if (ret) {
+		puts("DDR: Failed to decode memory node\n");
+		return -ENXIO;
+	}
+
+	if (gd->ram_size != hw_size) {
+		printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n",
+		       gd->ram_size >> 20);
+		printf(" mismatch with hardware (%lld MiB).\n",
+		       hw_size >> 20);
+	}
+
+	if (gd->ram_size > hw_size) {
+		printf("DDR: Error: DRAM size from device tree is greater\n");
+		printf(" than hardware size.\n");
+		hang();
+	}
+
+	printf("DDR: %lld MiB\n", gd->ram_size >> 20);
+
+	/* This enables nonsecure access to DDR */
+	/* mpuregion0addr_limit */
+	FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
+			      FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
+	FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
+
+	/* nonmpuregion0addr_limit */
+	FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
+			      FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
+
+	/* Enable mpuregion0enable and nonmpuregion0enable */
+	FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
+			      FW_MPU_DDR_SCR_EN_SET);
+
+	u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
+
+	/* Enable or disable the DDR ECC */
+	if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
+		setbits_le32(plat->hmc + ECCCTRL1,
+			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(plat->hmc + ECCCTRL1,
+			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
+		setbits_le32(plat->hmc + ECCCTRL2,
+			     (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
+			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
+		setbits_le32(plat->hmc + ERRINTEN,
+			     DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);
+
+		if (!cpu_has_been_warmreset())
+			sdram_init_ecc_bits(&bd);
+	} else {
+		clrbits_le32(plat->hmc + ECCCTRL1,
+			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(plat->hmc + ECCCTRL2,
+			     (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
+			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
+	}
+
+	/* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
+	writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
+
+	sdram_size_check(&bd);
+
+	priv->info.base = bd.bi_dram[0].start;
+	priv->info.size = gd->ram_size;
+
+	debug("DDR: HMC init success\n");
+	return 0;
+}
diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 8c8ea19eb9..435f42bc0a 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -40,9 +40,6 @@ struct sdram_prot_rule {
 	u32	hi_prot_id;
 };
 
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
 
 /**
@@ -455,12 +452,14 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
 			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 	int ret;
 
-	writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
+	writel(rows,
+	       socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
 
 	sdr_load_regs(sdr_ctrl, cfg);
 
 	/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
-	writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
+	writel(cfg->fpgaport_rst,
+	       socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(3));
 
 	/* only enable if the FPGA is programmed */
 	if (fpgamgr_test_fpga_ready()) {
@@ -516,7 +515,8 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
 	 * since the FB specifies we modify ROWBITs to work around SDRAM
 	 * controller issue.
 	 */
-	row = readl(&sysmgr_regs->iswgrp_handoff[4]);
+	row = readl(socfpga_get_sysmgr_addr() +
+		    SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
 	if (row == 0)
 		row = rowbits;
 	/*
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 82d9a13efa..93c15dd18b 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -14,32 +14,15 @@
 #include <reset.h>
 #include "sdram_s10.h"
 #include <wait_bit.h>
-#include <asm/arch/firewall_s10.h>
-#include <asm/arch/system_manager.h>
+#include <asm/arch/firewall.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 
-struct altera_sdram_priv {
-	struct ram_info info;
-	struct reset_ctl_bulk resets;
-};
-
-struct altera_sdram_platdata {
-	void __iomem *hmc;
-	void __iomem *ddr_sch;
-	void __iomem *iomhc;
-};
-
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_system_manager *sysmgr_regs =
-		(void *)SOCFPGA_SYSMGR_ADDRESS;
-
 #define DDR_CONFIG(A, B, C, R)	(((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
 
-#define PGTABLE_OFF	0x4000
-
 /* The followring are the supported configurations */
 u32 ddr_config[] = {
 	/* DDR_CONFIG(Address order,Bank,Column,Row) */
@@ -66,28 +49,6 @@ u32 ddr_config[] = {
 	DDR_CONFIG(1, 4, 10, 17),
 };
 
-static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
-{
-	return readl(plat->iomhc + reg);
-}
-
-static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
-{
-	return readl(plat->hmc + reg);
-}
-
-static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
-			  u32 data, u32 reg)
-{
-	return writel(data, plat->hmc + reg);
-}
-
-static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
-			  u32 reg)
-{
-	return writel(data, plat->ddr_sch + reg);
-}
-
 int match_ddr_conf(u32 ddr_conf)
 {
 	int i;
@@ -99,192 +60,12 @@ int match_ddr_conf(u32 ddr_conf)
 	return 0;
 }
 
-static int emif_clear(struct altera_sdram_platdata *plat)
-{
-	hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
-
-	return wait_for_bit_le32((const void *)(plat->hmc +
-				 RSTHANDSHAKESTAT),
-				 DDR_HMC_RSTHANDSHAKE_MASK,
-				 false, 1000, false);
-}
-
-static int emif_reset(struct altera_sdram_platdata *plat)
-{
-	u32 c2s, s2c, ret;
-
-	c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
-	s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
-
-	debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
-	      c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
-	      hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
-	      hmc_readl(plat, DRAMSTS));
-
-	if (s2c && emif_clear(plat)) {
-		printf("DDR: emif_clear() failed\n");
-		return -1;
-	}
-
-	debug("DDR: Triggerring emif reset\n");
-	hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
-
-	/* if seq2core[3] = 0, we are good */
-	ret = wait_for_bit_le32((const void *)(plat->hmc +
-				 RSTHANDSHAKESTAT),
-				 DDR_HMC_SEQ2CORE_INT_RESP_MASK,
-				 false, 1000, false);
-	if (ret) {
-		printf("DDR: failed to get ack from EMIF\n");
-		return ret;
-	}
-
-	ret = emif_clear(plat);
-	if (ret) {
-		printf("DDR: emif_clear() failed\n");
-		return ret;
-	}
-
-	debug("DDR: %s triggered successly\n", __func__);
-	return 0;
-}
-
-static int poll_hmc_clock_status(void)
-{
-	return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
-				 SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
-}
-
-static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
-{
-	phys_size_t i;
-
-	if (addr % CONFIG_SYS_CACHELINE_SIZE) {
-		printf("DDR: address 0x%llx is not cacheline size aligned.\n",
-		       addr);
-		hang();
-	}
-
-	if (size % CONFIG_SYS_CACHELINE_SIZE) {
-		printf("DDR: size 0x%llx is not multiple of cacheline size\n",
-		       size);
-		hang();
-	}
-
-	/* Use DC ZVA instruction to clear memory to zeros by a cache line */
-	for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
-		asm volatile("dc zva, %0"
-		     :
-		     : "r"(addr)
-		     : "memory");
-		addr += CONFIG_SYS_CACHELINE_SIZE;
-	}
-}
-
-static void sdram_init_ecc_bits(bd_t *bd)
-{
-	phys_size_t size, size_init;
-	phys_addr_t start_addr;
-	int bank = 0;
-	unsigned int start = get_timer(0);
-
-	icache_enable();
-
-	start_addr = bd->bi_dram[0].start;
-	size = bd->bi_dram[0].size;
-
-	/* Initialize small block for page table */
-	memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
-	gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
-	gd->arch.tlb_size = PGTABLE_SIZE;
-	start_addr += PGTABLE_SIZE + PGTABLE_OFF;
-	size -= (PGTABLE_OFF + PGTABLE_SIZE);
-	dcache_enable();
-
-	while (1) {
-		while (size) {
-			size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
-			sdram_clear_mem(start_addr, size_init);
-			size -= size_init;
-			start_addr += size_init;
-			WATCHDOG_RESET();
-		}
-
-		bank++;
-		if (bank >= CONFIG_NR_DRAM_BANKS)
-			break;
-
-		start_addr = bd->bi_dram[bank].start;
-		size = bd->bi_dram[bank].size;
-	}
-
-	dcache_disable();
-	icache_disable();
-
-	printf("SDRAM-ECC: Initialized success with %d ms\n",
-	       (unsigned int)get_timer(start));
-}
-
-static void sdram_size_check(bd_t *bd)
-{
-	phys_size_t total_ram_check = 0;
-	phys_size_t ram_check = 0;
-	phys_addr_t start = 0;
-	int bank;
-
-	/* Sanity check ensure correct SDRAM size specified */
-	debug("DDR: Running SDRAM size sanity check\n");
-
-	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		start = bd->bi_dram[bank].start;
-		while (ram_check < bd->bi_dram[bank].size) {
-			ram_check += get_ram_size((void *)(start + ram_check),
-						 (phys_size_t)SZ_1G);
-		}
-		total_ram_check += ram_check;
-		ram_check = 0;
-	}
-
-	/* If the ram_size is 2GB smaller, we can assume the IO space is
-	 * not mapped in.  gd->ram_size is the actual size of the dram
-	 * not the accessible size.
-	 */
-	if (total_ram_check != gd->ram_size) {
-		puts("DDR: SDRAM size check failed!\n");
-		hang();
-	}
-
-	debug("DDR: SDRAM size check passed!\n");
-}
-
-/**
- * sdram_calculate_size() - Calculate SDRAM size
- *
- * Calculate SDRAM device size based on SDRAM controller parameters.
- * Size is specified in bytes.
- */
-static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
-{
-	u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
-
-	phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
-			 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
-			 DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
-			 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
-			 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
-
-	size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
-			DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
-
-	return size;
-}
-
 /**
  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
  *
  * Initialize the SDRAM MMR.
  */
-static int sdram_mmr_init_full(struct udevice *dev)
+int sdram_mmr_init_full(struct udevice *dev)
 {
 	struct altera_sdram_platdata *plat = dev->platdata;
 	struct altera_sdram_priv *priv = dev_get_priv(dev);
@@ -324,6 +105,20 @@ static int sdram_mmr_init_full(struct udevice *dev)
 	clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
 		     CCU_ADBASE_DI_MASK);
 
+	/* Enable access to DDR from TCU */
+	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
+		     CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
+		     CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
+		     CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
+		     CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
+		     CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
+		     CCU_ADBASE_DI_MASK);
+
 	/* this enables nonsecure access to DDR */
 	/* mpuregion0addr_limit */
 	FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
@@ -512,9 +307,6 @@ static int sdram_mmr_init_full(struct udevice *dev)
 			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 		hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
 
-		/* Enable non-secure writes to HMC Adapter for SDRAM ECC */
-		writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
-
 		/* Initialize memory content if not from warm reset */
 		if (!cpu_has_been_warmreset())
 			sdram_init_ecc_bits(&bd);
@@ -528,6 +320,9 @@ static int sdram_mmr_init_full(struct udevice *dev)
 			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 	}
 
+	/* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
+	writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
+
 	sdram_size_check(&bd);
 
 	priv->info.base = bd.bi_dram[0].start;
@@ -537,80 +332,3 @@ static int sdram_mmr_init_full(struct udevice *dev)
 	return 0;
 }
 
-static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
-{
-	struct altera_sdram_platdata *plat = dev->platdata;
-	fdt_addr_t addr;
-
-	addr = dev_read_addr_index(dev, 0);
-	if (addr == FDT_ADDR_T_NONE)
-		return -EINVAL;
-	plat->ddr_sch = (void __iomem *)addr;
-
-	addr = dev_read_addr_index(dev, 1);
-	if (addr == FDT_ADDR_T_NONE)
-		return -EINVAL;
-	plat->iomhc = (void __iomem *)addr;
-
-	addr = dev_read_addr_index(dev, 2);
-	if (addr == FDT_ADDR_T_NONE)
-		return -EINVAL;
-	plat->hmc = (void __iomem *)addr;
-
-	return 0;
-}
-
-static int altera_sdram_probe(struct udevice *dev)
-{
-	int ret;
-	struct altera_sdram_priv *priv = dev_get_priv(dev);
-
-	ret = reset_get_bulk(dev, &priv->resets);
-	if (ret) {
-		dev_err(dev, "Can't get reset: %d\n", ret);
-		return -ENODEV;
-	}
-	reset_deassert_bulk(&priv->resets);
-
-	if (sdram_mmr_init_full(dev) != 0) {
-		puts("SDRAM init failed.\n");
-		goto failed;
-	}
-
-	return 0;
-
-failed:
-	reset_release_bulk(&priv->resets);
-	return -ENODEV;
-}
-
-static int altera_sdram_get_info(struct udevice *dev,
-				 struct ram_info *info)
-{
-	struct altera_sdram_priv *priv = dev_get_priv(dev);
-
-	info->base = priv->info.base;
-	info->size = priv->info.size;
-
-	return 0;
-}
-
-static struct ram_ops altera_sdram_ops = {
-	.get_info = altera_sdram_get_info,
-};
-
-static const struct udevice_id altera_sdram_ids[] = {
-	{ .compatible = "altr,sdr-ctl-s10" },
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(altera_sdram) = {
-	.name = "altr_sdr_ctl",
-	.id = UCLASS_RAM,
-	.of_match = altera_sdram_ids,
-	.ops = &altera_sdram_ops,
-	.ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
-	.platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
-	.probe = altera_sdram_probe,
-	.priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
-};
diff --git a/drivers/ddr/altera/sdram_s10.h b/drivers/ddr/altera/sdram_s10.h
index 096c06cba2..cca4cb35ec 100644
--- a/drivers/ddr/altera/sdram_s10.h
+++ b/drivers/ddr/altera/sdram_s10.h
@@ -11,48 +11,6 @@
 #define DDR_READ_LATENCY_DELAY		40
 #define DDR_ACTIVATE_FAWBANK		0x1
 
-/* ECC HMC registers */
-#define DDRIOCTRL			0x8
-#define DDRCALSTAT			0xc
-#define DRAMADDRWIDTH			0xe0
-#define ECCCTRL1			0x100
-#define ECCCTRL2			0x104
-#define ERRINTEN			0x110
-#define ERRINTENS			0x114
-#define INTMODE				0x11c
-#define INTSTAT				0x120
-#define AUTOWB_CORRADDR			0x138
-#define ECC_REG2WRECCDATABUS		0x144
-#define ECC_DIAGON			0x150
-#define ECC_DECSTAT			0x154
-#define HPSINTFCSEL			0x210
-#define RSTHANDSHAKECTRL		0x214
-#define RSTHANDSHAKESTAT		0x218
-
-#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK		0x00000003
-#define DDR_HMC_DDRCALSTAT_CAL_MSK		BIT(0)
-#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK	BIT(16)
-#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK		BIT(8)
-#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK		BIT(0)
-#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK		BIT(8)
-#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK		BIT(0)
-#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK	BIT(16)
-#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK	BIT(0)
-#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK	BIT(0)
-#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK	BIT(1)
-#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK	BIT(0)
-#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK	BIT(1)
-#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK	BIT(16)
-#define DDR_HMC_INTMODE_INTMODE_SET_MSK		BIT(0)
-#define DDR_HMC_RSTHANDSHAKE_MASK		0x000000ff
-#define DDR_HMC_CORE2SEQ_INT_REQ		0xF
-#define DDR_HMC_SEQ2CORE_INT_RESP_MASK		BIT(3)
-#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK		0x001f1f1f
-
-#define	DDR_HMC_ERRINTEN_INTMASK				\
-		(DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |	\
-		 DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
-
 /* NOC DDR scheduler */
 #define DDR_SCH_ID_COREID		0
 #define DDR_SCH_ID_REVID		0x4
@@ -79,110 +37,6 @@
 #define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF		2
 #define DDR_SCH_DEVTODEV_BUSWRTORD_OFF		4
 
-/* HMC MMR IO48 registers */
-#define CTRLCFG0			0x28
-#define CTRLCFG1			0x2c
-#define DRAMTIMING0			0x50
-#define CALTIMING0			0x7c
-#define CALTIMING1			0x80
-#define CALTIMING2			0x84
-#define CALTIMING3			0x88
-#define CALTIMING4			0x8c
-#define CALTIMING9			0xa0
-#define DRAMADDRW			0xa8
-#define DRAMSTS				0xec
-#define NIOSRESERVED0			0x110
-#define NIOSRESERVED1			0x114
-#define NIOSRESERVED2			0x118
-
-#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x)			\
-	(((x) >> 0) & 0x1F)
-#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x)			\
-	(((x) >> 5) & 0x1F)
-#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x)		\
-	(((x) >> 10) & 0xF)
-#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x)		\
-	(((x) >> 14) & 0x3)
-#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x)			\
-	(((x) >> 16) & 0x7)
-
-#define CTRLCFG0_CFG_MEMTYPE(x)				\
-	(((x) >> 0) & 0xF)
-#define CTRLCFG0_CFG_DIMM_TYPE(x)			\
-	(((x) >> 4) & 0x7)
-#define CTRLCFG0_CFG_AC_POS(x)				\
-	(((x) >> 7) & 0x3)
-#define CTRLCFG0_CFG_CTRL_BURST_LEN(x)			\
-	(((x) >> 9) & 0x1F)
-
-#define CTRLCFG1_CFG_DBC3_BURST_LEN(x)			\
-	(((x) >> 0) & 0x1F)
-#define CTRLCFG1_CFG_ADDR_ORDER(x)			\
-	(((x) >> 5) & 0x3)
-#define CTRLCFG1_CFG_CTRL_EN_ECC(x)			\
-	(((x) >> 7) & 0x1)
-
-#define DRAMTIMING0_CFG_TCL(x)				\
-	(((x) >> 0) & 0x7F)
-
-#define CALTIMING0_CFG_ACT_TO_RDWR(x)			\
-	(((x) >> 0) & 0x3F)
-#define CALTIMING0_CFG_ACT_TO_PCH(x)			\
-	(((x) >> 6) & 0x3F)
-#define CALTIMING0_CFG_ACT_TO_ACT(x)			\
-	(((x) >> 12) & 0x3F)
-#define CALTIMING0_CFG_ACT_TO_ACT_DB(x)			\
-	(((x) >> 18) & 0x3F)
-
-#define CALTIMING1_CFG_RD_TO_RD(x)			\
-	(((x) >> 0) & 0x3F)
-#define CALTIMING1_CFG_RD_TO_RD_DC(x)			\
-	(((x) >> 6) & 0x3F)
-#define CALTIMING1_CFG_RD_TO_RD_DB(x)			\
-	(((x) >> 12) & 0x3F)
-#define CALTIMING1_CFG_RD_TO_WR(x)			\
-	(((x) >> 18) & 0x3F)
-#define CALTIMING1_CFG_RD_TO_WR_DC(x)			\
-	(((x) >> 24) & 0x3F)
-
-#define CALTIMING2_CFG_RD_TO_WR_DB(x)			\
-	(((x) >> 0) & 0x3F)
-#define CALTIMING2_CFG_RD_TO_WR_PCH(x)			\
-	(((x) >> 6) & 0x3F)
-#define CALTIMING2_CFG_RD_AP_TO_VALID(x)		\
-	(((x) >> 12) & 0x3F)
-#define CALTIMING2_CFG_WR_TO_WR(x)			\
-	(((x) >> 18) & 0x3F)
-#define CALTIMING2_CFG_WR_TO_WR_DC(x)			\
-	(((x) >> 24) & 0x3F)
-
-#define CALTIMING3_CFG_WR_TO_WR_DB(x)			\
-	(((x) >> 0) & 0x3F)
-#define CALTIMING3_CFG_WR_TO_RD(x)			\
-	(((x) >> 6) & 0x3F)
-#define CALTIMING3_CFG_WR_TO_RD_DC(x)			\
-	(((x) >> 12) & 0x3F)
-#define CALTIMING3_CFG_WR_TO_RD_DB(x)			\
-	(((x) >> 18) & 0x3F)
-#define CALTIMING3_CFG_WR_TO_PCH(x)			\
-	(((x) >> 24) & 0x3F)
-
-#define CALTIMING4_CFG_WR_AP_TO_VALID(x)		\
-	(((x) >> 0) & 0x3F)
-#define CALTIMING4_CFG_PCH_TO_VALID(x)			\
-	(((x) >> 6) & 0x3F)
-#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x)		\
-	(((x) >> 12) & 0x3F)
-#define CALTIMING4_CFG_ARF_TO_VALID(x)			\
-	(((x) >> 18) & 0xFF)
-#define CALTIMING4_CFG_PDN_TO_VALID(x)			\
-	(((x) >> 26) & 0x3F)
-
-#define CALTIMING9_CFG_4_ACT_TO_ACT(x)			\
-	(((x) >> 0) & 0xFF)
-
-/* Firewall DDR scheduler MPFE */
-#define FW_HMC_ADAPTOR_REG_ADDR			0xf8020004
-#define FW_HMC_ADAPTOR_MPU_MASK			BIT(0)
+#include "sdram_soc64.h"
 
 #endif /* _SDRAM_S10_H_ */
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
new file mode 100644
index 0000000000..985a108b1c
--- /dev/null
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <div64.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <reset.h>
+#include "sdram_soc64.h"
+#include <wait_bit.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+
+#define PGTABLE_OFF	0x4000
+
+u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
+{
+	return readl(plat->iomhc + reg);
+}
+
+u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
+{
+	return readl(plat->hmc + reg);
+}
+
+u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+		   u32 data, u32 reg)
+{
+	return writel(data, plat->hmc + reg);
+}
+
+u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+		   u32 reg)
+{
+	return writel(data, plat->ddr_sch + reg);
+}
+
+int emif_clear(struct altera_sdram_platdata *plat)
+{
+	hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
+
+	return wait_for_bit_le32((const void *)(plat->hmc +
+				 RSTHANDSHAKESTAT),
+				 DDR_HMC_RSTHANDSHAKE_MASK,
+				 false, 1000, false);
+}
+
+int emif_reset(struct altera_sdram_platdata *plat)
+{
+	u32 c2s, s2c, ret;
+
+	c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
+	s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
+
+	debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
+	      c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
+	      hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
+	      hmc_readl(plat, DRAMSTS));
+
+	if (s2c && emif_clear(plat)) {
+		printf("DDR: emif_clear() failed\n");
+		return -1;
+	}
+
+	debug("DDR: Triggerring emif reset\n");
+	hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
+
+	/* if seq2core[3] = 0, we are good */
+	ret = wait_for_bit_le32((const void *)(plat->hmc +
+				 RSTHANDSHAKESTAT),
+				 DDR_HMC_SEQ2CORE_INT_RESP_MASK,
+				 false, 1000, false);
+	if (ret) {
+		printf("DDR: failed to get ack from EMIF\n");
+		return ret;
+	}
+
+	ret = emif_clear(plat);
+	if (ret) {
+		printf("DDR: emif_clear() failed\n");
+		return ret;
+	}
+
+	debug("DDR: %s triggered successly\n", __func__);
+	return 0;
+}
+
+int poll_hmc_clock_status(void)
+{
+	return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
+				 SYSMGR_SOC64_HMC_CLK),
+				 SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
+}
+
+void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
+{
+	phys_size_t i;
+
+	if (addr % CONFIG_SYS_CACHELINE_SIZE) {
+		printf("DDR: address 0x%llx is not cacheline size aligned.\n",
+		       addr);
+		hang();
+	}
+
+	if (size % CONFIG_SYS_CACHELINE_SIZE) {
+		printf("DDR: size 0x%llx is not multiple of cacheline size\n",
+		       size);
+		hang();
+	}
+
+	/* Use DC ZVA instruction to clear memory to zeros by a cache line */
+	for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
+		asm volatile("dc zva, %0"
+		     :
+		     : "r"(addr)
+		     : "memory");
+		addr += CONFIG_SYS_CACHELINE_SIZE;
+	}
+}
+
+void sdram_init_ecc_bits(bd_t *bd)
+{
+	phys_size_t size, size_init;
+	phys_addr_t start_addr;
+	int bank = 0;
+	unsigned int start = get_timer(0);
+
+	icache_enable();
+
+	start_addr = bd->bi_dram[0].start;
+	size = bd->bi_dram[0].size;
+
+	/* Initialize small block for page table */
+	memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
+	gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
+	gd->arch.tlb_size = PGTABLE_SIZE;
+	start_addr += PGTABLE_SIZE + PGTABLE_OFF;
+	size -= (PGTABLE_OFF + PGTABLE_SIZE);
+	dcache_enable();
+
+	while (1) {
+		while (size) {
+			size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
+			sdram_clear_mem(start_addr, size_init);
+			size -= size_init;
+			start_addr += size_init;
+			WATCHDOG_RESET();
+		}
+
+		bank++;
+		if (bank >= CONFIG_NR_DRAM_BANKS)
+			break;
+
+		start_addr = bd->bi_dram[bank].start;
+		size = bd->bi_dram[bank].size;
+	}
+
+	dcache_disable();
+	icache_disable();
+
+	printf("SDRAM-ECC: Initialized success with %d ms\n",
+	       (unsigned int)get_timer(start));
+}
+
+void sdram_size_check(bd_t *bd)
+{
+	phys_size_t total_ram_check = 0;
+	phys_size_t ram_check = 0;
+	phys_addr_t start = 0;
+	int bank;
+
+	/* Sanity check ensure correct SDRAM size specified */
+	debug("DDR: Running SDRAM size sanity check\n");
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start = bd->bi_dram[bank].start;
+		while (ram_check < bd->bi_dram[bank].size) {
+			ram_check += get_ram_size((void *)(start + ram_check),
+						 (phys_size_t)SZ_1G);
+		}
+		total_ram_check += ram_check;
+		ram_check = 0;
+	}
+
+	/* If the ram_size is 2GB smaller, we can assume the IO space is
+	 * not mapped in.  gd->ram_size is the actual size of the dram
+	 * not the accessible size.
+	 */
+	if (total_ram_check != gd->ram_size) {
+		puts("DDR: SDRAM size check failed!\n");
+		hang();
+	}
+
+	debug("DDR: SDRAM size check passed!\n");
+}
+
+/**
+ * sdram_calculate_size() - Calculate SDRAM size
+ *
+ * Calculate SDRAM device size based on SDRAM controller parameters.
+ * Size is specified in bytes.
+ */
+phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
+{
+	u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
+
+	phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+			 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
+			 DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
+			 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
+			 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
+
+	size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
+			DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
+
+	return size;
+}
+
+static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
+{
+	struct altera_sdram_platdata *plat = dev->platdata;
+	fdt_addr_t addr;
+
+	addr = dev_read_addr_index(dev, 0);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	plat->ddr_sch = (void __iomem *)addr;
+
+	addr = dev_read_addr_index(dev, 1);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	plat->iomhc = (void __iomem *)addr;
+
+	addr = dev_read_addr_index(dev, 2);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	plat->hmc = (void __iomem *)addr;
+
+	return 0;
+}
+
+static int altera_sdram_probe(struct udevice *dev)
+{
+	int ret;
+	struct altera_sdram_priv *priv = dev_get_priv(dev);
+
+	ret = reset_get_bulk(dev, &priv->resets);
+	if (ret) {
+		dev_err(dev, "Can't get reset: %d\n", ret);
+		return -ENODEV;
+	}
+	reset_deassert_bulk(&priv->resets);
+
+	if (sdram_mmr_init_full(dev) != 0) {
+		puts("SDRAM init failed.\n");
+		goto failed;
+	}
+
+	return 0;
+
+failed:
+	reset_release_bulk(&priv->resets);
+	return -ENODEV;
+}
+
+static int altera_sdram_get_info(struct udevice *dev,
+				 struct ram_info *info)
+{
+	struct altera_sdram_priv *priv = dev_get_priv(dev);
+
+	info->base = priv->info.base;
+	info->size = priv->info.size;
+
+	return 0;
+}
+
+static struct ram_ops altera_sdram_ops = {
+	.get_info = altera_sdram_get_info,
+};
+
+static const struct udevice_id altera_sdram_ids[] = {
+	{ .compatible = "altr,sdr-ctl-s10" },
+	{ .compatible = "intel,sdr-ctl-agilex" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(altera_sdram) = {
+	.name = "altr_sdr_ctl",
+	.id = UCLASS_RAM,
+	.of_match = altera_sdram_ids,
+	.ops = &altera_sdram_ops,
+	.ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
+	.probe = altera_sdram_probe,
+	.priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
+};
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
new file mode 100644
index 0000000000..7b25a80ae2
--- /dev/null
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef	_SDRAM_SOC64_H_
+#define	_SDRAM_SOC64_H_
+
+#include <common.h>
+#include <linux/sizes.h>
+
+struct altera_sdram_priv {
+	struct ram_info info;
+	struct reset_ctl_bulk resets;
+};
+
+struct altera_sdram_platdata {
+	void __iomem *hmc;
+	void __iomem *ddr_sch;
+	void __iomem *iomhc;
+};
+
+/* ECC HMC registers */
+#define DDRIOCTRL			0x8
+#define DDRCALSTAT			0xc
+#define DRAMADDRWIDTH			0xe0
+#define ECCCTRL1			0x100
+#define ECCCTRL2			0x104
+#define ERRINTEN			0x110
+#define ERRINTENS			0x114
+#define INTMODE				0x11c
+#define INTSTAT				0x120
+#define AUTOWB_CORRADDR			0x138
+#define ECC_REG2WRECCDATABUS		0x144
+#define ECC_DIAGON			0x150
+#define ECC_DECSTAT			0x154
+#define HPSINTFCSEL			0x210
+#define RSTHANDSHAKECTRL		0x214
+#define RSTHANDSHAKESTAT		0x218
+
+#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK		0x00000003
+#define DDR_HMC_DDRCALSTAT_CAL_MSK		BIT(0)
+#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK	BIT(16)
+#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK		BIT(8)
+#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK		BIT(0)
+#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK		BIT(8)
+#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK		BIT(0)
+#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK	BIT(16)
+#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK	BIT(0)
+#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK	BIT(0)
+#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK	BIT(1)
+#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK	BIT(0)
+#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK	BIT(1)
+#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK	BIT(16)
+#define DDR_HMC_INTMODE_INTMODE_SET_MSK		BIT(0)
+#define DDR_HMC_RSTHANDSHAKE_MASK		0x000000ff
+#define DDR_HMC_CORE2SEQ_INT_REQ		0xF
+#define DDR_HMC_SEQ2CORE_INT_RESP_MASK		BIT(3)
+#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK		0x001f1f1f
+
+#define	DDR_HMC_ERRINTEN_INTMASK				\
+		(DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |	\
+		 DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
+
+/* HMC MMR IO48 registers */
+#define CTRLCFG0			0x28
+#define CTRLCFG1			0x2c
+#define CTRLCFG3                        0x34
+#define DRAMTIMING0			0x50
+#define CALTIMING0			0x7c
+#define CALTIMING1			0x80
+#define CALTIMING2			0x84
+#define CALTIMING3			0x88
+#define CALTIMING4			0x8c
+#define CALTIMING9			0xa0
+#define DRAMADDRW			0xa8
+#define DRAMSTS				0xec
+#define NIOSRESERVED0			0x110
+#define NIOSRESERVED1			0x114
+#define NIOSRESERVED2			0x118
+
+#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x)			\
+	(((x) >> 0) & 0x1F)
+#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x)			\
+	(((x) >> 5) & 0x1F)
+#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x)		\
+	(((x) >> 10) & 0xF)
+#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x)		\
+	(((x) >> 14) & 0x3)
+#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x)			\
+	(((x) >> 16) & 0x7)
+
+#define CTRLCFG0_CFG_MEMTYPE(x)				\
+	(((x) >> 0) & 0xF)
+#define CTRLCFG0_CFG_DIMM_TYPE(x)			\
+	(((x) >> 4) & 0x7)
+#define CTRLCFG0_CFG_AC_POS(x)				\
+	(((x) >> 7) & 0x3)
+#define CTRLCFG0_CFG_CTRL_BURST_LEN(x)			\
+	(((x) >> 9) & 0x1F)
+
+#define CTRLCFG1_CFG_DBC3_BURST_LEN(x)			\
+	(((x) >> 0) & 0x1F)
+#define CTRLCFG1_CFG_ADDR_ORDER(x)			\
+	(((x) >> 5) & 0x3)
+#define CTRLCFG1_CFG_CTRL_EN_ECC(x)			\
+	(((x) >> 7) & 0x1)
+
+#define DRAMTIMING0_CFG_TCL(x)				\
+	(((x) >> 0) & 0x7F)
+
+#define CALTIMING0_CFG_ACT_TO_RDWR(x)			\
+	(((x) >> 0) & 0x3F)
+#define CALTIMING0_CFG_ACT_TO_PCH(x)			\
+	(((x) >> 6) & 0x3F)
+#define CALTIMING0_CFG_ACT_TO_ACT(x)			\
+	(((x) >> 12) & 0x3F)
+#define CALTIMING0_CFG_ACT_TO_ACT_DB(x)			\
+	(((x) >> 18) & 0x3F)
+
+#define CALTIMING1_CFG_RD_TO_RD(x)			\
+	(((x) >> 0) & 0x3F)
+#define CALTIMING1_CFG_RD_TO_RD_DC(x)			\
+	(((x) >> 6) & 0x3F)
+#define CALTIMING1_CFG_RD_TO_RD_DB(x)			\
+	(((x) >> 12) & 0x3F)
+#define CALTIMING1_CFG_RD_TO_WR(x)			\
+	(((x) >> 18) & 0x3F)
+#define CALTIMING1_CFG_RD_TO_WR_DC(x)			\
+	(((x) >> 24) & 0x3F)
+
+#define CALTIMING2_CFG_RD_TO_WR_DB(x)			\
+	(((x) >> 0) & 0x3F)
+#define CALTIMING2_CFG_RD_TO_WR_PCH(x)			\
+	(((x) >> 6) & 0x3F)
+#define CALTIMING2_CFG_RD_AP_TO_VALID(x)		\
+	(((x) >> 12) & 0x3F)
+#define CALTIMING2_CFG_WR_TO_WR(x)			\
+	(((x) >> 18) & 0x3F)
+#define CALTIMING2_CFG_WR_TO_WR_DC(x)			\
+	(((x) >> 24) & 0x3F)
+
+#define CALTIMING3_CFG_WR_TO_WR_DB(x)			\
+	(((x) >> 0) & 0x3F)
+#define CALTIMING3_CFG_WR_TO_RD(x)			\
+	(((x) >> 6) & 0x3F)
+#define CALTIMING3_CFG_WR_TO_RD_DC(x)			\
+	(((x) >> 12) & 0x3F)
+#define CALTIMING3_CFG_WR_TO_RD_DB(x)			\
+	(((x) >> 18) & 0x3F)
+#define CALTIMING3_CFG_WR_TO_PCH(x)			\
+	(((x) >> 24) & 0x3F)
+
+#define CALTIMING4_CFG_WR_AP_TO_VALID(x)		\
+	(((x) >> 0) & 0x3F)
+#define CALTIMING4_CFG_PCH_TO_VALID(x)			\
+	(((x) >> 6) & 0x3F)
+#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x)		\
+	(((x) >> 12) & 0x3F)
+#define CALTIMING4_CFG_ARF_TO_VALID(x)			\
+	(((x) >> 18) & 0xFF)
+#define CALTIMING4_CFG_PDN_TO_VALID(x)			\
+	(((x) >> 26) & 0x3F)
+
+#define CALTIMING9_CFG_4_ACT_TO_ACT(x)			\
+	(((x) >> 0) & 0xFF)
+
+/* Firewall DDR scheduler MPFE */
+#define FW_HMC_ADAPTOR_REG_ADDR			0xf8020004
+#define FW_HMC_ADAPTOR_MPU_MASK			BIT(0)
+
+u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg);
+u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg);
+u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+		   u32 data, u32 reg);
+u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+		   u32 reg);
+int emif_clear(struct altera_sdram_platdata *plat);
+int emif_reset(struct altera_sdram_platdata *plat);
+int poll_hmc_clock_status(void);
+void sdram_clear_mem(phys_addr_t addr, phys_size_t size);
+void sdram_init_ecc_bits(bd_t *bd);
+void sdram_size_check(bd_t *bd);
+phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat);
+int sdram_mmr_init_full(struct udevice *dev);
+
+#endif /* _SDRAM_SOC64_H_ */
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 5fb9d6a191..2853581b97 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -30,9 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
 static const struct socfpga_fpga_manager *fpga_manager_base =
 		(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
 
-static const struct socfpga_system_manager *system_manager_base =
-		(void *)SOCFPGA_SYSMGR_ADDRESS;
-
 static void fpgamgr_set_cd_ratio(unsigned long ratio);
 
 static uint32_t fpgamgr_get_msel(void)
@@ -818,7 +815,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 	}
 
 	/* Disable all signals from HPS peripheral controller to FPGA */
-	writel(0, &system_manager_base->fpgaintf_en_global);
+	writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 
 	/* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
 	socfpga_bridges_reset();
@@ -910,7 +907,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 	memset(&rbfinfo, 0, sizeof(rbfinfo));
 
 	/* Disable all signals from hps peripheral controller to fpga */
-	writel(0, &system_manager_base->fpgaintf_en_global);
+	writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 
 	/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
 	socfpga_bridges_reset();
diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
index 6d16e0b37f..d73474f29e 100644
--- a/drivers/fpga/socfpga_gen5.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -15,8 +15,6 @@
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
 	(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -214,7 +212,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 	/* Prior programming the FPGA, all bridges need to be shut off */
 
 	/* Disable all signals from hps peripheral controller to fpga */
-	writel(0, &sysmgr_regs->fpgaintfgrp_module);
+	writel(0, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_FPGAINFGRP_MODULE);
 
 	/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS	0x5080
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 739c1629a2..568a3e77d3 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -18,11 +18,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_clock_manager *clock_manager_base =
-		(void *)SOCFPGA_CLKMGR_ADDRESS;
-static const struct socfpga_system_manager *system_manager_base =
-		(void *)SOCFPGA_SYSMGR_ADDRESS;
-
 struct socfpga_dwmci_plat {
 	struct mmc_config cfg;
 	struct mmc mmc;
@@ -56,19 +51,19 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
 			 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
 
 	/* Disable SDMMC clock. */
-	clrbits_le32(&clock_manager_base->per_pll.en,
-		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
+		     CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 
 	debug("%s: drvsel %d smplsel %d\n", __func__,
 	      priv->drvsel, priv->smplsel);
-	writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
+	writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
 
 	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
-		readl(&system_manager_base->sdmmcgrp_ctrl));
+		readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
 
 	/* Enable SDMMC clock */
-	setbits_le32(&clock_manager_base->per_pll.en,
-		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
+		     CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 }
 
 static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c
index d6c26a5b23..3390b7bdc2 100644
--- a/drivers/sysreset/sysreset_socfpga.c
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -12,7 +12,7 @@
 #include <asm/arch/reset_manager.h>
 
 struct socfpga_sysreset_data {
-	struct socfpga_reset_manager *rstmgr_base;
+	void __iomem *rstmgr_base;
 };
 
 static int socfpga_sysreset_request(struct udevice *dev,
@@ -23,11 +23,11 @@ static int socfpga_sysreset_request(struct udevice *dev,
 	switch (type) {
 	case SYSRESET_WARM:
 		writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB),
-		       &data->rstmgr_base->ctrl);
+		       data->rstmgr_base + RSTMGR_CTRL);
 		break;
 	case SYSRESET_COLD:
 		writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB),
-		       &data->rstmgr_base->ctrl);
+		       data->rstmgr_base + RSTMGR_CTRL);
 		break;
 	default:
 		return -EPROTONOSUPPORT;
diff --git a/include/configs/socfpga_agilex_socdk.h b/include/configs/socfpga_agilex_socdk.h
new file mode 100644
index 0000000000..4eede7c84b
--- /dev/null
+++ b/include/configs/socfpga_agilex_socdk.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_AGILEX_H__
+#define __CONFIG_SOCFGPA_AGILEX_H__
+
+#include <configs/socfpga_soc64_common.h>
+
+#endif	/* __CONFIG_SOCFGPA_AGILEX_H__ */
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
new file mode 100644
index 0000000000..4afadafd35
--- /dev/null
+++ b/include/configs/socfpga_soc64_common.h
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
+#define __CONFIG_SOCFPGA_SOC64_COMMON_H__
+
+#include <asm/arch/base_addr_s10.h>
+#include <asm/arch/handoff_s10.h>
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_LOADADDR			0x2000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_REMAKE_ELF
+/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
+#define CPU_RELEASE_ADDR		0xFFD12210
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_MEM_RESERVE_SECURE	0	/* using OCRAM, not DDR */
+
+/*
+ * U-Boot console configurations
+ */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+/*
+ * U-Boot run time memory configurations
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x40000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR  \
+					+ CONFIG_SYS_INIT_RAM_SIZE \
+					- S10_HANDOFF_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_SP_ADDR)
+#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
+
+/*
+ * U-Boot environment configurations
+ */
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
+
+/*
+ * QSPI support
+ */
+ #ifdef CONFIG_CADENCE_QSPI
+/* Enable it if you want to use dual-stacked mode */
+/*#define CONFIG_QSPI_RBF_ADDR		0x720000*/
+
+/* Flash device info */
+
+/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT			"nor0=ff705000.spi.0"
+#endif /* CONFIG_SPL_BUILD */
+
+#ifndef __ASSEMBLY__
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
+#endif
+
+#endif /* CONFIG_CADENCE_QSPI */
+
+/*
+ * Boot arguments passed to the boot command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will override also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "earlycon"
+#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
+			   "run mmcboot"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"bootfile=Image\0" \
+	"fdt_addr=8000000\0" \
+	"fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"booti ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootfile};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"linux_qspi_enable=if sf probe; then " \
+		"echo Enabling QSPI at Linux DTB...;" \
+		"fdt addr ${fdt_addr}; fdt resize;" \
+		"fdt set /soc/spi@ff8d2000 status okay;" \
+		"fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
+		" ${qspi_clock}; fi; \0" \
+	"scriptaddr=0x02100000\0" \
+	"scriptfile=u-boot.scr\0" \
+	"fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+		   "then source ${scriptaddr}; fi\0" \
+	"socfpga_legacy_reset_compat=1\0"
+
+/*
+ * Generic Interrupt Controller Definitions
+ */
+#define CONFIG_GICV2
+
+/*
+ * External memory configurations
+ */
+#define PHYS_SDRAM_1			0x0
+#define PHYS_SDRAM_1_SIZE		(1 * 1024 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_MEMTEST_START	0
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE - 0x200000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_CLK		100000000
+#define CONFIG_SYS_NS16550_MEM32
+
+/*
+ * Timer & watchdog configurations
+ */
+#define COUNTER_FREQUENCY		400000000
+
+/*
+ * SDMMC configurations
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256
+#endif
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_DW_ALTDESCRIPTOR
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * L4 Watchdog
+ */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+#ifndef __ASSEMBLY__
+unsigned int cm_get_l4_sys_free_clk_hz(void);
+#define CONFIG_DW_WDT_CLOCK_KHZ		(cm_get_l4_sys_free_clk_hz() / 1000)
+#endif
+#else
+#define CONFIG_DW_WDT_CLOCK_KHZ		100000
+#endif
+#endif
+
+/*
+ * SPL memory layout
+ *
+ * On chip RAM
+ * 0xFFE0_0000 ...... Start of OCRAM
+ * SPL code, rwdata
+ * empty space
+ * 0xFFEx_xxxx ...... Top of stack (grows down)
+ * 0xFFEy_yyyy ...... Global Data
+ * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
+ * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
+ * 0xFFE3_FFFF ...... End of OCRAM
+ *
+ * SDRAM
+ * 0x0000_0000 ...... Start of SDRAM_1
+ * unused / empty space for image loading
+ * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
+ * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
+ * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
+ *
+ */
+#define CONFIG_SPL_TARGET		"spl/u-boot-spl.hex"
+#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
+#define CONFIG_SPL_BSS_START_ADDR	(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
+					- CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR \
+					- CONFIG_SYS_SPL_MALLOC_SIZE)
+
+/* SPL SDMMC boot support */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+
+#endif	/* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
index a10cbec17f..09b46ba013 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -1,198 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
  *
  */
 
 #ifndef __CONFIG_SOCFGPA_STRATIX10_H__
 #define __CONFIG_SOCFGPA_STRATIX10_H__
 
-#include <asm/arch/base_addr_s10.h>
-#include <asm/arch/handoff_s10.h>
+#include <configs/socfpga_soc64_common.h>
 
-/*
- * U-Boot general configurations
- */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_LOADADDR			0x2000000
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-#define CONFIG_REMAKE_ELF
-/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
-#define CPU_RELEASE_ADDR		0xFFD12210
-#define CONFIG_SYS_CACHELINE_SIZE	64
-#define CONFIG_SYS_MEM_RESERVE_SECURE	0	/* using OCRAM, not DDR */
-
-/*
- * U-Boot console configurations
- */
-#define CONFIG_SYS_MAXARGS		64
-#define CONFIG_SYS_CBSIZE		2048
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-/* Extend size of kernel image for uncompression */
-#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
-
-/*
- * U-Boot run time memory configurations
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x40000
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR  \
-					+ CONFIG_SYS_INIT_RAM_SIZE \
-					- S10_HANDOFF_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_SP_ADDR)
-#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
-
-/*
- * U-Boot environment configurations
- */
-#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
-
-/*
- * QSPI support
- */
- #ifdef CONFIG_CADENCE_QSPI
-/* Enable it if you want to use dual-stacked mode */
-/*#define CONFIG_QSPI_RBF_ADDR		0x720000*/
-
-/* Flash device info */
-
-/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_MTD_PARTITIONS
-#define MTDIDS_DEFAULT			"nor0=ff705000.spi.0"
-#endif /* CONFIG_SPL_BUILD */
-
-#ifndef __ASSEMBLY__
-unsigned int cm_get_qspi_controller_clk_hz(void);
-#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
-#endif
-
-#endif /* CONFIG_CADENCE_QSPI */
-
-/*
- * Boot arguments passed to the boot command. The value of
- * CONFIG_BOOTARGS goes into the environment value "bootargs".
- * Do note the value will override also the chosen node in FDT blob.
- */
-#define CONFIG_BOOTARGS "earlycon"
-#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
-			   "run mmcboot"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"bootfile=Image\0" \
-	"fdt_addr=8000000\0" \
-	"fdtimage=socfpga_stratix10_socdk.dtb\0" \
-	"mmcroot=/dev/mmcblk0p2\0" \
-	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-		" root=${mmcroot} rw rootwait;" \
-		"booti ${loadaddr} - ${fdt_addr}\0" \
-	"mmcload=mmc rescan;" \
-		"load mmc 0:1 ${loadaddr} ${bootfile};" \
-		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-	"linux_qspi_enable=if sf probe; then " \
-		"echo Enabling QSPI at Linux DTB...;" \
-		"fdt addr ${fdt_addr}; fdt resize;" \
-		"fdt set /soc/spi@ff8d2000 status okay;" \
-		"fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
-		" ${qspi_clock}; fi; \0" \
-	"scriptaddr=0x02100000\0" \
-	"scriptfile=u-boot.scr\0" \
-	"fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
-		   "then source ${scriptaddr}; fi\0" \
-	"socfpga_legacy_reset_compat=1\0"
-
-/*
- * Generic Interrupt Controller Definitions
- */
-#define CONFIG_GICV2
-
-/*
- * External memory configurations
- */
-#define PHYS_SDRAM_1			0x0
-#define PHYS_SDRAM_1_SIZE		(1 * 1024 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE		0
-#define CONFIG_SYS_MEMTEST_START	0
-#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE - 0x200000
-
-/*
- * Serial / UART configurations
- */
-#define CONFIG_SYS_NS16550_CLK		100000000
-#define CONFIG_SYS_NS16550_MEM32
-
-/*
- * Timer & watchdog configurations
- */
-#define COUNTER_FREQUENCY		400000000
-
-/*
- * SDMMC configurations
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256
-#endif
-/*
- * Flash configurations
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-
-/* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_DW_ALTDESCRIPTOR
-#endif /* CONFIG_CMD_NET */
-
-/*
- * L4 Watchdog
- */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_DESIGNWARE_WATCHDOG
-#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
-#ifndef __ASSEMBLY__
-unsigned int cm_get_l4_sys_free_clk_hz(void);
-#define CONFIG_DW_WDT_CLOCK_KHZ		(cm_get_l4_sys_free_clk_hz() / 1000)
-#endif
-#endif
-
-/*
- * SPL memory layout
- *
- * On chip RAM
- * 0xFFE0_0000 ...... Start of OCRAM
- * SPL code, rwdata
- * empty space
- * 0xFFEx_xxxx ...... Top of stack (grows down)
- * 0xFFEy_yyyy ...... Global Data
- * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
- * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
- * 0xFFE3_FFFF ...... End of OCRAM
- *
- * SDRAM
- * 0x0000_0000 ...... Start of SDRAM_1
- * unused / empty space for image loading
- * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
- * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
- * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
- *
- */
-#define CONFIG_SPL_TARGET		"spl/u-boot-spl.hex"
-#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
-#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
-#define CONFIG_SPL_BSS_START_ADDR	(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
-					- CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE	(CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR \
-					- CONFIG_SYS_SPL_MALLOC_SIZE)
-
-/* SPL SDMMC boot support */
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
-
-#endif	/* __CONFIG_H */
+#endif	/* __CONFIG_SOCFGPA_STRATIX10_H__ */
diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h
new file mode 100644
index 0000000000..f751aad4da
--- /dev/null
+++ b/include/dt-bindings/clock/agilex-clock.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+#ifndef __AGILEX_CLOCK_H
+#define __AGILEX_CLOCK_H
+
+/* fixed rate clocks */
+#define AGILEX_OSC1			0
+#define AGILEX_CB_INTOSC_HS_DIV2_CLK	1
+#define AGILEX_CB_INTOSC_LS_CLK		2
+#define AGILEX_L4_SYS_FREE_CLK		3
+#define AGILEX_F2S_FREE_CLK		4
+
+/* PLL clocks */
+#define AGILEX_MAIN_PLL_CLK		5
+#define AGILEX_MAIN_PLL_C0_CLK		6
+#define AGILEX_MAIN_PLL_C1_CLK		7
+#define AGILEX_MAIN_PLL_C2_CLK		8
+#define AGILEX_MAIN_PLL_C3_CLK		9
+#define AGILEX_PERIPH_PLL_CLK		10
+#define AGILEX_PERIPH_PLL_C0_CLK	11
+#define AGILEX_PERIPH_PLL_C1_CLK	12
+#define AGILEX_PERIPH_PLL_C2_CLK	13
+#define AGILEX_PERIPH_PLL_C3_CLK	14
+#define AGILEX_MPU_FREE_CLK		15
+#define AGILEX_MPU_CCU_CLK		16
+#define AGILEX_BOOT_CLK			17
+
+/* fixed factor clocks */
+#define AGILEX_L3_MAIN_FREE_CLK		18
+#define AGILEX_NOC_FREE_CLK		19
+#define AGILEX_S2F_USR0_CLK		20
+#define AGILEX_NOC_CLK			21
+#define AGILEX_EMAC_A_FREE_CLK		22
+#define AGILEX_EMAC_B_FREE_CLK		23
+#define AGILEX_EMAC_PTP_FREE_CLK	24
+#define AGILEX_GPIO_DB_FREE_CLK		25
+#define AGILEX_SDMMC_FREE_CLK		26
+#define AGILEX_S2F_USER0_FREE_CLK	27
+#define AGILEX_S2F_USER1_FREE_CLK	28
+#define AGILEX_PSI_REF_FREE_CLK		29
+
+/* Gate clocks */
+#define AGILEX_MPU_CLK			30
+#define AGILEX_MPU_PERIPH_CLK		31
+#define AGILEX_L4_MAIN_CLK		32
+#define AGILEX_L4_MP_CLK		33
+#define AGILEX_L4_SP_CLK		34
+#define AGILEX_CS_AT_CLK		35
+#define AGILEX_CS_TRACE_CLK		36
+#define AGILEX_CS_PDBG_CLK		37
+#define AGILEX_CS_TIMER_CLK		38
+#define AGILEX_S2F_USER0_CLK		39
+#define AGILEX_EMAC0_CLK		40
+#define AGILEX_EMAC1_CLK		41
+#define AGILEX_EMAC2_CLK		42
+#define AGILEX_EMAC_PTP_CLK		43
+#define AGILEX_GPIO_DB_CLK		44
+#define AGILEX_NAND_CLK			45
+#define AGILEX_PSI_REF_CLK		46
+#define AGILEX_S2F_USER1_CLK		47
+#define AGILEX_SDMMC_CLK		48
+#define AGILEX_SPI_M_CLK		49
+#define AGILEX_USB_CLK			50
+#define AGILEX_NAND_X_CLK		51
+#define AGILEX_NAND_ECC_CLK		52
+#define AGILEX_NUM_CLKS			53
+
+#endif	/* __AGILEX_CLOCK_H */