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authorTom Rini <trini@konsulko.com>2017-07-07 15:21:45 -0400
committerTom Rini <trini@konsulko.com>2017-07-11 22:41:56 -0400
commitab86dc7948778cb087fa8cf9949bd53441097cf8 (patch)
treeef51edf5fa28d8cdeaa1a4f1e560b9047d98a094
parent39b4f6bce332dc1ebd9c2b94910a1d58e1628f13 (diff)
ARM: ti816x: Fix enabling GPIO0, enable GPIO1 as well
The TI816x has 2 GPIO banks. For bank 0 we had been clearing the enable bit when setting BIT(8). Correct this by setting it to BIT(1) | BIT(8) after we set and wait for BIT(1) (aka PRCM_MOD_EN). Enable GPIO1 as well so that when CMD_GPIO is enabled it won't crash probing the second bank. Enable CMD_GPIO on ti816x_evm. Signed-off-by: Tom Rini <trini@konsulko.com>
-rw-r--r--arch/arm/mach-omap2/am33xx/clock_ti816x.c8
-rw-r--r--configs/ti816x_evm_defconfig1
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/am33xx/clock_ti816x.c b/arch/arm/mach-omap2/am33xx/clock_ti816x.c
index 967623d467b..e9c7b2d9969 100644
--- a/arch/arm/mach-omap2/am33xx/clock_ti816x.c
+++ b/arch/arm/mach-omap2/am33xx/clock_ti816x.c
@@ -335,7 +335,13 @@ static void peripheral_enable(void)
writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
;
- writel((BIT(8)), &cmalwon->gpio0clkctrl);
+ writel((BIT(1) | BIT(8)), &cmalwon->gpio0clkctrl);
+
+ /* Enable gpio1 */
+ writel(PRCM_MOD_EN, &cmalwon->gpio1clkctrl);
+ while (readl(&cmalwon->gpio1clkctrl) != PRCM_MOD_EN)
+ ;
+ writel((BIT(1) | BIT(8)), &cmalwon->gpio1clkctrl);
/* Enable spi */
writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 7f43ecb7ebc..2ae72b2f77d 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -27,6 +27,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_ISO_PARTITION is not set