ARM: dts: socfpga: Factor out U-Boot specifics from A10 handoff files

Pull out the u-boot,dm-pre-reloc from socfpga_arria10_socdk_sdmmc_handoff.dtsi
into separate dtsi header file to make it easier to patch in custom handoff
dtsi files, without having to manually add the U-Boot bits. Shuffle the include
clauses in the A10 DT files to make it obvious what gets included where without
having to follow confusing long chain of includes, i.e. board DT file includes
everything it needs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

4 files changed, 71 insertions, 18 deletions

diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
new file mode 100644
index 00000000000..39a8d9a3e76
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/ {
+	chosen {
+		u-boot,dm-pre-reloc;
+	};
+
+	clocks {
+		u-boot,dm-pre-reloc;
+
+		altera_arria10_hps_eosc1 {
+			u-boot,dm-pre-reloc;
+		};
+
+		altera_arria10_hps_cb_intosc_ls {
+			u-boot,dm-pre-reloc;
+		};
+
+		altera_arria10_hps_f2h_free {
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clock_manager@0xffd04000 {
+		u-boot,dm-pre-reloc;
+
+		mainpll {
+			u-boot,dm-pre-reloc;
+		};
+
+		perpll {
+			u-boot,dm-pre-reloc;
+		};
+
+		alteragrp {
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	pinmux@0xffd07000 {
+		u-boot,dm-pre-reloc;
+
+		shared {
+			u-boot,dm-pre-reloc;
+		};
+
+		dedicated {
+			u-boot,dm-pre-reloc;
+		};
+
+		dedicated_cfg {
+			u-boot,dm-pre-reloc;
+		};
+
+		fpga {
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	noc@0xffd10000 {
+		u-boot,dm-pre-reloc;
+
+		firewall {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index 42e888548ee..6e5578d7bd3 100644
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -14,7 +14,8 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
-#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+
+#include "socfpga_arria10.dtsi"
 
 / {
 	model = "Altera SOCFPGA Arria 10";
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index cc761967c77..d6b6c2ddc09 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -17,6 +17,8 @@
 
 /dts-v1/;
 #include "socfpga_arria10_socdk.dtsi"
+#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
 
 / {
 	chosen {
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
index 39009654d9d..0446fd441e2 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
@@ -11,8 +11,6 @@
  *</auto-generated>
  */
 
-#include "socfpga_arria10.dtsi"
-
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -24,13 +22,11 @@
 
 	/* Clock sources */
 	clocks {
-		u-boot,dm-pre-reloc;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
 		/* Clock source: altera_arria10_hps_eosc1 */
 		altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
-			u-boot,dm-pre-reloc;
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <25000000>;
@@ -39,7 +35,6 @@
 
 		/* Clock source: altera_arria10_hps_cb_intosc_ls */
 		altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
-			u-boot,dm-pre-reloc;
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <60000000>;
@@ -48,7 +43,6 @@
 
 		/* Clock source: altera_arria10_hps_f2h_free */
 		altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
-			u-boot,dm-pre-reloc;
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <200000000>;
@@ -62,14 +56,12 @@
 	 * Binding: device
 	 */
 	i_clk_mgr: clock_manager@0xffd04000 {
-		u-boot,dm-pre-reloc;
 		compatible = "altr,socfpga-a10-clk-init";
 		reg = <0xffd04000 0x00000200>;
 		reg-names = "soc_clock_manager_OCP_SLV";
 
 		/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
 		mainpll {
-			u-boot,dm-pre-reloc;
 			vco0-psrc = <0>;	/* Field: vco0.psrc */
 			vco1-denom = <1>;	/* Field: vco1.denom */
 			vco1-numer = <191>;	/* Field: vco1.numer */
@@ -98,7 +90,6 @@
 
 		/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
 		perpll {
-			u-boot,dm-pre-reloc;
 			vco0-psrc = <0>;	/* Field: vco0.psrc */
 			vco1-denom = <1>;	/* Field: vco1.denom */
 			vco1-numer = <159>;	/* Field: vco1.numer */
@@ -124,7 +115,6 @@
 
 		/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
 		alteragrp {
-			u-boot,dm-pre-reloc;
 			nocclk = <0x0384000b>;	/* Register: nocclk */
 			mpuclk = <0x03840001>;	/* Register: mpuclk */
 		};
@@ -136,7 +126,6 @@
 	 * Binding: pinmux
 	 */
 	i_io48_pin_mux: pinmux@0xffd07000 {
-		u-boot,dm-pre-reloc;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "pinctrl-single";
@@ -145,7 +134,6 @@
 
 		/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
 		shared {
-			u-boot,dm-pre-reloc;
 			reg = <0xffd07000 0x00000200>;
 			pinctrl-single,register-width = <32>;
 			pinctrl-single,function-mask = <0x0000000f>;
@@ -202,7 +190,6 @@
 
 		/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
 		dedicated {
-			u-boot,dm-pre-reloc;
 			reg = <0xffd07200 0x00000200>;
 			pinctrl-single,register-width = <32>;
 			pinctrl-single,function-mask = <0x0000000f>;
@@ -225,7 +212,6 @@
 
 		/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
 		dedicated_cfg {
-			u-boot,dm-pre-reloc;
 			reg = <0xffd07200 0x00000200>;
 			pinctrl-single,register-width = <32>;
 			pinctrl-single,function-mask = <0x003f3f3f>;
@@ -252,7 +238,6 @@
 
 		/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
 		fpga {
-			u-boot,dm-pre-reloc;
 			reg = <0xffd07400 0x00000100>;
 			pinctrl-single,register-width = <32>;
 			pinctrl-single,function-mask = <0x00000001>;
@@ -283,13 +268,11 @@
 	 * Binding: device
 	 */
 	i_noc: noc@0xffd10000 {
-		u-boot,dm-pre-reloc;
 		compatible = "altr,socfpga-a10-noc";
 		reg = <0xffd10000 0x00008000>;
 		reg-names = "mpu_m0";
 
 		firewall {
-			u-boot,dm-pre-reloc;
 			/*
 			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
 			 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit