Merge remote-tracking branch 'origin/imx_v2022.04' into lf_v2022.04

* origin/imx_v2022.04: (6 commits)
  LFU-369-4: Added configs required for dcp_rng driver
  LFU-369-3: Added dcp_rng driver device binding code
  LFU-369-2: Uboot RNG Driver using Data Co-processor
  LFU-369-1: Adding rngb entry in imx6ull device tree
  LFU-373 imx8ulp: upower: Do not send AFFB enable message for A1
  ...

16 files changed, 271 insertions, 15 deletions

diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi
index 46e7ad6bab..c5d5a5ab7b 100644
--- a/arch/arm/dts/imx6ull.dtsi
+++ b/arch/arm/dts/imx6ull.dtsi
@@ -66,6 +66,12 @@
 				clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
 				clock-names = "dcp";
 			};
+			rngb: rng@2284000 {
+				compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb";
+				reg = <0x02284000 0x4000>;
+				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_DUMMY>;
+			};
 
 			iomuxc_snvs: iomuxc-snvs@2290000 {
 				compatible = "fsl,imx6ull-iomuxc-snvs";
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index b4240c83a1..2898c8b96c 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -447,10 +447,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
 	debug("PLL4 rate %ukhz\n", pll4_rate);
 
 	for (pfd = 12; pfd <= 35; pfd++) {
-		parent_rate = pll4_rate;
-		parent_rate = parent_rate * 18 / pfd;
-
 		for (div = 1; div <= 64; div++) {
+			parent_rate = pll4_rate;
+			parent_rate = parent_rate * 18 / pfd;
 			parent_rate = parent_rate / div;
 
 			for (pcd = 0; pcd < 8; pcd++) {
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
index c24bc079ec..87152ca818 100644
--- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
@@ -6,6 +6,7 @@
 #include <log.h>
 #include <asm/io.h>
 #include <linux/delay.h>
+#include <asm/arch/sys_proto.h>
 
 #include "upower_soc_defs.h"
 #include "upower_api.h"
@@ -191,20 +192,22 @@ int upower_init(void)
 	if (ret != UPWR_REQ_OK)
 		printk("Faliure %d\n", ret);
 
-	/* Enable AFBB for AP domain */
-	bias.apply = BIAS_APPLY_APD;
-	bias.dommode = AFBB_BIAS_MODE;
-	ret = upwr_pwm_chng_dom_bias(&bias, NULL);
+	if (is_soc_rev(CHIP_REV_1_0)) {
+		/* Enable AFBB for AP domain */
+		bias.apply = BIAS_APPLY_APD;
+		bias.dommode = AFBB_BIAS_MODE;
+		ret = upwr_pwm_chng_dom_bias(&bias, NULL);
 
-	if (ret)
-		printf("Enable AFBB for APD bias fail %d\n", ret);
-	else
-		printf("Enable AFBB for APD bias ok\n");
+		if (ret)
+			printf("Enable AFBB for APD bias fail %d\n", ret);
+		else
+			printf("Enable AFBB for APD bias ok\n");
 
-	upower_wait_resp();
-	ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000);
-	if (ret != UPWR_REQ_OK)
-		printk("Faliure %d\n", ret);
+		upower_wait_resp();
+		ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000);
+		if (ret != UPWR_REQ_OK)
+			printk("Faliure %d\n", ret);
+	}
 
 	return 0;
 }
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 3e538754d9..9bf16119c2 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -31,6 +31,8 @@
 #include <hang.h>
 #include <cpu_func.h>
 #include <env.h>
+#include<dm/device-internal.h>
+#include<dm/lists.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -1005,6 +1007,20 @@ int arch_misc_init(void)
 		if (ret)
 			printf("Failed to initialize caam_jr: %d\n", ret);
 	}
+
+	if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = device_bind_driver(NULL, "dcp_rng", "dcp_rng", NULL);
+		if (ret)
+			printf("Couldn't bind dcp rng driver (%d)\n", ret);
+
+		ret = uclass_get_device_by_driver(UCLASS_RNG, DM_DRIVER_GET(dcp_rng), &dev);
+		if (ret)
+			printf("Failed to initialize dcp rng: %d\n", ret);
+	}
+
 	setup_serial_number();
 	return 0;
 }
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index cdcd496edd..79964b3ccf 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -99,3 +99,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_emmc_defconfig b/configs/mx6ull_14x14_evk_emmc_defconfig
index d94085e13b..f4bcc40544 100644
--- a/configs/mx6ull_14x14_evk_emmc_defconfig
+++ b/configs/mx6ull_14x14_evk_emmc_defconfig
@@ -99,3 +99,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_nand_defconfig b/configs/mx6ull_14x14_evk_nand_defconfig
index 16900e04f0..1931293bc6 100644
--- a/configs/mx6ull_14x14_evk_nand_defconfig
+++ b/configs/mx6ull_14x14_evk_nand_defconfig
@@ -106,3 +106,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_optee_defconfig b/configs/mx6ull_14x14_evk_optee_defconfig
index 2bb3d44fa8..ba1c8e02a4 100644
--- a/configs/mx6ull_14x14_evk_optee_defconfig
+++ b/configs/mx6ull_14x14_evk_optee_defconfig
@@ -100,3 +100,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index baab9c2ee8..9c1354981e 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -100,3 +100,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_qspi1_defconfig b/configs/mx6ull_14x14_evk_qspi1_defconfig
index f1fe8b4000..13a1eec75e 100644
--- a/configs/mx6ull_14x14_evk_qspi1_defconfig
+++ b/configs/mx6ull_14x14_evk_qspi1_defconfig
@@ -102,3 +102,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_9x9_evk_defconfig b/configs/mx6ull_9x9_evk_defconfig
index 66eacc55fa..3f73c5e697 100644
--- a/configs/mx6ull_9x9_evk_defconfig
+++ b/configs/mx6ull_9x9_evk_defconfig
@@ -103,3 +103,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_EFI_PARTITION=y
+
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_9x9_evk_plugin_defconfig b/configs/mx6ull_9x9_evk_plugin_defconfig
index 7eace52b5c..41468f2d38 100644
--- a/configs/mx6ull_9x9_evk_plugin_defconfig
+++ b/configs/mx6ull_9x9_evk_plugin_defconfig
@@ -104,3 +104,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_9x9_evk_qspi1_defconfig b/configs/mx6ull_9x9_evk_qspi1_defconfig
index f145b65e6c..f1446ef8e0 100644
--- a/configs/mx6ull_9x9_evk_qspi1_defconfig
+++ b/configs/mx6ull_9x9_evk_qspi1_defconfig
@@ -106,3 +106,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 702d204a3d..da5955e31d 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -96,3 +96,13 @@ config RNG_SELF_TEST
 	 must be run before running any RNG based crypto implementation.
 
 endif
+
+config FSL_DCP_RNG
+	bool "Enable Random Number Generator support"
+	depends on DM_RNG
+	default n
+	help
+	Enable support for the hardware based random number generator
+	module of the DCP.It uses the True Random Number Generator (TRNG)
+	and a Pseudo-Random Number Generator (PRNG) to achieve a true
+	randomness and cryptographic strength.
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index 926300e2ab..c653208d23 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
 obj-$(CONFIG_FSL_BLOB) += fsl_blob.o
 obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
 obj-$(CONFIG_FSL_CAAM_RNG) += rng.o
+obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o
 obj-$(CONFIG_IMX_CAAM_MFG_PROT) += fsl_mfgprot.o
 obj-$(CONFIG_RNG_SELF_TEST) += rng_self_test.o
 obj-$(CONFIG_CMD_PROVISION_KEY) += fsl_aes.o tag_object.o
diff --git a/drivers/crypto/fsl/dcp_rng.c b/drivers/crypto/fsl/dcp_rng.c
new file mode 100644
index 0000000000..a797710c2e
--- /dev/null
+++ b/drivers/crypto/fsl/dcp_rng.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * RNG driver for Freescale RNGC
+ *
+ * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx>
+ *	Copyright 2022 NXP
+ *
+ * Based on RNGC driver in drivers/char/hw_random/imx-rngc.c in Linux
+ */
+
+#include <asm/cache.h>
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <rng.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <dm/root.h>
+
+#define DCP_RNG_MAX_FIFO_STORE_SIZE	4
+#define RNGC_VER_ID			0x0000
+#define RNGC_COMMAND			0x0004
+#define RNGC_CONTROL			0x0008
+#define RNGC_STATUS			0x000C
+#define RNGC_ERROR			0x0010
+#define RNGC_FIFO			0x0014
+
+/* the fields in the ver id register */
+#define RNGC_TYPE_SHIFT			28
+
+/* the rng_type field */
+#define RNGC_TYPE_RNGB			0x1
+#define RNGC_TYPE_RNGC			0x2
+
+#define RNGC_CMD_CLR_ERR		0x00000020
+#define RNGC_CMD_SEED			0x00000002
+
+#define RNGC_CTRL_AUTO_SEED		0x00000010
+
+#define RNGC_STATUS_ERROR		0x00010000
+#define RNGC_STATUS_FIFO_LEVEL_MASK	0x00000f00
+#define RNGC_STATUS_FIFO_LEVEL_SHIFT	8
+#define RNGC_STATUS_SEED_DONE		0x00000020
+#define RNGC_STATUS_ST_DONE		0x00000010
+
+#define RNGC_ERROR_STATUS_STAT_ERR	0x00000008
+
+#define RNGC_TIMEOUT			3000000U /* 3 sec */
+
+struct imx_rngc {
+	unsigned long base;
+};
+
+static int rngc_read(struct udevice *dev, void *data, size_t len)
+{
+	struct imx_rngc *rngc = dev_get_priv(dev);
+	u8 buffer[DCP_RNG_MAX_FIFO_STORE_SIZE];
+	u32 status, level;
+	size_t size;
+
+	while (len) {
+		status = readl(rngc->base + RNGC_STATUS);
+
+		/* is there some error while reading this random number? */
+		if (status & RNGC_STATUS_ERROR)
+			break;
+		/* how many random numbers are in FIFO? [0-16] */
+		level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
+			RNGC_STATUS_FIFO_LEVEL_SHIFT;
+
+		if (level) {
+			/* retrieve a random number from FIFO */
+			*(u32 *)buffer = readl(rngc->base + RNGC_FIFO);
+			size = min(len, sizeof(u32));
+			memcpy(data, buffer, size);
+			data += size;
+			len -= size;
+		}
+	}
+
+	return len ? -EIO : 0;
+}
+
+static int rngc_init(struct imx_rngc *rngc)
+{
+	u32 cmd, ctrl, status, err_reg = 0;
+	unsigned long long timeval = 0;
+	unsigned long long timeout = RNGC_TIMEOUT;
+
+	/* clear error */
+	cmd = readl(rngc->base + RNGC_COMMAND);
+	writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
+
+	/* create seed, repeat while there is some statistical error */
+	do {
+		/* seed creation */
+		cmd = readl(rngc->base + RNGC_COMMAND);
+		writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
+
+		udelay(1);
+		timeval += 1;
+
+		status = readl(rngc->base + RNGC_STATUS);
+		err_reg = readl(rngc->base + RNGC_ERROR);
+
+		if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE))
+			break;
+
+		if (timeval > timeout) {
+			debug("rngc timed out\n");
+			return -ETIMEDOUT;
+		}
+	} while (err_reg == RNGC_ERROR_STATUS_STAT_ERR);
+
+	if (err_reg)
+		return -EIO;
+
+	/*
+	 * enable automatic seeding, the rngc creates a new seed automatically
+	 * after serving 2^20 random 160-bit words
+	 */
+	ctrl = readl(rngc->base + RNGC_CONTROL);
+	ctrl |= RNGC_CTRL_AUTO_SEED;
+	writel(ctrl, rngc->base + RNGC_CONTROL);
+	return 0;
+}
+
+static int rngc_probe(struct udevice *dev)
+{
+	struct imx_rngc *rngc = dev_get_priv(dev);
+	fdt_addr_t addr;
+	u32 ver_id;
+	u8  rng_type;
+	int ret;
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	rngc->base = addr;
+	ver_id = readl(rngc->base + RNGC_VER_ID);
+	rng_type = ver_id >> RNGC_TYPE_SHIFT;
+	/*
+	 * This driver supports only RNGC and RNGB. (There's a different
+	 * driver for RNGA.)
+	 */
+	if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) {
+		ret = -ENODEV;
+		goto err;
+	}
+
+	ret = rngc_init(rngc);
+	if (ret)
+		goto err;
+
+	return 0;
+
+err:
+	printf("%s error = %d\n", __func__, ret);
+	return ret;
+}
+
+static const struct dm_rng_ops rngc_ops = {
+	.read = rngc_read,
+};
+
+static const struct udevice_id rngc_dt_ids[] = {
+	{ .compatible = "fsl,imx25-rngb" },
+	{ }
+};
+
+U_BOOT_DRIVER(dcp_rng) = {
+	.name = "dcp_rng",
+	.id = UCLASS_RNG,
+	.of_match = rngc_dt_ids,
+	.ops = &rngc_ops,
+	.probe = rngc_probe,
+	.priv_auto  = sizeof(struct imx_rngc),
+	.flags = DM_FLAG_ALLOC_PRIV_DMA,
+};