summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2019-04-08 10:15:32 +0000
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2019-05-22 12:24:24 +0530
commit8348e79865963a15dcb794f9a950f500c0b6f743 (patch)
tree3159f327fabd3b14d1d81f0de27e2895e2a8f084
parent626f3875e733dbd2f81cd0b749475e02a0ebb079 (diff)
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry
Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 12d709e23ec..db7577b6ed3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -251,7 +251,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
@@ -453,11 +453,13 @@ static void fix_pcie_mmu_map(void)
final_map[i].virt = 0x3000000000ULL;
final_map[i].size = 0x800000000ULL;
break;
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
case CONFIG_SYS_PCIE4_PHYS_ADDR:
final_map[i].phys = 0x3800000000ULL;
final_map[i].virt = 0x3800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
+#endif
default:
break;
}