diff options
| author | Stefan Roese <sr@denx.de> | 2017-03-09 12:01:57 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2017-03-29 07:44:26 +0200 |
| commit | 3e3cbb4967f0bff734aba20ca501bd391d858d77 (patch) | |
| tree | ce9bf5435b1ef5a90d4b651dd49b0371bc6a8645 | |
| parent | 025e5921be8555f38ad4578df07b337fb6d185e0 (diff) | |
net: mvpp2: Enable PHY polling mode on PPv2.2
Testing shows, that PHY polling needs to be enabled on Armada 7k/8k.
Otherwise ethernet transfers will not work correctly. PHY polling
is enabled per default after reset, so we do not need to specifically
enable it, but this makes it clearer.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| -rw-r--r-- | drivers/net/mvpp2.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 79442b873e8..36e209e83d2 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4957,14 +4957,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) if (priv->hw_version == MVPP22) mvpp2_axi_init(priv); - /* Disable HW PHY polling */ if (priv->hw_version == MVPP21) { + /* Disable HW PHY polling */ val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); val |= MVPP2_PHY_AN_STOP_SMI0_MASK; writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); } else { + /* Enable HW PHY polling */ val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); - val &= ~MVPP22_SMI_POLLING_EN; + val |= MVPP22_SMI_POLLING_EN; writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); } |