diff options
| author | Gary Bisson <gary.bisson@boundarydevices.com> | 2018-11-14 17:55:28 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-01-01 14:12:18 +0100 |
| commit | cb15885b48fa13b30fb24b24c7d1d9ae801caba4 (patch) | |
| tree | fbff662dc7ffbbe18603425a7490a6574105170e | |
| parent | 757ab988e44892dee6df4cc2a2a36f74eb6d73a6 (diff) | |
imx: mx8m: add memory mapping for CAAM and TCM
Otherwise can't boot the M4 core as it is impossible to load its
firmware into the TCM memory.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | arch/arm/mach-imx/mx8m/soc.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mx8m/soc.c b/arch/arm/mach-imx/mx8m/soc.c index 46873aa8dd..11251c5f9a 100644 --- a/arch/arm/mach-imx/mx8m/soc.c +++ b/arch/arm/mach-imx/mx8m/soc.c @@ -78,6 +78,22 @@ static struct mm_region imx8m_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE }, { + /* CAAM */ + .virt = 0x100000UL, + .phys = 0x100000UL, + .size = 0x8000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* TCM */ + .virt = 0x7C0000UL, + .phys = 0x7C0000UL, + .size = 0x80000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { /* OCRAM */ .virt = 0x900000UL, .phys = 0x900000UL, |