diff options
author | Stefan Agner <stefan.agner@toradex.com> | 2018-06-05 14:59:03 +0200 |
---|---|---|
committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-06-18 12:42:13 +0200 |
commit | b5cc69a7e8b6a6f5eaf7bf3e3a6dc8719bdbb2a5 (patch) | |
tree | 7753cc76f5d6a6db7fa8e33c29b30a28e2f6e854 | |
parent | e2d5257acd40f9473ca8b7cb7549bc69a106a58f (diff) |
colibri-vf: use leveling evaluated by DDR validation tools
The DDR validation tool (which is part of Processor Expert) allows
to evaluate leveling parameters for CR105/CR106/CR110. Several
runs have been made with Colibri VF50 and VF61 and it seems to
evaluate very similar values. Use this values by default.
Note: The newly evaluated parameters seem to require CTLUPD_AREF
to be enabled!
Note 2: The tool also evaluated 6 as a new value for PHY02/18
GATE_CFG (Coarse adjust of gate open time). However, this seems
not to work in practise.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
-rw-r--r-- | board/toradex/colibri_vf/colibri_vf.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 4c68eb1f65f..02997e18a82 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -44,6 +44,13 @@ DECLARE_GLOBAL_DATA_PTR; #define USB_CDET_GPIO 102 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { + { DDRMC_CR79_CTLUPD_AREF(1), 79 }, + /* sets manual values for read lvl. (gate) delay of data slice 0/1 */ + { DDRMC_CR105_RDLVL_DL_0(28), 105 }, + { DDRMC_CR106_RDLVL_GTDL_0(24), 106 }, + { DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 }, + { DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 }, + /* AXI */ { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, |