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authorSimon Glass <sjg@chromium.org>2015-06-05 14:39:43 -0600
committerTom Warren <twarren@nvidia.com>2015-06-09 09:56:15 -0700
commit7cfde8117fc74d7d10035dfef37ae21c014705fa (patch)
tree3065c5008129f653106f819bb43f8cebaa86edf7
parentc96d709f30cdf57ba78ef780066784a09276705f (diff)
tegra: nyan-big: Add additional clock and kernel init
We need to turn on all audio-related clocks for the Chrome OS kernel to boot. Otherwise it will hang when trying to enable audio. Also for Linux set up graphics driver video protection. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
-rw-r--r--board/nvidia/nyan-big/nyan-big.c69
1 files changed, 69 insertions, 0 deletions
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c
index ae8874bbd2..ba96401890 100644
--- a/board/nvidia/nyan-big/nyan-big.c
+++ b/board/nvidia/nyan-big/nyan-big.c
@@ -8,7 +8,12 @@
#include <common.h>
#include <errno.h>
#include <asm/gpio.h>
+#include <asm/io.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
#include <power/as3722.h>
#include <power/pmic.h>
#include "pinmux-config-nyan-big.h"
@@ -57,3 +62,67 @@ int tegra_lcd_pmic_init(int board_id)
return 0;
}
+
+/* Setup required information for Linux kernel */
+static void setup_kernel_info(void)
+{
+ struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
+
+ /* The kernel graphics driver needs this region locked down */
+ writel(0, &mc->mc_video_protect_bom);
+ writel(0, &mc->mc_video_protect_size_mb);
+ writel(1, &mc->mc_video_protect_reg_ctrl);
+}
+
+/*
+ * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
+ * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
+ * Otherwise reading AHUB devices will hang when the kernel boots.
+ */
+static void enable_required_clocks(void)
+{
+ static enum periph_id ids[] = {
+ PERIPH_ID_I2S0,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_I2S2,
+ PERIPH_ID_I2S3,
+ PERIPH_ID_I2S4,
+ PERIPH_ID_AUDIO,
+ PERIPH_ID_APBIF,
+ PERIPH_ID_DAM0,
+ PERIPH_ID_DAM1,
+ PERIPH_ID_DAM2,
+ PERIPH_ID_AMX0,
+ PERIPH_ID_AMX1,
+ PERIPH_ID_ADX0,
+ PERIPH_ID_ADX1,
+ PERIPH_ID_SPDIF,
+ PERIPH_ID_AFC0,
+ PERIPH_ID_AFC1,
+ PERIPH_ID_AFC2,
+ PERIPH_ID_AFC3,
+ PERIPH_ID_AFC4,
+ PERIPH_ID_AFC5,
+ PERIPH_ID_EXTPERIPH1
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ids); i++)
+ clock_enable(ids[i]);
+ udelay(2);
+ for (i = 0; i < ARRAY_SIZE(ids); i++)
+ reset_set_enable(ids[i], 0);
+}
+
+int nvidia_board_init(void)
+{
+ clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
+ clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000);
+
+ /* For external MAX98090 audio codec */
+ clock_external_output(1);
+ setup_kernel_info();
+ enable_required_clocks();
+
+ return 0;
+}