diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2011-11-29 10:16:14 -0800 |
|---|---|---|
| committer | Vadim Bendebury <vbendeb@chromium.org> | 2011-12-08 11:27:22 -0800 |
| commit | 9e3469de88449c1ca3af5f33a885890e9e931235 (patch) | |
| tree | ea3c67e6f0eff4b08535f36f91134e295d5b8207 | |
| parent | 04ed7a4e7f5e5fb60aead7855e7870068c0d6f23 (diff) | |
Make u-boot use the new PCH
New device ID range is included to allow the SPI driver to use the
Panther Point based controller and a new device ID is checked when
attaching the AHCI controller.
BUG=chrome-os-partner:7112
TEST=manual
After this change the top of the tree ChromeOS can be booted on IVB
reworked Stumpy platforms.
Change-Id: Ia41c17b58337cde2d041990b3d1c9da37c0cd92c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/12606
| -rw-r--r-- | drivers/spi/ich.c | 31 | ||||
| -rw-r--r-- | include/configs/coreboot.h | 8 | ||||
| -rw-r--r-- | include/pci_ids.h | 3 |
3 files changed, 27 insertions, 15 deletions
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 7a168e9310..a602532acb 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -275,11 +275,24 @@ void spi_free_slave(struct spi_slave *_slave) free(slave); } -static inline int spi_is_cougarpoint_lpc(uint16_t device_id) +/* + * Check if this device ID matches one of supported Intel PCH devices. + * + * Return the ICH version if there is a match, or zero otherwise. + */ +static inline int get_ich_version(uint16_t device_id) { - return device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX; -}; + if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) + return 7; + + if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && + device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || + (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && + device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) + return 9; + + return 0; +} void spi_init(void) { @@ -298,7 +311,7 @@ void spi_init(void) return; } - for (bus = 0; bus <= last_bus; bus++) { + for (bus = 0; (bus <= last_bus) && !ich_version; bus++) { uint32_t ids; uint16_t vendor_id, device_id; @@ -310,13 +323,7 @@ void spi_init(void) if (vendor_id != PCI_VENDOR_ID_INTEL) continue; - if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) { - ich_version = 7; - break; - } else if (spi_is_cougarpoint_lpc(device_id)) { - ich_version = 9; - break; - } + ich_version = get_ich_version(device_id); } if (!ich_version) { diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index c5bf9b7208..8baca6b368 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -55,9 +55,11 @@ #ifdef CONFIG_SCSI_AHCI #define CONFIG_SATA_INTEL 1 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE} + PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 diff --git a/include/pci_ids.h b/include/pci_ids.h index a893426ef3..dc5016d0c5 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2522,6 +2522,9 @@ #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e55 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e55 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 #define PCI_DEVICE_ID_INTEL_PATSBURG_LPC 0x1d40 #define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 |