diff options
author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2016-11-30 16:52:39 +0100 |
---|---|---|
committer | Max Krummenacher <max.krummenacher@toradex.com> | 2017-01-11 17:44:03 +0100 |
commit | 9b1d7cae48113f4443768a8a73c9fe4a12e2ada0 (patch) | |
tree | 47be5675973117ac090e0756796d734977dabd79 | |
parent | d257bdecf964c6af3009f323087d28000af26a0c (diff) |
mmc: tegra: allow disabling external clock loopback
Introduce CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK to disable the external clock
loopback and use the internal one on SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0
register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
-rw-r--r-- | arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 | ||||
-rw-r--r-- | drivers/mmc/Kconfig | 8 | ||||
-rw-r--r-- | drivers/mmc/tegra_mmc.c | 13 |
3 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index 64c848acb13..c40599ab19a 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -108,6 +108,8 @@ struct tegra_mmc { #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) +#define TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK (1 << 17) + #define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) #define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) #define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 19e89abc450..2c714206504 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -101,4 +101,12 @@ config TEGRA_MMC help This selects support for SDHCI on Tegra SoCs. +config TEGRA124_MMC_DISABLE_EXT_LOOPBACK + bool "Disable external clock loopback" + depends on TEGRA_MMC && TEGRA124 + help + Disable the external clock loopback and use the internal one on SDMMC3 + as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits + being set to 0xfffd according to the TRM. + endmenu diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 97b11545954..ed02708e9c7 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -511,6 +511,19 @@ static int tegra_mmc_init(struct mmc *mmc) tegra_mmc_reset(priv, mmc); +#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK) + /* + * Disable the external clock loopback and use the internal one on + * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 + * bits being set to 0xfffd according to the TRM. + */ + if (priv->reg == (void *)0x700b0400) { + mask = readl(&priv->reg->venmiscctl); + mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK; + writel(mask, &priv->reg->venmiscctl); + } +#endif + priv->version = readw(&priv->reg->hcver); debug("host version = %x\n", priv->version); |