diff options
| author | Ye Li <ye.li@nxp.com> | 2019-01-03 23:08:56 -0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2019-01-08 21:45:18 -0800 |
| commit | 94b6e0f525ce3adb015e41659b240689dab304ec (patch) | |
| tree | 05b848b7c13ab1284c42254ae074d38cbfbc03bb | |
| parent | 0e202ab93ea99c1e8ca855c896566a4a18957795 (diff) | |
MLK-20666-1 DTS: imx8mm: Enable i2c force idle
Add i2c gpio pinctrl settings and properties to enable i2c force idle.
Avoid any i2c bus not released by device during reboot.
Signed-off-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | arch/arm/dts/fsl-imx8mm-ddr3l-val.dts | 36 | ||||
| -rw-r--r-- | arch/arm/dts/fsl-imx8mm-ddr4-val.dts | 36 | ||||
| -rw-r--r-- | arch/arm/dts/fsl-imx8mm-evk.dts | 36 |
3 files changed, 99 insertions, 9 deletions
diff --git a/arch/arm/dts/fsl-imx8mm-ddr3l-val.dts b/arch/arm/dts/fsl-imx8mm-ddr3l-val.dts index a07c5bcadfe..906ba19f346 100644 --- a/arch/arm/dts/fsl-imx8mm-ddr3l-val.dts +++ b/arch/arm/dts/fsl-imx8mm-ddr3l-val.dts @@ -76,6 +76,27 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 @@ -129,8 +150,11 @@ &i2c1 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; status = "okay"; pmic: bd71837@4b { @@ -282,15 +306,21 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; status = "okay"; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/dts/fsl-imx8mm-ddr4-val.dts b/arch/arm/dts/fsl-imx8mm-ddr4-val.dts index b3fe4070dde..ffe5d28b138 100644 --- a/arch/arm/dts/fsl-imx8mm-ddr4-val.dts +++ b/arch/arm/dts/fsl-imx8mm-ddr4-val.dts @@ -94,6 +94,27 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + pinctrl_pmic: pmicirq { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 @@ -207,8 +228,11 @@ &i2c1 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; status = "okay"; pmic: bd71837@4b { @@ -363,8 +387,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; status = "okay"; typec_ptn5110_1: ptn5110@50 { @@ -396,8 +423,11 @@ &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/dts/fsl-imx8mm-evk.dts b/arch/arm/dts/fsl-imx8mm-evk.dts index 747abb4ed32..8c9cec0c5d1 100644 --- a/arch/arm/dts/fsl-imx8mm-evk.dts +++ b/arch/arm/dts/fsl-imx8mm-evk.dts @@ -101,6 +101,27 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + pinctrl_pmic: pmicirq { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 @@ -214,8 +235,11 @@ &i2c1 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; status = "okay"; pmic: bd71837@4b { @@ -370,8 +394,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; status = "okay"; typec_ptn5110_1: ptn5110@50 { @@ -403,8 +430,11 @@ &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; status = "okay"; }; |