diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-05-22 14:49:54 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-05-23 06:31:01 -0700 |
| commit | d27ca2cade7f6460ea8c248d3aa55b5337c9f411 (patch) | |
| tree | 7d1a211347b29a84c48470d33067b1b84ef8e433 | |
| parent | 95e018dc7eaf9735337c3aa35a3dc1910a86dbab (diff) | |
MLK-18367 imx8mm: change the GIC clock source
The GIC clock rate has some limitation, it should be
set to higher than 100MHz when NOC frequency is set to
the highest frequency. So switch the GIC clock source
to sys_pll2_100mhz.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit bd4cfcb391389287894bb5cd715be0a67f6332cf)
| -rw-r--r-- | arch/arm/mach-imx/imx8m/clock_imx8mm.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 25e465ee724..baa2d468e19 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -488,8 +488,6 @@ int clock_init() { uint32_t val_cfg0; - clock_enable(CCGR_GIC, 1); - /* Configure ARM at 1GHz */ clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | \ CLK_ROOT_SOURCE_SEL(0)); @@ -523,6 +521,12 @@ int clock_init() writel(val_cfg0, SYS_PLL2_GNRL_CTL); intpll_configure(ANATOP_SYSTEM_PLL3, INTPLL_OUT_800M); + + /* config GIC to sys_pll2_100m */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3)); + clock_enable(CCGR_GIC, 1); + /* * set uart clock root * 24M OSC |