diff options
| author | Wayne Zou <b36644@freescale.com> | 2012-05-16 14:39:36 +0800 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2012-09-12 11:05:50 -0400 |
| commit | c77472ca4ee8c2873352111f83c4cdc128e68e78 (patch) | |
| tree | b36ad2d50f66f4cb2f8e080ccac1fa38e7e3a615 | |
| parent | 5b0aad9358729ab5627dff7b1c07a6ce98f79367 (diff) | |
ENGR00180103 MX6 sabreauto: Adjust IPU AXI-id0/1 Qos value
set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7,
mx6q use AXI-id0 for IPU display channel, it should has
highest priority(bypass), and AXI-id1 for other IPU channel,
it has high priority.
Signed-off-by: Wayne Zou <b36644@freescale.com>
| -rw-r--r-- | board/freescale/mx6q_sabreauto/flash_header.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S index 3dc4790cdad..c63ed7ab6d0 100644 --- a/board/freescale/mx6q_sabreauto/flash_header.S +++ b/board/freescale/mx6q_sabreauto/flash_header.S @@ -156,9 +156,9 @@ MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) /* enable AXI cache for VDOA/VPU/IPU */ MXC_DCD_ITEM(81, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) -/* set IPU Qos=0x7 */ -MXC_DCD_ITEM(82, IOMUXC_BASE_ADDR + 0x018, 0x00070007) -MXC_DCD_ITEM(83, IOMUXC_BASE_ADDR + 0x01c, 0x00070007) +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +MXC_DCD_ITEM(82, IOMUXC_BASE_ADDR + 0x018, 0x007f007f) +MXC_DCD_ITEM(83, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f) #elif defined CONFIG_LPDDR2 dcd_hdr: .word 0x400804D2 /* Tag=0xD2, Len=128*8 + 4 + 4, Ver=0x40 */ @@ -453,9 +453,9 @@ MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) /* enable AXI cache for VDOA/VPU/IPU */ MXC_DCD_ITEM(86, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) -/* set IPU Qos=0x7 */ -MXC_DCD_ITEM(87, IOMUXC_BASE_ADDR + 0x018, 0x00070007) -MXC_DCD_ITEM(88, IOMUXC_BASE_ADDR + 0x01c, 0x00070007) +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +MXC_DCD_ITEM(87, IOMUXC_BASE_ADDR + 0x018, 0x007f007f) +MXC_DCD_ITEM(88, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f) #endif #endif |