MLK-18942-1 imx8: Update SCFW API to latest version

Update SCFW API from below SCFW commit which provides
the API to get seco events

    commit 50355d4b11b089be8fc1bc13afa7da001b081a44
    Author: Chuck Cannon <chuck.cannon@nxp.com>
    Date:   Mon Jan 14 12:30:42 2019 -0600

    SCF-275: Fix monitor error on command 'event'.

    Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>

Signed-off-by: Ye Li <ye.li@nxp.com>

8 files changed, 128 insertions, 24 deletions

diff --git a/arch/arm/include/asm/mach-imx/sci/rpc.h b/arch/arm/include/asm/mach-imx/sci/rpc.h
index f57ab4a86b0..399f7b13938 100644
--- a/arch/arm/include/asm/mach-imx/sci/rpc.h
+++ b/arch/arm/include/asm/mach-imx/sci/rpc.h
@@ -53,6 +53,8 @@
 #define SC_RPC_ASYNC_STATE_WR_DONE       5U
 
 #define SC_RPC_MU_GIR_SVC       0x1U
+#define SC_RPC_MU_GIR_WAKE      0x2U
+#define SC_RPC_MU_GIR_BOOT      0x4U
 #define SC_RPC_MU_GIR_DBG       0x8U
 
 #define I8(X)       ((int8_t) (X))
@@ -83,7 +85,7 @@
 
 typedef uint8_t sc_rpc_svc_t;
 
-typedef struct sc_rpc_msg_s
+typedef struct
 {
     uint8_t version;
     uint8_t size;
@@ -102,7 +104,7 @@ typedef struct sc_rpc_msg_s
 
 typedef uint8_t sc_rpc_async_state_t;
 
-typedef struct sc_rpc_async_msg_s
+typedef struct
 {
     sc_rpc_async_state_t state;
     uint8_t wordIdx;
diff --git a/arch/arm/include/asm/mach-imx/sci/svc/irq/api.h b/arch/arm/include/asm/mach-imx/sci/svc/irq/api.h
index 1508a23a3ad..439dc289451 100644
--- a/arch/arm/include/asm/mach-imx/sci/svc/irq/api.h
+++ b/arch/arm/include/asm/mach-imx/sci/svc/irq/api.h
@@ -25,17 +25,18 @@
 
 /* Defines */
 
-#define SC_IRQ_NUM_GROUP    5U          /*!< Number of groups */
+#define SC_IRQ_NUM_GROUP        6U   /*!< Number of groups */
 
 /*!
  * @name Defines for sc_irq_group_t
  */
 /*@{*/
-#define SC_IRQ_GROUP_TEMP   0U   /*!< Temp interrupts */
-#define SC_IRQ_GROUP_WDOG   1U   /*!< Watchdog interrupts */
-#define SC_IRQ_GROUP_RTC    2U   /*!< RTC interrupts */
-#define SC_IRQ_GROUP_WAKE   3U   /*!< Wakeup interrupts */
-#define SC_IRQ_GROUP_SYSCTR 4U   /*!< System counter interrupts */
+#define SC_IRQ_GROUP_TEMP       0U   /*!< Temp interrupts */
+#define SC_IRQ_GROUP_WDOG       1U   /*!< Watchdog interrupts */
+#define SC_IRQ_GROUP_RTC        2U   /*!< RTC interrupts */
+#define SC_IRQ_GROUP_WAKE       3U   /*!< Wakeup interrupts */
+#define SC_IRQ_GROUP_SYSCTR     4U   /*!< System counter interrupts */
+#define SC_IRQ_GROUP_REBOOTED   5U   /*!< Partition reboot complete */
 /*@}*/
 
 /*!
diff --git a/arch/arm/include/asm/mach-imx/sci/svc/misc/api.h b/arch/arm/include/asm/mach-imx/sci/svc/misc/api.h
index c271a2c15b0..6049b3a447a 100644
--- a/arch/arm/include/asm/mach-imx/sci/svc/misc/api.h
+++ b/arch/arm/include/asm/mach-imx/sci/svc/misc/api.h
@@ -253,6 +253,29 @@ sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
     sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr);
 
 /*!
+ * This function is used to load a SECO key.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     id          key identifier
+ * @param[in]     addr        key address
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This function is used to install private cryptographic keys encapsulated
+ * in a blob previously generated by SECO. The controller can be either the
+ * IEE or the VPU. The blob header carries the controller type and the key
+ * size, as provided by the user when generating the key blob.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_misc_seco_load_key(sc_ipc_t ipc, uint32_t id,
+    sc_faddr_t addr);
+
+/*!
  * This function securely writes a group of fuse words.
  *
  * @param[in]     ipc         IPC handle
@@ -354,6 +377,21 @@ sc_err_t sc_misc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc,
     uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h);
 
 /*!
+ * This function is used to return an event from the SECO error log.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    idx         index of event to return
+ * @param[out]    event       pointer to return event
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Read of \a idx 0 captures events from SECO. Loop starting
+ * with 0 until an error is returned to dump all events.
+ */
+sc_err_t sc_misc_seco_get_event(sc_ipc_t ipc, uint8_t idx,
+    uint32_t *event);
+
+/*!
  * This function is used to set the attestation mode. Only the owner of
  * the SC_R_ATTESTATION resource may make this call.
  *
@@ -605,7 +643,9 @@ sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu);
 sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val);
 
 /*!
- * This function writes a given fuse word index.
+ * This function writes a given fuse word index. Only the owner of the
+ * SC_R_SYSTEM resource or a partition with access permissions to
+ * SC_R_SYSTEM can do this.
  *
  * @param[in]     ipc         IPC handle
  * @param[in]     word        fuse word index
@@ -620,6 +660,7 @@ sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val);
  *
  * Return errors codes:
  * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access
  * - SC_ERR_NOACCESS if write operation failed
  * - SC_ERR_LOCKED if write operation is locked
  */
@@ -642,6 +683,8 @@ sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val);
  *
  * Return errors codes:
  * - SC_ERR_PARM if parameters invalid
+ * - SC_ERR_NOACCESS if caller does not own the resource
+ * - SC_ERR_NOPOWER if power domain of resource not powered
  */
 sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource,
     sc_misc_temp_t temp, int16_t celsius, int8_t tenths);
@@ -660,6 +703,7 @@ sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource,
  * Return errors codes:
  * - SC_ERR_PARM if parameters invalid
  * - SC_ERR_BUSY if temp not ready yet (time delay after power on)
+ * - SC_ERR_NOPOWER if power domain of resource not powered
  */
 sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
     sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths);
diff --git a/arch/arm/include/asm/mach-imx/sci/svc/pm/api.h b/arch/arm/include/asm/mach-imx/sci/svc/pm/api.h
index a68915e3855..487f9debf0f 100644
--- a/arch/arm/include/asm/mach-imx/sci/svc/pm/api.h
+++ b/arch/arm/include/asm/mach-imx/sci/svc/pm/api.h
@@ -211,7 +211,8 @@ typedef uint8_t sc_pm_wake_src_t;
 
 /*!
  * This function sets the system power mode. Only the owner of the
- * SC_R_SYSTEM resource can do this.
+ * SC_R_SYSTEM resource or a partition with access permissions to
+ * SC_R_SYSTEM can do this.
  *
  * @param[in]     ipc         IPC handle
  * @param[in]     mode        power mode to apply
@@ -220,7 +221,7 @@ typedef uint8_t sc_pm_wake_src_t;
  *
  * Return errors:
  * - SC_ERR_PARM if invalid mode,
- * - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
+ * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access
  *
  * @see sc_pm_set_sys_power_mode().
  */
@@ -574,7 +575,8 @@ sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
 
 /*!
  * This function is used to reset the system. Only the owner of the
- * SC_R_SYSTEM resource can do this.
+ * SC_R_SYSTEM resource or a partition with access permissions to
+ * SC_R_SYSTEM can do this.
  *
  * @param[in]     ipc         IPC handle
  * @param[in]     type        reset type
@@ -583,7 +585,7 @@ sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
  *
  * Return errors:
  * - SC_ERR_PARM if invalid type,
- * - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
+ * - SC_ERR_NOACCESS if caller cannot access SC_R_SYSTEM
  *
  * If this function returns, then the reset did not occur due to an
  * invalid parameter.
@@ -678,7 +680,8 @@ void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type);
  *
  * Return errors:
  * - SC_ERR_PARM if invalid partition or type
- * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt
+ *   and the caller does not have access to SC_R_SYSTEM
  *
  * Most peripherals owned by the partition will be reset if
  * possible. SC state (partitions, power, clocks, etc.) is reset. The
@@ -725,9 +728,9 @@ sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
  *
  * This function does not return anything as the calling core may have been
  * reset. It can still fail if the resource or address is invalid. It can also
- * fail if the caller's partition is not the owner of the CPU or not the
- * parent of the CPU resource owner. Will also fail if the resource is not
- * powered on. No indication of failure is returned.
+ * fail if the caller's partition is not the owner of the CPU, not the parent
+ * of the CPU resource owner, or has access to SC_R_SYSTEM. Will also fail if
+ * the resource is not powered on. No indication of failure is returned.
  *
  * Note this just resets the CPU. None of the peripherals or bus fabric used by
  * the CPU is reset. State configured in the SCFW is not reset. The SW running
diff --git a/arch/arm/include/asm/mach-imx/sci/svc/rm/api.h b/arch/arm/include/asm/mach-imx/sci/svc/rm/api.h
index a27fa95525c..a2174d8c9f7 100644
--- a/arch/arm/include/asm/mach-imx/sci/svc/rm/api.h
+++ b/arch/arm/include/asm/mach-imx/sci/svc/rm/api.h
@@ -324,7 +324,7 @@ sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
  * ASSERT if the partition si secure and NEGATE if it is not, and
  * masters will defaulted to SMMU bypass. Access permissions will reset
  * to SEC_RW for the owning partition only for secure partitions, FULL for
- * non-secure. DEfault is no access by other partitions.
+ * non-secure. Default is no access by other partitions.
  *
  * Return errors:
  * - SC_ERR_NOACCESS if caller's partition is restricted,
@@ -445,7 +445,8 @@ sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
  * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt
  *
  * This function configures how the HW isolation will restrict access to a
- * peripheral based on the attributes of a transaction from bus master.
+ * peripheral based on the attributes of a transaction from bus master. It
+ * also allows the access permissions of SC_R_SYSTEM to be set.
  */
 sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
     sc_rm_pt_t pt, sc_rm_perm_t perm);
diff --git a/arch/arm/include/asm/mach-imx/sci/svc/timer/api.h b/arch/arm/include/asm/mach-imx/sci/svc/timer/api.h
index a96f5b9cd62..bd1ccbd5bfd 100644
--- a/arch/arm/include/asm/mach-imx/sci/svc/timer/api.h
+++ b/arch/arm/include/asm/mach-imx/sci/svc/timer/api.h
@@ -190,7 +190,8 @@ sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
 
 /*!
  * This function sets the RTC time. Only the owner of the SC_R_SYSTEM
- * resource can set the time.
+ * resource or a partition with access permissions to SC_R_SYSTEM can
+ * set the time.
  *
  * @param[in]     ipc         IPC handle
  * @param[in]     year        year (min 1970)
@@ -204,7 +205,7 @@ sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
  *
  * Return errors:
  * - SC_ERR_PARM if invalid time/date parameters,
- * - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner
+ * - SC_ERR_NOACCESS if caller's partition cannot access SC_R_SYSTEM
  */
 sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
     uint8_t day, uint8_t hour, uint8_t min, uint8_t sec);
@@ -246,7 +247,8 @@ sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec);
  * @param[in]     min         minute (0-59)
  * @param[in]     sec         second (0-59)
  *
- * Note this alarm setting clears when the alarm is triggered.
+ * Note this alarm setting clears when the alarm is triggered. This is an
+ * absolute time.
  *
  * @return Returns an error code (SC_ERR_NONE = success).
  *
@@ -264,6 +266,8 @@ sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
  *
  * @return Returns an error code (SC_ERR_NONE = success).
  *
+ * Note this is a relative time.
+ *
  * Return errors:
  * - SC_ERR_PARM if invalid time/date parameters
  */
@@ -285,7 +289,8 @@ sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc);
 
 /*!
  * This function sets the RTC calibration value. Only the owner of the SC_R_SYSTEM
- * resource can set the calibration.
+ * resource or a partition with access permissions to SC_R_SYSTEM can set the
+ * calibration.
  *
  * @param[in]     ipc         IPC handle
  * @param[in]     count       calbration count (-16 to 15)
@@ -311,7 +316,8 @@ sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count);
  * @param[in]     ipc         IPC handle
  * @param[in]     ticks       number of 8MHz cycles
  *
- * Note this alarm setting clears when the alarm is triggered.
+ * Note the \a ticks parameter is an absolute time. This alarm
+ * setting clears when the alarm is triggered.
  *
  * @return Returns an error code (SC_ERR_NONE = success).
  *
@@ -326,6 +332,8 @@ sc_err_t sc_timer_set_sysctr_alarm(sc_ipc_t ipc, uint64_t ticks);
  * @param[in]     ipc          IPC handle
  * @param[in]     ticks        number of 8MHz cycles
  *
+ * Note the \a ticks parameter is a relative time.
+ *
  * @return Returns an error code (SC_ERR_NONE = success).
  *
  * Return errors:
diff --git a/arch/arm/mach-imx/sci/svc/misc/rpc.h b/arch/arm/mach-imx/sci/svc/misc/rpc.h
index 614f06bd71f..8faae860bc1 100644
--- a/arch/arm/mach-imx/sci/svc/misc/rpc.h
+++ b/arch/arm/mach-imx/sci/svc/misc/rpc.h
@@ -30,12 +30,14 @@
 #define MISC_FUNC_SET_DMA_GROUP 5U /*!< Index for misc_set_dma_group() RPC call */
 #define MISC_FUNC_SECO_IMAGE_LOAD 8U /*!< Index for misc_seco_image_load() RPC call */
 #define MISC_FUNC_SECO_AUTHENTICATE 9U /*!< Index for misc_seco_authenticate() RPC call */
+#define MISC_FUNC_SECO_LOAD_KEY 34U /*!< Index for misc_seco_load_key() RPC call */
 #define MISC_FUNC_SECO_FUSE_WRITE 20U /*!< Index for misc_seco_fuse_write() RPC call */
 #define MISC_FUNC_SECO_ENABLE_DEBUG 21U /*!< Index for misc_seco_enable_debug() RPC call */
 #define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U /*!< Index for misc_seco_forward_lifecycle() RPC call */
 #define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U /*!< Index for misc_seco_return_lifecycle() RPC call */
 #define MISC_FUNC_SECO_BUILD_INFO 24U /*!< Index for misc_seco_build_info() RPC call */
 #define MISC_FUNC_SECO_CHIP_INFO 25U /*!< Index for misc_seco_chip_info() RPC call */
+#define MISC_FUNC_SECO_GET_EVENT 35U /*!< Index for misc_seco_get_event() RPC call */
 #define MISC_FUNC_SECO_ATTEST_MODE 27U /*!< Index for misc_seco_attest_mode() RPC call */
 #define MISC_FUNC_SECO_ATTEST 28U /*!< Index for misc_seco_attest() RPC call */
 #define MISC_FUNC_SECO_GET_ATTEST_PKEY 31U /*!< Index for misc_seco_get_attest_pkey() RPC call */
diff --git a/arch/arm/mach-imx/sci/svc/misc/rpc_clnt.c b/arch/arm/mach-imx/sci/svc/misc/rpc_clnt.c
index d6d0744d751..e85258839e7 100644
--- a/arch/arm/mach-imx/sci/svc/misc/rpc_clnt.c
+++ b/arch/arm/mach-imx/sci/svc/misc/rpc_clnt.c
@@ -152,6 +152,26 @@ sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
     return (sc_err_t) result;
 }
 
+sc_err_t sc_misc_seco_load_key(sc_ipc_t ipc, uint32_t id,
+    sc_faddr_t addr)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+    RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_LOAD_KEY);
+    RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+    RPC_U32(&msg, 4U) = U32(addr);
+    RPC_U32(&msg, 8U) = U32(id);
+    RPC_SIZE(&msg) = 4U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
 sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr)
 {
     sc_rpc_msg_t msg;
@@ -285,6 +305,29 @@ sc_err_t sc_misc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc,
     return (sc_err_t) result;
 }
 
+sc_err_t sc_misc_seco_get_event(sc_ipc_t ipc, uint8_t idx,
+    uint32_t *event)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+    RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_GET_EVENT);
+    RPC_U8(&msg, 0U) = U8(idx);
+    RPC_SIZE(&msg) = 2U;
+
+    sc_call_rpc(ipc, &msg, SC_FALSE);
+
+    if (event != NULL)
+    {
+        *event = RPC_U32(&msg, 0U);
+    }
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
 sc_err_t sc_misc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode)
 {
     sc_rpc_msg_t msg;